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arm: dts: mt7623: add Mali-450 device node
Add a node for Mali-450. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Link: https://lore.kernel.org/r/af7b5a2e00eb3a4b6262807c378e43afd5f74779.1563867856.git.ryder.lee@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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@ -3,6 +3,7 @@
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* Copyright (c) 2017-2018 MediaTek Inc.
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* Author: John Crispin <john@phrozen.org>
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* Sean Wang <sean.wang@mediatek.com>
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* Ryder Lee <ryder.lee@mediatek.com>
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*
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*/
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@ -733,6 +734,30 @@ g3dsys: syscon@13000000 {
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#reset-cells = <1>;
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};
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mali: gpu@13040000 {
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compatible = "mediatek,mt7623-mali", "arm,mali-450";
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reg = <0 0x13040000 0 0x30000>;
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interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 172 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 173 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 174 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 177 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 178 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 179 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
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interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
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"ppmmu1", "pp2", "ppmmu2", "pp3", "ppmmu3",
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"pp";
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clocks = <&topckgen CLK_TOP_MMPLL>,
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<&g3dsys CLK_G3DSYS_CORE>;
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clock-names = "bus", "core";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>;
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resets = <&g3dsys MT2701_G3DSYS_CORE_RST>;
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};
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mmsys: syscon@14000000 {
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compatible = "mediatek,mt7623-mmsys",
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"mediatek,mt2701-mmsys",
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