mirror of https://gitee.com/openkylin/linux.git
firmware: qcom_scm-64: Add SCM results struct
Remove knowledge of arm_smccc_res struct from client wrappers so that client wrappers only work QCOM SCM data structures. SCM calls may have up to 3 arguments, so qcom_scm_call_smccc is responsible now for filling those 3 arguments accordingly. This is necessary to support merging legacy and SMC conventions in an upcoming patch. Tested-by: Brian Masney <masneyb@onstation.org> # arm32 Tested-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Elliot Berman <eberman@codeaurora.org> Link: https://lore.kernel.org/r/1578431066-19600-7-git-send-email-eberman@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
Elliot Berman
Bjorn Andersson
parent
b30a2a72b8
commit
1f7166fdae
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@ -45,7 +45,6 @@ enum qcom_scm_arg_types {
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* struct qcom_scm_desc
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* @arginfo: Metadata describing the arguments in args[]
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* @args: The array of arguments for the secure syscall
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* @res: The values returned by the secure syscall
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*/
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struct qcom_scm_desc {
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u32 svc;
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@ -55,6 +54,14 @@ struct qcom_scm_desc {
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u32 owner;
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};
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/**
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* struct qcom_scm_res
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* @result: The values returned by the secure syscall
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*/
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struct qcom_scm_res {
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u64 result[MAX_QCOM_SCM_RETS];
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};
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static u64 qcom_smccc_convention = -1;
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static DEFINE_MUTEX(qcom_scm_lock);
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@ -116,7 +123,7 @@ static void __scm_smc_do(const struct qcom_scm_desc *desc,
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}
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static int __scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc,
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struct arm_smccc_res *res, bool atomic)
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struct qcom_scm_res *res, bool atomic)
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{
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int arglen = desc->arginfo & 0xf;
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int i;
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@ -125,6 +132,7 @@ static int __scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc,
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void *args_virt = NULL;
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size_t alloc_len;
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gfp_t flag = atomic ? GFP_ATOMIC : GFP_KERNEL;
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struct arm_smccc_res smc_res;
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if (unlikely(arglen > SCM_SMC_N_REG_ARGS)) {
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alloc_len = SCM_SMC_N_EXT_ARGS * sizeof(u64);
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@ -158,17 +166,20 @@ static int __scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc,
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x5 = args_phys;
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}
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__scm_smc_do(desc, res, x5, atomic);
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__scm_smc_do(desc, &smc_res, x5, atomic);
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if (args_virt) {
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dma_unmap_single(dev, args_phys, alloc_len, DMA_TO_DEVICE);
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kfree(args_virt);
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}
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if ((long)res->a0 < 0)
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return qcom_scm_remap_error(res->a0);
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if (res) {
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res->result[0] = smc_res.a1;
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res->result[1] = smc_res.a2;
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res->result[2] = smc_res.a3;
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}
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return 0;
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return (long)smc_res.a0 ? qcom_scm_remap_error(smc_res.a0) : 0;
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}
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/**
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@ -182,7 +193,7 @@ static int __scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc,
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* This should *only* be called in pre-emptible context.
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*/
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static int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc,
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struct arm_smccc_res *res)
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struct qcom_scm_res *res)
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{
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might_sleep();
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return __scm_smc_call(dev, desc, res, false);
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@ -201,7 +212,7 @@ static int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc,
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*/
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static int qcom_scm_call_atomic(struct device *dev,
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const struct qcom_scm_desc *desc,
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struct arm_smccc_res *res)
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struct qcom_scm_res *res)
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{
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return __scm_smc_call(dev, desc, res, true);
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}
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@ -254,7 +265,7 @@ int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id)
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.cmd = QCOM_SCM_INFO_IS_CALL_AVAIL,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct arm_smccc_res res;
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struct qcom_scm_res res;
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desc.arginfo = QCOM_SCM_ARGS(1);
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desc.args[0] = SCM_SMC_FNID(svc_id, cmd_id) |
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@ -262,7 +273,7 @@ int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id)
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ret = qcom_scm_call(dev, &desc, &res);
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return ret ? : res.a1;
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return ret ? : res.result[0];
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}
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int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req,
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@ -274,7 +285,7 @@ int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req,
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.cmd = QCOM_SCM_HDCP_INVOKE,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct arm_smccc_res res;
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struct qcom_scm_res res;
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if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT)
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return -ERANGE;
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@ -292,7 +303,7 @@ int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req,
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desc.arginfo = QCOM_SCM_ARGS(10);
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ret = qcom_scm_call(dev, &desc, &res);
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*resp = res.a1;
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*resp = res.result[0];
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return ret;
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}
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@ -336,14 +347,14 @@ bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral)
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.cmd = QCOM_SCM_PIL_PAS_IS_SUPPORTED,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct arm_smccc_res res;
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struct qcom_scm_res res;
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desc.args[0] = peripheral;
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desc.arginfo = QCOM_SCM_ARGS(1);
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ret = qcom_scm_call(dev, &desc, &res);
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return ret ? false : !!res.a1;
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return ret ? false : !!res.result[0];
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}
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int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral,
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@ -355,7 +366,7 @@ int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral,
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.cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct arm_smccc_res res;
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struct qcom_scm_res res;
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desc.args[0] = peripheral;
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desc.args[1] = metadata_phys;
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@ -363,7 +374,7 @@ int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral,
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ret = qcom_scm_call(dev, &desc, &res);
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return ret ? : res.a1;
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return ret ? : res.result[0];
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}
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int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral,
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@ -375,7 +386,7 @@ int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral,
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.cmd = QCOM_SCM_PIL_PAS_MEM_SETUP,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct arm_smccc_res res;
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struct qcom_scm_res res;
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desc.args[0] = peripheral;
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desc.args[1] = addr;
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@ -384,7 +395,7 @@ int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral,
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ret = qcom_scm_call(dev, &desc, &res);
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return ret ? : res.a1;
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return ret ? : res.result[0];
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}
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int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral)
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@ -395,14 +406,14 @@ int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral)
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.cmd = QCOM_SCM_PIL_PAS_AUTH_AND_RESET,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct arm_smccc_res res;
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struct qcom_scm_res res;
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desc.args[0] = peripheral;
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desc.arginfo = QCOM_SCM_ARGS(1);
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ret = qcom_scm_call(dev, &desc, &res);
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return ret ? : res.a1;
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return ret ? : res.result[0];
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}
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int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral)
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@ -413,14 +424,14 @@ int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral)
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.cmd = QCOM_SCM_PIL_PAS_SHUTDOWN,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct arm_smccc_res res;
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struct qcom_scm_res res;
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desc.args[0] = peripheral;
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desc.arginfo = QCOM_SCM_ARGS(1);
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ret = qcom_scm_call(dev, &desc, &res);
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return ret ? : res.a1;
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return ret ? : res.result[0];
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}
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int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)
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@ -430,7 +441,7 @@ int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)
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.cmd = QCOM_SCM_PIL_PAS_MSS_RESET,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct arm_smccc_res res;
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struct qcom_scm_res res;
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int ret;
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desc.args[0] = reset;
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@ -439,7 +450,7 @@ int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)
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ret = qcom_scm_call(dev, &desc, &res);
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return ret ? : res.a1;
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return ret ? : res.result[0];
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}
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int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id)
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@ -449,7 +460,7 @@ int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id)
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.cmd = QCOM_SCM_BOOT_SET_REMOTE_STATE,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct arm_smccc_res res;
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struct qcom_scm_res res;
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int ret;
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desc.args[0] = state;
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@ -458,7 +469,7 @@ int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id)
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ret = qcom_scm_call(dev, &desc, &res);
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return ret ? : res.a1;
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return ret ? : res.result[0];
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}
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int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region,
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@ -471,7 +482,7 @@ int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region,
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.cmd = QCOM_SCM_MP_ASSIGN,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct arm_smccc_res res;
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struct qcom_scm_res res;
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desc.args[0] = mem_region;
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desc.args[1] = mem_sz;
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@ -487,7 +498,7 @@ int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region,
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ret = qcom_scm_call(dev, &desc, &res);
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return ret ? : res.a1;
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return ret ? : res.result[0];
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}
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int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id, u32 spare)
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@ -497,7 +508,7 @@ int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id, u32 spare)
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.cmd = QCOM_SCM_MP_RESTORE_SEC_CFG,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct arm_smccc_res res;
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struct qcom_scm_res res;
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int ret;
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desc.args[0] = device_id;
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@ -506,7 +517,7 @@ int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id, u32 spare)
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ret = qcom_scm_call(dev, &desc, &res);
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return ret ? : res.a1;
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return ret ? : res.result[0];
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}
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int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,
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@ -517,7 +528,7 @@ int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,
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.cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct arm_smccc_res res;
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struct qcom_scm_res res;
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int ret;
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desc.args[0] = spare;
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@ -526,9 +537,9 @@ int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,
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ret = qcom_scm_call(dev, &desc, &res);
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if (size)
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*size = res.a1;
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*size = res.result[0];
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return ret ? : res.a2;
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return ret ? : res.result[1];
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}
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int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size,
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@ -539,7 +550,6 @@ int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size,
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.cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct arm_smccc_res res;
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int ret;
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desc.args[0] = addr;
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@ -548,7 +558,7 @@ int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size,
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desc.arginfo = QCOM_SCM_ARGS(3, QCOM_SCM_RW, QCOM_SCM_VAL,
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QCOM_SCM_VAL);
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ret = qcom_scm_call(dev, &desc, &res);
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ret = qcom_scm_call(dev, &desc, NULL);
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/* the pg table has been initialized already, ignore the error */
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if (ret == -EPERM)
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@ -564,13 +574,12 @@ int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
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.cmd = QCOM_SCM_BOOT_SET_DLOAD_MODE,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct arm_smccc_res res;
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desc.args[0] = QCOM_SCM_BOOT_SET_DLOAD_MODE;
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desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0;
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desc.arginfo = QCOM_SCM_ARGS(2);
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return qcom_scm_call(dev, &desc, &res);
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return qcom_scm_call(dev, &desc, NULL);
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}
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int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr,
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@ -581,7 +590,7 @@ int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr,
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.cmd = QCOM_SCM_IO_READ,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct arm_smccc_res res;
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struct qcom_scm_res res;
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int ret;
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desc.args[0] = addr;
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@ -589,7 +598,7 @@ int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr,
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ret = qcom_scm_call(dev, &desc, &res);
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if (ret >= 0)
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*val = res.a1;
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*val = res.result[0];
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return ret < 0 ? ret : 0;
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}
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@ -601,13 +610,12 @@ int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val)
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.cmd = QCOM_SCM_IO_WRITE,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct arm_smccc_res res;
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desc.args[0] = addr;
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desc.args[1] = val;
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desc.arginfo = QCOM_SCM_ARGS(2);
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return qcom_scm_call(dev, &desc, &res);
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return qcom_scm_call(dev, &desc, NULL);
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}
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int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev, bool en)
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@ -617,11 +625,10 @@ int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev, bool en)
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.cmd = QCOM_SCM_SMMU_CONFIG_ERRATA1,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct arm_smccc_res res;
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desc.args[0] = QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL;
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desc.args[1] = en;
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desc.arginfo = QCOM_SCM_ARGS(2);
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return qcom_scm_call_atomic(dev, &desc, &res);
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return qcom_scm_call_atomic(dev, &desc, NULL);
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}
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