mirror of https://gitee.com/openkylin/linux.git
drm/amd/powerplay: add basic powerplay framework
amdgpu_pp_ip_funcs is introduced to handle the two code paths, the legacy one and the new powerplay implementation. CONFIG_DRM_AMD_POWERPLAY kernel configuration option is introduced for the powerplay component. v4: squash in fixes v3: register debugfs file when powerplay module enable v2: add amdgpu_ucode_init_bo in hw init when amdgpu_powerplay enable. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
47bf18b5b2
commit
1f7371b2a5
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@ -160,6 +160,7 @@ config DRM_AMDGPU
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If M is selected, the module will be called amdgpu.
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source "drivers/gpu/drm/amd/amdgpu/Kconfig"
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source "drivers/gpu/drm/amd/powerplay/Kconfig"
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source "drivers/gpu/drm/nouveau/Kconfig"
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@ -7,7 +7,8 @@ FULL_AMD_PATH=$(src)/..
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ccflags-y := -Iinclude/drm -I$(FULL_AMD_PATH)/include/asic_reg \
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-I$(FULL_AMD_PATH)/include \
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-I$(FULL_AMD_PATH)/amdgpu \
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-I$(FULL_AMD_PATH)/scheduler
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-I$(FULL_AMD_PATH)/scheduler \
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-I$(FULL_AMD_PATH)/powerplay/inc
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amdgpu-y := amdgpu_drv.o
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@ -46,6 +47,7 @@ amdgpu-y += \
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# add SMC block
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amdgpu-y += \
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amdgpu_dpm.o \
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amdgpu_powerplay.o \
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cz_smc.o cz_dpm.o \
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tonga_smc.o tonga_dpm.o \
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fiji_smc.o fiji_dpm.o \
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@ -96,6 +98,14 @@ amdgpu-$(CONFIG_VGA_SWITCHEROO) += amdgpu_atpx_handler.o
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amdgpu-$(CONFIG_ACPI) += amdgpu_acpi.o
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amdgpu-$(CONFIG_MMU_NOTIFIER) += amdgpu_mn.o
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ifneq ($(CONFIG_DRM_AMD_POWERPLAY),)
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include drivers/gpu/drm/amd/powerplay/Makefile
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amdgpu-y += $(AMD_POWERPLAY_FILES)
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endif
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obj-$(CONFIG_DRM_AMDGPU)+= amdgpu.o
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CFLAGS_amdgpu_trace_points.o := -I$(src)
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@ -52,6 +52,7 @@
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#include "amdgpu_irq.h"
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#include "amdgpu_ucode.h"
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#include "amdgpu_gds.h"
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#include "amd_powerplay.h"
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#include "gpu_scheduler.h"
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@ -85,6 +86,7 @@ extern int amdgpu_enable_scheduler;
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extern int amdgpu_sched_jobs;
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extern int amdgpu_sched_hw_submission;
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extern int amdgpu_enable_semaphores;
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extern int amdgpu_powerplay;
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#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
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#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
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@ -2036,6 +2038,9 @@ struct amdgpu_device {
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/* interrupts */
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struct amdgpu_irq irq;
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/* powerplay */
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struct amd_powerplay powerplay;
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/* dpm */
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struct amdgpu_pm pm;
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u32 cg_flags;
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@ -82,6 +82,7 @@ int amdgpu_enable_scheduler = 1;
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int amdgpu_sched_jobs = 32;
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int amdgpu_sched_hw_submission = 2;
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int amdgpu_enable_semaphores = 0;
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int amdgpu_powerplay = 0;
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MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
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module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
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@ -0,0 +1,280 @@
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/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "atom.h"
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#include "amdgpu.h"
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#include "amd_shared.h"
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include "amdgpu_pm.h"
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#include <drm/amdgpu_drm.h>
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#include "amdgpu_powerplay.h"
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#include "cik_dpm.h"
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#include "vi_dpm.h"
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static int amdgpu_powerplay_init(struct amdgpu_device *adev)
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{
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int ret = 0;
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struct amd_powerplay *amd_pp;
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amd_pp = &(adev->powerplay);
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if (amdgpu_powerplay) {
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#ifdef CONFIG_DRM_AMD_POWERPLAY
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struct amd_pp_init *pp_init;
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pp_init = kzalloc(sizeof(struct amd_pp_init), GFP_KERNEL);
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if (pp_init == NULL)
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return -ENOMEM;
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pp_init->chip_family = adev->family;
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pp_init->chip_id = adev->asic_type;
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pp_init->device = amdgpu_cgs_create_device(adev);
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ret = amd_powerplay_init(pp_init, amd_pp);
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kfree(pp_init);
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#endif
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} else {
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amd_pp->pp_handle = (void *)adev;
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switch (adev->asic_type) {
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#ifdef CONFIG_DRM_AMDGPU_CIK
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case CHIP_BONAIRE:
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case CHIP_HAWAII:
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amd_pp->ip_funcs = &ci_dpm_ip_funcs;
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break;
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case CHIP_KABINI:
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case CHIP_MULLINS:
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case CHIP_KAVERI:
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amd_pp->ip_funcs = &kv_dpm_ip_funcs;
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break;
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#endif
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case CHIP_TOPAZ:
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amd_pp->ip_funcs = &iceland_dpm_ip_funcs;
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break;
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case CHIP_TONGA:
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amd_pp->ip_funcs = &tonga_dpm_ip_funcs;
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break;
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case CHIP_CARRIZO:
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amd_pp->ip_funcs = &cz_dpm_ip_funcs;
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break;
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default:
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ret = -EINVAL;
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break;
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}
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}
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return ret;
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}
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static int amdgpu_pp_early_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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int ret = 0;
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ret = amdgpu_powerplay_init(adev);
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if (ret)
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return ret;
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if (adev->powerplay.ip_funcs->early_init)
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ret = adev->powerplay.ip_funcs->early_init(
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adev->powerplay.pp_handle);
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return ret;
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}
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static int amdgpu_pp_sw_init(void *handle)
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{
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int ret = 0;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (adev->powerplay.ip_funcs->sw_init)
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ret = adev->powerplay.ip_funcs->sw_init(
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adev->powerplay.pp_handle);
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#ifdef CONFIG_DRM_AMD_POWERPLAY
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if (amdgpu_powerplay) {
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adev->pm.dpm_enabled = true;
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amdgpu_pm_sysfs_init(adev);
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}
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#endif
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return ret;
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}
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static int amdgpu_pp_sw_fini(void *handle)
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{
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int ret = 0;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (adev->powerplay.ip_funcs->sw_fini)
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ret = adev->powerplay.ip_funcs->sw_fini(
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adev->powerplay.pp_handle);
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if (ret)
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return ret;
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#ifdef CONFIG_DRM_AMD_POWERPLAY
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if (amdgpu_powerplay) {
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amdgpu_pm_sysfs_fini(adev);
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amd_powerplay_fini(adev->powerplay.pp_handle);
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}
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#endif
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return ret;
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}
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static int amdgpu_pp_hw_init(void *handle)
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{
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int ret = 0;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (amdgpu_powerplay && adev->firmware.smu_load)
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amdgpu_ucode_init_bo(adev);
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if (adev->powerplay.ip_funcs->hw_init)
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ret = adev->powerplay.ip_funcs->hw_init(
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adev->powerplay.pp_handle);
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return ret;
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}
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static int amdgpu_pp_hw_fini(void *handle)
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{
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int ret = 0;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (adev->powerplay.ip_funcs->hw_fini)
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ret = adev->powerplay.ip_funcs->hw_fini(
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adev->powerplay.pp_handle);
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if (amdgpu_powerplay && adev->firmware.smu_load)
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amdgpu_ucode_fini_bo(adev);
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return ret;
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}
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static int amdgpu_pp_suspend(void *handle)
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{
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int ret = 0;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (adev->powerplay.ip_funcs->suspend)
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ret = adev->powerplay.ip_funcs->suspend(
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adev->powerplay.pp_handle);
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return ret;
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}
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static int amdgpu_pp_resume(void *handle)
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{
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int ret = 0;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (adev->powerplay.ip_funcs->resume)
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ret = adev->powerplay.ip_funcs->resume(
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adev->powerplay.pp_handle);
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return ret;
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}
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static int amdgpu_pp_set_clockgating_state(void *handle,
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enum amd_clockgating_state state)
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{
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int ret = 0;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (adev->powerplay.ip_funcs->set_clockgating_state)
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ret = adev->powerplay.ip_funcs->set_clockgating_state(
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adev->powerplay.pp_handle, state);
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return ret;
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}
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static int amdgpu_pp_set_powergating_state(void *handle,
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enum amd_powergating_state state)
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{
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int ret = 0;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (adev->powerplay.ip_funcs->set_powergating_state)
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ret = adev->powerplay.ip_funcs->set_powergating_state(
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adev->powerplay.pp_handle, state);
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return ret;
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}
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static bool amdgpu_pp_is_idle(void *handle)
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{
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bool ret = true;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (adev->powerplay.ip_funcs->is_idle)
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ret = adev->powerplay.ip_funcs->is_idle(
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adev->powerplay.pp_handle);
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return ret;
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}
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static int amdgpu_pp_wait_for_idle(void *handle)
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{
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int ret = 0;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (adev->powerplay.ip_funcs->wait_for_idle)
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ret = adev->powerplay.ip_funcs->wait_for_idle(
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adev->powerplay.pp_handle);
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return ret;
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}
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static int amdgpu_pp_soft_reset(void *handle)
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{
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int ret = 0;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (adev->powerplay.ip_funcs->soft_reset)
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ret = adev->powerplay.ip_funcs->soft_reset(
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adev->powerplay.pp_handle);
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return ret;
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}
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static void amdgpu_pp_print_status(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (adev->powerplay.ip_funcs->print_status)
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adev->powerplay.ip_funcs->print_status(
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adev->powerplay.pp_handle);
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}
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const struct amd_ip_funcs amdgpu_pp_ip_funcs = {
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.early_init = amdgpu_pp_early_init,
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.late_init = NULL,
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.sw_init = amdgpu_pp_sw_init,
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.sw_fini = amdgpu_pp_sw_fini,
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.hw_init = amdgpu_pp_hw_init,
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.hw_fini = amdgpu_pp_hw_fini,
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.suspend = amdgpu_pp_suspend,
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.resume = amdgpu_pp_resume,
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.is_idle = amdgpu_pp_is_idle,
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.wait_for_idle = amdgpu_pp_wait_for_idle,
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.soft_reset = amdgpu_pp_soft_reset,
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.print_status = amdgpu_pp_print_status,
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.set_clockgating_state = amdgpu_pp_set_clockgating_state,
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.set_powergating_state = amdgpu_pp_set_powergating_state,
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};
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@ -0,0 +1,33 @@
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/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
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* OTHER DEALINGS IN THE SOFTWARE.
|
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*
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* Authors: AMD
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*
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*/
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#ifndef __AMDGPU_POPWERPLAY_H__
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#define __AMDGPU_POPWERPLAY_H__
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#include "amd_shared.h"
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extern const struct amd_ip_funcs amdgpu_pp_ip_funcs;
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#endif /* __AMDSOC_DM_H__ */
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@ -65,6 +65,7 @@
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#include "oss/oss_2_0_sh_mask.h"
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#include "amdgpu_amdkfd.h"
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#include "amdgpu_powerplay.h"
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/*
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* Indirect registers accessor
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@ -1953,7 +1954,7 @@ static const struct amdgpu_ip_block_version bonaire_ip_blocks[] =
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.major = 7,
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.minor = 0,
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.rev = 0,
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.funcs = &ci_dpm_ip_funcs,
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.funcs = &amdgpu_pp_ip_funcs,
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},
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{
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.type = AMD_IP_BLOCK_TYPE_DCE,
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@ -2021,7 +2022,7 @@ static const struct amdgpu_ip_block_version hawaii_ip_blocks[] =
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.major = 7,
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.minor = 0,
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.rev = 0,
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.funcs = &ci_dpm_ip_funcs,
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.funcs = &amdgpu_pp_ip_funcs,
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},
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{
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.type = AMD_IP_BLOCK_TYPE_DCE,
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@ -2089,7 +2090,7 @@ static const struct amdgpu_ip_block_version kabini_ip_blocks[] =
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.major = 7,
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.minor = 0,
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.rev = 0,
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.funcs = &kv_dpm_ip_funcs,
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.funcs = &amdgpu_pp_ip_funcs,
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},
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{
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.type = AMD_IP_BLOCK_TYPE_DCE,
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@ -2157,7 +2158,7 @@ static const struct amdgpu_ip_block_version mullins_ip_blocks[] =
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.major = 7,
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.minor = 0,
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.rev = 0,
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.funcs = &kv_dpm_ip_funcs,
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.funcs = &amdgpu_pp_ip_funcs,
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},
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{
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.type = AMD_IP_BLOCK_TYPE_DCE,
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@ -2225,7 +2226,7 @@ static const struct amdgpu_ip_block_version kaveri_ip_blocks[] =
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.major = 7,
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.minor = 0,
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.rev = 0,
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.funcs = &kv_dpm_ip_funcs,
|
||||
.funcs = &amdgpu_pp_ip_funcs,
|
||||
},
|
||||
{
|
||||
.type = AMD_IP_BLOCK_TYPE_DCE,
|
||||
|
|
|
@ -71,6 +71,7 @@
|
|||
#include "uvd_v5_0.h"
|
||||
#include "uvd_v6_0.h"
|
||||
#include "vce_v3_0.h"
|
||||
#include "amdgpu_powerplay.h"
|
||||
|
||||
/*
|
||||
* Indirect registers accessor
|
||||
|
@ -1130,7 +1131,7 @@ static const struct amdgpu_ip_block_version topaz_ip_blocks[] =
|
|||
.major = 7,
|
||||
.minor = 1,
|
||||
.rev = 0,
|
||||
.funcs = &iceland_dpm_ip_funcs,
|
||||
.funcs = &amdgpu_pp_ip_funcs,
|
||||
},
|
||||
{
|
||||
.type = AMD_IP_BLOCK_TYPE_GFX,
|
||||
|
@ -1177,7 +1178,7 @@ static const struct amdgpu_ip_block_version tonga_ip_blocks[] =
|
|||
.major = 7,
|
||||
.minor = 1,
|
||||
.rev = 0,
|
||||
.funcs = &tonga_dpm_ip_funcs,
|
||||
.funcs = &amdgpu_pp_ip_funcs,
|
||||
},
|
||||
{
|
||||
.type = AMD_IP_BLOCK_TYPE_DCE,
|
||||
|
@ -1313,7 +1314,7 @@ static const struct amdgpu_ip_block_version cz_ip_blocks[] =
|
|||
.major = 8,
|
||||
.minor = 0,
|
||||
.rev = 0,
|
||||
.funcs = &cz_dpm_ip_funcs,
|
||||
.funcs = &amdgpu_pp_ip_funcs
|
||||
},
|
||||
{
|
||||
.type = AMD_IP_BLOCK_TYPE_DCE,
|
||||
|
|
|
@ -0,0 +1,6 @@
|
|||
config DRM_AMD_POWERPLAY
|
||||
bool "Enable AMD powerplay component"
|
||||
depends on DRM_AMDGPU
|
||||
default n
|
||||
help
|
||||
select this option will enable AMD powerplay component.
|
|
@ -0,0 +1,15 @@
|
|||
|
||||
subdir-ccflags-y += -Iinclude/drm \
|
||||
-Idrivers/gpu/drm/amd/powerplay/inc/ \
|
||||
-Idrivers/gpu/drm/amd/include/asic_reg \
|
||||
-Idrivers/gpu/drm/amd/include
|
||||
|
||||
AMD_PP_PATH = ../powerplay
|
||||
|
||||
include $(AMD_POWERPLAY)
|
||||
|
||||
POWER_MGR = amd_powerplay.o
|
||||
|
||||
AMD_PP_POWER = $(addprefix $(AMD_PP_PATH)/,$(POWER_MGR))
|
||||
|
||||
AMD_POWERPLAY_FILES += $(AMD_PP_POWER)
|
|
@ -0,0 +1,194 @@
|
|||
/*
|
||||
* Copyright 2015 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
#include <linux/types.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/gfp.h>
|
||||
#include "amd_shared.h"
|
||||
#include "amd_powerplay.h"
|
||||
|
||||
static int pp_early_init(void *handle)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pp_sw_init(void *handle)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pp_sw_fini(void *handle)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pp_hw_init(void *handle)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pp_hw_fini(void *handle)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static bool pp_is_idle(void *handle)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pp_wait_for_idle(void *handle)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pp_sw_reset(void *handle)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void pp_print_status(void *handle)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
static int pp_set_clockgating_state(void *handle,
|
||||
enum amd_clockgating_state state)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pp_set_powergating_state(void *handle,
|
||||
enum amd_powergating_state state)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pp_suspend(void *handle)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pp_resume(void *handle)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct amd_ip_funcs pp_ip_funcs = {
|
||||
.early_init = pp_early_init,
|
||||
.late_init = NULL,
|
||||
.sw_init = pp_sw_init,
|
||||
.sw_fini = pp_sw_fini,
|
||||
.hw_init = pp_hw_init,
|
||||
.hw_fini = pp_hw_fini,
|
||||
.suspend = pp_suspend,
|
||||
.resume = pp_resume,
|
||||
.is_idle = pp_is_idle,
|
||||
.wait_for_idle = pp_wait_for_idle,
|
||||
.soft_reset = pp_sw_reset,
|
||||
.print_status = pp_print_status,
|
||||
.set_clockgating_state = pp_set_clockgating_state,
|
||||
.set_powergating_state = pp_set_powergating_state,
|
||||
};
|
||||
|
||||
static int pp_dpm_load_fw(void *handle)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pp_dpm_fw_loading_complete(void *handle)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pp_dpm_force_performance_level(void *handle,
|
||||
enum amd_dpm_forced_level level)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static enum amd_dpm_forced_level pp_dpm_get_performance_level(
|
||||
void *handle)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static int pp_dpm_get_sclk(void *handle, bool low)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static int pp_dpm_get_mclk(void *handle, bool low)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static int pp_dpm_powergate_vce(void *handle, bool gate)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static int pp_dpm_powergate_uvd(void *handle, bool gate)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id, void *input, void *output)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static void
|
||||
pp_debugfs_print_current_performance_level(void *handle,
|
||||
struct seq_file *m)
|
||||
{
|
||||
return;
|
||||
}
|
||||
const struct amd_powerplay_funcs pp_dpm_funcs = {
|
||||
.get_temperature = NULL,
|
||||
.load_firmware = pp_dpm_load_fw,
|
||||
.wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
|
||||
.force_performance_level = pp_dpm_force_performance_level,
|
||||
.get_performance_level = pp_dpm_get_performance_level,
|
||||
.get_current_power_state = pp_dpm_get_current_power_state,
|
||||
.get_sclk = pp_dpm_get_sclk,
|
||||
.get_mclk = pp_dpm_get_mclk,
|
||||
.powergate_vce = pp_dpm_powergate_vce,
|
||||
.powergate_uvd = pp_dpm_powergate_uvd,
|
||||
.dispatch_tasks = pp_dpm_dispatch_tasks,
|
||||
.print_current_performance_level = pp_debugfs_print_current_performance_level,
|
||||
};
|
||||
|
||||
int amd_powerplay_init(struct amd_pp_init *pp_init,
|
||||
struct amd_powerplay *amd_pp)
|
||||
{
|
||||
if (pp_init == NULL || amd_pp == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
amd_pp->ip_funcs = &pp_ip_funcs;
|
||||
amd_pp->pp_funcs = &pp_dpm_funcs;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int amd_powerplay_fini(void *handle)
|
||||
{
|
||||
return 0;
|
||||
}
|
|
@ -0,0 +1,162 @@
|
|||
/*
|
||||
* Copyright 2015 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
#ifndef _AMD_POWERPLAY_H_
|
||||
#define _AMD_POWERPLAY_H_
|
||||
|
||||
#include <linux/seq_file.h>
|
||||
#include <linux/types.h>
|
||||
#include "amd_shared.h"
|
||||
#include "cgs_common.h"
|
||||
|
||||
|
||||
enum amd_pp_event {
|
||||
AMD_PP_EVENT_INITIALIZE = 0,
|
||||
AMD_PP_EVENT_UNINITIALIZE,
|
||||
AMD_PP_EVENT_POWER_SOURCE_CHANGE,
|
||||
AMD_PP_EVENT_SUSPEND,
|
||||
AMD_PP_EVENT_RESUME,
|
||||
AMD_PP_EVENT_ENTER_REST_STATE,
|
||||
AMD_PP_EVENT_EXIT_REST_STATE,
|
||||
AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE,
|
||||
AMD_PP_EVENT_THERMAL_NOTIFICATION,
|
||||
AMD_PP_EVENT_VBIOS_NOTIFICATION,
|
||||
AMD_PP_EVENT_ENTER_THERMAL_STATE,
|
||||
AMD_PP_EVENT_EXIT_THERMAL_STATE,
|
||||
AMD_PP_EVENT_ENTER_FORCED_STATE,
|
||||
AMD_PP_EVENT_EXIT_FORCED_STATE,
|
||||
AMD_PP_EVENT_ENTER_EXCLUSIVE_MODE,
|
||||
AMD_PP_EVENT_EXIT_EXCLUSIVE_MODE,
|
||||
AMD_PP_EVENT_ENTER_SCREEN_SAVER,
|
||||
AMD_PP_EVENT_EXIT_SCREEN_SAVER,
|
||||
AMD_PP_EVENT_VPU_RECOVERY_BEGIN,
|
||||
AMD_PP_EVENT_VPU_RECOVERY_END,
|
||||
AMD_PP_EVENT_ENABLE_POWER_PLAY,
|
||||
AMD_PP_EVENT_DISABLE_POWER_PLAY,
|
||||
AMD_PP_EVENT_CHANGE_POWER_SOURCE_UI_LABEL,
|
||||
AMD_PP_EVENT_ENABLE_USER2D_PERFORMANCE,
|
||||
AMD_PP_EVENT_DISABLE_USER2D_PERFORMANCE,
|
||||
AMD_PP_EVENT_ENABLE_USER3D_PERFORMANCE,
|
||||
AMD_PP_EVENT_DISABLE_USER3D_PERFORMANCE,
|
||||
AMD_PP_EVENT_ENABLE_OVER_DRIVE_TEST,
|
||||
AMD_PP_EVENT_DISABLE_OVER_DRIVE_TEST,
|
||||
AMD_PP_EVENT_ENABLE_REDUCED_REFRESH_RATE,
|
||||
AMD_PP_EVENT_DISABLE_REDUCED_REFRESH_RATE,
|
||||
AMD_PP_EVENT_ENABLE_GFX_CLOCK_GATING,
|
||||
AMD_PP_EVENT_DISABLE_GFX_CLOCK_GATING,
|
||||
AMD_PP_EVENT_ENABLE_CGPG,
|
||||
AMD_PP_EVENT_DISABLE_CGPG,
|
||||
AMD_PP_EVENT_ENTER_TEXT_MODE,
|
||||
AMD_PP_EVENT_EXIT_TEXT_MODE,
|
||||
AMD_PP_EVENT_VIDEO_START,
|
||||
AMD_PP_EVENT_VIDEO_STOP,
|
||||
AMD_PP_EVENT_ENABLE_USER_STATE,
|
||||
AMD_PP_EVENT_DISABLE_USER_STATE,
|
||||
AMD_PP_EVENT_READJUST_POWER_STATE,
|
||||
AMD_PP_EVENT_START_INACTIVITY,
|
||||
AMD_PP_EVENT_STOP_INACTIVITY,
|
||||
AMD_PP_EVENT_LINKED_ADAPTERS_READY,
|
||||
AMD_PP_EVENT_ADAPTER_SAFE_TO_DISABLE,
|
||||
AMD_PP_EVENT_COMPLETE_INIT,
|
||||
AMD_PP_EVENT_CRITICAL_THERMAL_FAULT,
|
||||
AMD_PP_EVENT_BACKLIGHT_CHANGED,
|
||||
AMD_PP_EVENT_ENABLE_VARI_BRIGHT,
|
||||
AMD_PP_EVENT_DISABLE_VARI_BRIGHT,
|
||||
AMD_PP_EVENT_ENABLE_VARI_BRIGHT_ON_POWER_XPRESS,
|
||||
AMD_PP_EVENT_DISABLE_VARI_BRIGHT_ON_POWER_XPRESS,
|
||||
AMD_PP_EVENT_SET_VARI_BRIGHT_LEVEL,
|
||||
AMD_PP_EVENT_VARI_BRIGHT_MONITOR_MEASUREMENT,
|
||||
AMD_PP_EVENT_SCREEN_ON,
|
||||
AMD_PP_EVENT_SCREEN_OFF,
|
||||
AMD_PP_EVENT_PRE_DISPLAY_CONFIG_CHANGE,
|
||||
AMD_PP_EVENT_ENTER_ULP_STATE,
|
||||
AMD_PP_EVENT_EXIT_ULP_STATE,
|
||||
AMD_PP_EVENT_REGISTER_IP_STATE,
|
||||
AMD_PP_EVENT_UNREGISTER_IP_STATE,
|
||||
AMD_PP_EVENT_ENTER_MGPU_MODE,
|
||||
AMD_PP_EVENT_EXIT_MGPU_MODE,
|
||||
AMD_PP_EVENT_ENTER_MULTI_GPU_MODE,
|
||||
AMD_PP_EVENT_PRE_SUSPEND,
|
||||
AMD_PP_EVENT_PRE_RESUME,
|
||||
AMD_PP_EVENT_ENTER_BACOS,
|
||||
AMD_PP_EVENT_EXIT_BACOS,
|
||||
AMD_PP_EVENT_RESUME_BACO,
|
||||
AMD_PP_EVENT_RESET_BACO,
|
||||
AMD_PP_EVENT_PRE_DISPLAY_PHY_ACCESS,
|
||||
AMD_PP_EVENT_POST_DISPLAY_PHY_CCESS,
|
||||
AMD_PP_EVENT_START_COMPUTE_APPLICATION,
|
||||
AMD_PP_EVENT_STOP_COMPUTE_APPLICATION,
|
||||
AMD_PP_EVENT_REDUCE_POWER_LIMIT,
|
||||
AMD_PP_EVENT_ENTER_FRAME_LOCK,
|
||||
AMD_PP_EVENT_EXIT_FRAME_LOOCK,
|
||||
AMD_PP_EVENT_LONG_IDLE_REQUEST_BACO,
|
||||
AMD_PP_EVENT_LONG_IDLE_ENTER_BACO,
|
||||
AMD_PP_EVENT_LONG_IDLE_EXIT_BACO,
|
||||
AMD_PP_EVENT_HIBERNATE,
|
||||
AMD_PP_EVENT_CONNECTED_STANDBY,
|
||||
AMD_PP_EVENT_ENTER_SELF_REFRESH,
|
||||
AMD_PP_EVENT_EXIT_SELF_REFRESH,
|
||||
AMD_PP_EVENT_START_AVFS_BTC,
|
||||
AMD_PP_EVENT_MAX
|
||||
};
|
||||
|
||||
enum amd_dpm_forced_level {
|
||||
AMD_DPM_FORCED_LEVEL_AUTO = 0,
|
||||
AMD_DPM_FORCED_LEVEL_LOW = 1,
|
||||
AMD_DPM_FORCED_LEVEL_HIGH = 2,
|
||||
};
|
||||
|
||||
struct amd_pp_init {
|
||||
struct cgs_device *device;
|
||||
uint32_t chip_family;
|
||||
uint32_t chip_id;
|
||||
uint32_t rev_id;
|
||||
};
|
||||
|
||||
struct amd_powerplay_funcs {
|
||||
int (*get_temperature)(void *handle);
|
||||
int (*load_firmware)(void *handle);
|
||||
int (*wait_for_fw_loading_complete)(void *handle);
|
||||
int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
|
||||
enum amd_dpm_forced_level (*get_performance_level)(void *handle);
|
||||
enum amd_pm_state_type (*get_current_power_state)(void *handle);
|
||||
int (*get_sclk)(void *handle, bool low);
|
||||
int (*get_mclk)(void *handle, bool low);
|
||||
int (*powergate_vce)(void *handle, bool gate);
|
||||
int (*powergate_uvd)(void *handle, bool gate);
|
||||
int (*dispatch_tasks)(void *handle, enum amd_pp_event event_id,
|
||||
void *input, void *output);
|
||||
void (*print_current_performance_level)(void *handle,
|
||||
struct seq_file *m);
|
||||
};
|
||||
|
||||
struct amd_powerplay {
|
||||
void *pp_handle;
|
||||
const struct amd_ip_funcs *ip_funcs;
|
||||
const struct amd_powerplay_funcs *pp_funcs;
|
||||
};
|
||||
|
||||
int amd_powerplay_init(struct amd_pp_init *pp_init,
|
||||
struct amd_powerplay *amd_pp);
|
||||
int amd_powerplay_fini(void *handle);
|
||||
|
||||
#endif /* _AMD_POWERPLAY_H_ */
|
Loading…
Reference in New Issue