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i.MX device tree updates for 4.10: 

- New boards support: i.MX6SX UDOO Neo, Boundary Devices Nitrogen6_SOM2,
    Engicam i.CoreM6, Grinn i.MX6UL liteSOM/liteBoard, Toradex Colibri
    iMX6 module, i.MX6ULL and EVK board.
  - Remove skeleton.dtsi inclusion from all i.MX SoC dts files, as it's
    been deprecated, since commit 9c0da3cc61 ("ARM: dts: explicitly
    mark skeleton.dtsi as deprecated").
  - Misc device addition and enabling: OCOTP for Vybrid, MMDC for i.MX6QP,
    TMU for LS1021A, FEC for imx6qdl-icore, DMA for Vybrid DSPI.
  - A few cleanups: use hyphens for node names, fix white spaces, move
    imx-weim parameters into SoC dtsi, replace gpio-key,wakeup with
    wakeup-source, remove pwm-leds from imx6q-apalis-ixora, remove I2C3
    from vf610-zii-dev-rev-b.
  - Other small random changes: calibrate USB PHY for b650v3 board,
    update TX D_CAL for USBPHY, use enable-gpios for backlight on
    imx6qdl-apalis, etc.
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Merge tag 'imx-dt-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt

i.MX device tree updates for 4.10:
 - New boards support: i.MX6SX UDOO Neo, Boundary Devices Nitrogen6_SOM2,
   Engicam i.CoreM6, Grinn i.MX6UL liteSOM/liteBoard, Toradex Colibri
   iMX6 module, i.MX6ULL and EVK board.
 - Remove skeleton.dtsi inclusion from all i.MX SoC dts files, as it's
   been deprecated, since commit 9c0da3cc61 ("ARM: dts: explicitly
   mark skeleton.dtsi as deprecated").
 - Misc device addition and enabling: OCOTP for Vybrid, MMDC for i.MX6QP,
   TMU for LS1021A, FEC for imx6qdl-icore, DMA for Vybrid DSPI.
 - A few cleanups: use hyphens for node names, fix white spaces, move
   imx-weim parameters into SoC dtsi, replace gpio-key,wakeup with
   wakeup-source, remove pwm-leds from imx6q-apalis-ixora, remove I2C3
   from vf610-zii-dev-rev-b.
 - Other small random changes: calibrate USB PHY for b650v3 board,
   update TX D_CAL for USBPHY, use enable-gpios for backlight on
   imx6qdl-apalis, etc.

* tag 'imx-dt-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (38 commits)
  ARM: dts: imx6ull: add imx6ull support
  ARM: dts: imx6q: replace gpio-key,wakeup with wakeup-source for Utilite Pro
  ARM: dts: vfxxx: Enable DMA for DSPI2 and DSPI3
  ARM: dts: imx: Remove skeleton.dtsi
  ARM: dts: imx6q-utilite-pro: i2c1 is muxed
  ARM: dts: add new compatible string for i.MX6QP mmdc
  ARM: dts: imx6sx-udoo: Add board specific compatible strings
  ARM: dts: mx5: Add new M53EVK manufacturer compat
  ARM: dts: mxs: Add new M28EVK manufacturer compat
  ARM: dts: imx6ul-14x14-evk: update TX D_CAL for USBPHY
  ARM: dts: imx6sx-sdb: update TX D_CAL for USBPHY
  ARM: dts: imx6: Add imx-weim parameters to dtsi's
  ARM: dts: imx: Fix "ERROR: code indent should use tabs where possible"
  ARM: dts: imx6qdl-nitrogen6_max: use hyphens for nodes name
  ARM: dts: imx6qdl-nit6xlite: use hyphens for nodes name
  ARM: dts: imx6qdl-nitrogen6x: use hyphens for nodes name
  ARM: dts: imx6qdl-sabrelite: use hyphens for nodes name
  ARM: dts: imx: add Boundary Devices Nitrogen6_SOM2 support
  ARM: dts: imx6qdl-icore: Add FEC support
  ARM: dts: imx6q: Add Engicam i.CoreM6 DualLite/Solo initial support
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2016-11-18 09:59:57 -08:00
parent f05646c94b c201369d4a
commit 1fc7210c1d
72 changed files with 3638 additions and 268 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
arch/arm/boot/dts/Makefile
View File

@ -331,6 +331,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-aristainetos_7.dtb \
imx6dl-aristainetos2_4.dtb \
imx6dl-aristainetos2_7.dtb \
imx6dl-colibri-eval-v3.dtb \
imx6dl-cubox-i.dtb \
imx6dl-dfi-fs700-m60.dtb \
imx6dl-gw51xx.dtb \
@ -341,6 +342,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-gw552x.dtb \
imx6dl-gw553x.dtb \
imx6dl-hummingboard.dtb \
imx6dl-icore.dtb \
imx6dl-nit6xlite.dtb \
imx6dl-nitrogen6x.dtb \
imx6dl-phytec-pbab01.dtb \
@ -382,10 +384,12 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-gw553x.dtb \
imx6q-h100.dtb \
imx6q-hummingboard.dtb \
imx6q-icore.dtb \
imx6q-icore-rqs.dtb \
imx6q-marsboard.dtb \
imx6q-nitrogen6x.dtb \
imx6q-nitrogen6_max.dtb \
imx6q-nitrogen6_som2.dtb \
imx6q-novena.dtb \
imx6q-phytec-pbab01.dtb \
imx6q-rex-pro.dtb \
@ -417,14 +421,19 @@ dtb-$(CONFIG_SOC_IMX6SX) += \
imx6sx-sabreauto.dtb \
imx6sx-sdb-reva.dtb \
imx6sx-sdb-sai.dtb \
imx6sx-sdb.dtb
imx6sx-sdb.dtb \
imx6sx-udoo-neo-basic.dtb \
imx6sx-udoo-neo-extended.dtb \
imx6sx-udoo-neo-full.dtb
dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-14x14-evk.dtb \
imx6ul-geam-kit.dtb \
imx6ul-liteboard.dtb \
imx6ul-pico-hobbit.dtb \
imx6ul-tx6ul-0010.dtb \
imx6ul-tx6ul-0011.dtb \
imx6ul-tx6ul-mainboard.dtb
imx6ul-tx6ul-mainboard.dtb \
imx6ull-14x14-evk.dtb
dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-cl-som-imx7.dtb \
imx7d-colibri-eval-v3.dtb \

4
arch/arm/boot/dts/imx1.dtsi
View File

@ -9,7 +9,6 @@
* http://www.gnu.org/copyleft/gpl.html
*/
#include "skeleton.dtsi"
#include "imx1-pinfunc.h"
#include <dt-bindings/clock/imx1-clock.h>
@ -17,6 +16,9 @@
#include <dt-bindings/interrupt-controller/irq.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
aliases {
gpio0 = &gpio1;
gpio1 = &gpio2;

6
arch/arm/boot/dts/imx23.dtsi
View File

@ -9,10 +9,12 @@
* http://www.gnu.org/copyleft/gpl.html
*/
#include "skeleton.dtsi"
#include "imx23-pinfunc.h"
/ {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&icoll>;
aliases {
@ -464,7 +466,7 @@ tvenc@80038000 {
reg = <0x80038000 0x2000>;
status = "disabled";
};
};
};
apbx@80040000 {
compatible = "simple-bus";

4
arch/arm/boot/dts/imx25.dtsi
View File

@ -9,10 +9,12 @@
* http://www.gnu.org/copyleft/gpl.html
*/
#include "skeleton.dtsi"
#include "imx25-pinfunc.h"
/ {
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &fec;
gpio0 = &gpio1;

4
arch/arm/boot/dts/imx27.dtsi
View File

@ -9,7 +9,6 @@
* http://www.gnu.org/copyleft/gpl.html
*/
#include "skeleton.dtsi"
#include "imx27-pinfunc.h"
#include <dt-bindings/clock/imx27-clock.h>
@ -18,6 +17,9 @@
#include <dt-bindings/interrupt-controller/irq.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &fec;
gpio0 = &gpio1;

4
arch/arm/boot/dts/imx28-m28.dtsi
View File

@ -12,8 +12,8 @@
#include "imx28.dtsi"
/ {
model = "DENX M28";
compatible = "denx,m28", "fsl,imx28";
model = "Aries/DENX M28";
compatible = "aries,m28", "denx,m28", "fsl,imx28";
memory {
reg = <0x40000000 0x08000000>;

4
arch/arm/boot/dts/imx28-m28evk.dts
View File

@ -13,8 +13,8 @@
#include "imx28-m28.dtsi"
/ {
model = "DENX M28EVK";
compatible = "denx,m28evk", "fsl,imx28";
model = "Aries/DENX M28EVK";
compatible = "aries,m28evk", "denx,m28evk", "fsl,imx28";
apb@80000000 {
apbh@80000000 {

4
arch/arm/boot/dts/imx28.dtsi
View File

@ -10,10 +10,12 @@
*/
#include <dt-bindings/gpio/gpio.h>
#include "skeleton.dtsi"
#include "imx28-pinfunc.h"
/ {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&icoll>;
aliases {

5
arch/arm/boot/dts/imx31.dtsi
View File

@ -9,9 +9,10 @@
* http://www.gnu.org/copyleft/gpl.html
*/
#include "skeleton.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
aliases {
serial0 = &uart1;
serial1 = &uart2;

4
arch/arm/boot/dts/imx35.dtsi
View File

@ -8,10 +8,12 @@
* Free Software Foundation.
*/
#include "skeleton.dtsi"
#include "imx35-pinfunc.h"
/ {
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &fec;
gpio0 = &gpio1;

48
arch/arm/boot/dts/imx50.dtsi
View File

@ -11,11 +11,13 @@
* http://www.gnu.org/copyleft/gpl.html
*/
#include "skeleton.dtsi"
#include "imx50-pinfunc.h"
#include <dt-bindings/clock/imx5-clock.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &fec;
gpio0 = &gpio1;
@ -103,8 +105,8 @@ esdhc1: esdhc@50004000 {
reg = <0x50004000 0x4000>;
interrupts = <1>;
clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC1_PER_GATE>;
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC1_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@ -115,8 +117,8 @@ esdhc2: esdhc@50008000 {
reg = <0x50008000 0x4000>;
interrupts = <2>;
clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC2_PER_GATE>;
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC2_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@ -127,7 +129,7 @@ uart3: serial@5000c000 {
reg = <0x5000c000 0x4000>;
interrupts = <33>;
clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
<&clks IMX5_CLK_UART3_PER_GATE>;
<&clks IMX5_CLK_UART3_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@ -139,7 +141,7 @@ ecspi1: ecspi@50010000 {
reg = <0x50010000 0x4000>;
interrupts = <36>;
clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
<&clks IMX5_CLK_ECSPI1_PER_GATE>;
<&clks IMX5_CLK_ECSPI1_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@ -164,8 +166,8 @@ esdhc3: esdhc@50020000 {
reg = <0x50020000 0x4000>;
interrupts = <3>;
clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC3_PER_GATE>;
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC3_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@ -176,8 +178,8 @@ esdhc4: esdhc@50024000 {
reg = <0x50024000 0x4000>;
interrupts = <4>;
clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC4_PER_GATE>;
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC4_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@ -279,7 +281,7 @@ gpt: timer@53fa0000 {
reg = <0x53fa0000 0x4000>;
interrupts = <39>;
clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
<&clks IMX5_CLK_GPT_HF_GATE>;
<&clks IMX5_CLK_GPT_HF_GATE>;
clock-names = "ipg", "per";
};
@ -298,7 +300,7 @@ pwm1: pwm@53fb4000 {
compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
reg = <0x53fb4000 0x4000>;
clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
<&clks IMX5_CLK_PWM1_HF_GATE>;
<&clks IMX5_CLK_PWM1_HF_GATE>;
clock-names = "ipg", "per";
interrupts = <61>;
};
@ -308,7 +310,7 @@ pwm2: pwm@53fb8000 {
compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
reg = <0x53fb8000 0x4000>;
clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
<&clks IMX5_CLK_PWM2_HF_GATE>;
<&clks IMX5_CLK_PWM2_HF_GATE>;
clock-names = "ipg", "per";
interrupts = <94>;
};
@ -318,7 +320,7 @@ uart1: serial@53fbc000 {
reg = <0x53fbc000 0x4000>;
interrupts = <31>;
clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
<&clks IMX5_CLK_UART1_PER_GATE>;
<&clks IMX5_CLK_UART1_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@ -328,7 +330,7 @@ uart2: serial@53fc0000 {
reg = <0x53fc0000 0x4000>;
interrupts = <32>;
clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
<&clks IMX5_CLK_UART2_PER_GATE>;
<&clks IMX5_CLK_UART2_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@ -383,7 +385,7 @@ uart4: serial@53ff0000 {
reg = <0x53ff0000 0x4000>;
interrupts = <13>;
clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
<&clks IMX5_CLK_UART4_PER_GATE>;
<&clks IMX5_CLK_UART4_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@ -401,7 +403,7 @@ uart5: serial@63f90000 {
reg = <0x63f90000 0x4000>;
interrupts = <86>;
clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
<&clks IMX5_CLK_UART5_PER_GATE>;
<&clks IMX5_CLK_UART5_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@ -420,7 +422,7 @@ ecspi2: ecspi@63fac000 {
reg = <0x63fac000 0x4000>;
interrupts = <37>;
clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
<&clks IMX5_CLK_ECSPI2_PER_GATE>;
<&clks IMX5_CLK_ECSPI2_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@ -430,7 +432,7 @@ sdma: sdma@63fb0000 {
reg = <0x63fb0000 0x4000>;
interrupts = <6>;
clocks = <&clks IMX5_CLK_SDMA_GATE>,
<&clks IMX5_CLK_SDMA_GATE>;
<&clks IMX5_CLK_SDMA_GATE>;
clock-names = "ipg", "ahb";
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
};
@ -442,7 +444,7 @@ cspi: cspi@63fc0000 {
reg = <0x63fc0000 0x4000>;
interrupts = <38>;
clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
<&clks IMX5_CLK_CSPI_IPG_GATE>;
<&clks IMX5_CLK_CSPI_IPG_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@ -492,8 +494,8 @@ fec: ethernet@63fec000 {
reg = <0x63fec000 0x4000>;
interrupts = <87>;
clocks = <&clks IMX5_CLK_FEC_GATE>,
<&clks IMX5_CLK_FEC_GATE>,
<&clks IMX5_CLK_FEC_GATE>;
<&clks IMX5_CLK_FEC_GATE>,
<&clks IMX5_CLK_FEC_GATE>;
clock-names = "ipg", "ahb", "ptp";
status = "disabled";
};

48
arch/arm/boot/dts/imx51.dtsi
View File

@ -10,7 +10,6 @@
* http://www.gnu.org/copyleft/gpl.html
*/
#include "skeleton.dtsi"
#include "imx51-pinfunc.h"
#include <dt-bindings/clock/imx5-clock.h>
#include <dt-bindings/gpio/gpio.h>
@ -18,6 +17,9 @@
#include <dt-bindings/interrupt-controller/irq.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &fec;
gpio0 = &gpio1;
@ -130,8 +132,8 @@ ipu: ipu@40000000 {
reg = <0x40000000 0x20000000>;
interrupts = <11 10>;
clocks = <&clks IMX5_CLK_IPU_GATE>,
<&clks IMX5_CLK_IPU_DI0_GATE>,
<&clks IMX5_CLK_IPU_DI1_GATE>;
<&clks IMX5_CLK_IPU_DI0_GATE>,
<&clks IMX5_CLK_IPU_DI1_GATE>;
clock-names = "bus", "di0", "di1";
resets = <&src 2>;
@ -169,8 +171,8 @@ esdhc1: esdhc@70004000 {
reg = <0x70004000 0x4000>;
interrupts = <1>;
clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC1_PER_GATE>;
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC1_PER_GATE>;
clock-names = "ipg", "ahb", "per";
status = "disabled";
};
@ -180,8 +182,8 @@ esdhc2: esdhc@70008000 {
reg = <0x70008000 0x4000>;
interrupts = <2>;
clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC2_PER_GATE>;
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC2_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@ -192,7 +194,7 @@ uart3: serial@7000c000 {
reg = <0x7000c000 0x4000>;
interrupts = <33>;
clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
<&clks IMX5_CLK_UART3_PER_GATE>;
<&clks IMX5_CLK_UART3_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@ -204,7 +206,7 @@ ecspi1: ecspi@70010000 {
reg = <0x70010000 0x4000>;
interrupts = <36>;
clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
<&clks IMX5_CLK_ECSPI1_PER_GATE>;
<&clks IMX5_CLK_ECSPI1_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@ -229,8 +231,8 @@ esdhc3: esdhc@70020000 {
reg = <0x70020000 0x4000>;
interrupts = <3>;
clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC3_PER_GATE>;
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC3_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@ -241,8 +243,8 @@ esdhc4: esdhc@70024000 {
reg = <0x70024000 0x4000>;
interrupts = <4>;
clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC4_PER_GATE>;
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC4_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@ -364,7 +366,7 @@ gpt: timer@73fa0000 {
reg = <0x73fa0000 0x4000>;
interrupts = <39>;
clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
<&clks IMX5_CLK_GPT_HF_GATE>;
<&clks IMX5_CLK_GPT_HF_GATE>;
clock-names = "ipg", "per";
};
@ -378,7 +380,7 @@ pwm1: pwm@73fb4000 {
compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
reg = <0x73fb4000 0x4000>;
clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
<&clks IMX5_CLK_PWM1_HF_GATE>;
<&clks IMX5_CLK_PWM1_HF_GATE>;
clock-names = "ipg", "per";
interrupts = <61>;
};
@ -388,7 +390,7 @@ pwm2: pwm@73fb8000 {
compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
reg = <0x73fb8000 0x4000>;
clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
<&clks IMX5_CLK_PWM2_HF_GATE>;
<&clks IMX5_CLK_PWM2_HF_GATE>;
clock-names = "ipg", "per";
interrupts = <94>;
};
@ -398,7 +400,7 @@ uart1: serial@73fbc000 {
reg = <0x73fbc000 0x4000>;
interrupts = <31>;
clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
<&clks IMX5_CLK_UART1_PER_GATE>;
<&clks IMX5_CLK_UART1_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@ -408,7 +410,7 @@ uart2: serial@73fc0000 {
reg = <0x73fc0000 0x4000>;
interrupts = <32>;
clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
<&clks IMX5_CLK_UART2_PER_GATE>;
<&clks IMX5_CLK_UART2_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@ -456,7 +458,7 @@ ecspi2: ecspi@83fac000 {
reg = <0x83fac000 0x4000>;
interrupts = <37>;
clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
<&clks IMX5_CLK_ECSPI2_PER_GATE>;
<&clks IMX5_CLK_ECSPI2_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@ -466,7 +468,7 @@ sdma: sdma@83fb0000 {
reg = <0x83fb0000 0x4000>;
interrupts = <6>;
clocks = <&clks IMX5_CLK_SDMA_GATE>,
<&clks IMX5_CLK_SDMA_GATE>;
<&clks IMX5_CLK_SDMA_GATE>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
@ -479,7 +481,7 @@ cspi: cspi@83fc0000 {
reg = <0x83fc0000 0x4000>;
interrupts = <38>;
clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
<&clks IMX5_CLK_CSPI_IPG_GATE>;
<&clks IMX5_CLK_CSPI_IPG_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@ -582,8 +584,8 @@ fec: ethernet@83fec000 {
reg = <0x83fec000 0x4000>;
interrupts = <87>;
clocks = <&clks IMX5_CLK_FEC_GATE>,
<&clks IMX5_CLK_FEC_GATE>,
<&clks IMX5_CLK_FEC_GATE>;
<&clks IMX5_CLK_FEC_GATE>,
<&clks IMX5_CLK_FEC_GATE>;
clock-names = "ipg", "ahb", "ptp";
status = "disabled";
};

4
arch/arm/boot/dts/imx53-m53.dtsi
View File

@ -12,8 +12,8 @@
#include "imx53.dtsi"
/ {
model = "DENX M53";
compatible = "denx,imx53-m53", "fsl,imx53";
model = "Aries/DENX M53";
compatible = "aries,imx53-m53", "denx,imx53-m53", "fsl,imx53";
memory {
reg = <0x70000000 0x20000000>,

4
arch/arm/boot/dts/imx53-m53evk.dts
View File

@ -13,8 +13,8 @@
#include "imx53-m53.dtsi"
/ {
model = "DENX M53EVK";
compatible = "denx,imx53-m53evk", "fsl,imx53";
model = "Aries/DENX M53EVK";
compatible = "aries,imx53-m53evk", "denx,imx53-m53evk", "fsl,imx53";
display1: display@di1 {
compatible = "fsl,imx-parallel-display";

72
arch/arm/boot/dts/imx53.dtsi
View File

@ -10,7 +10,6 @@
* http://www.gnu.org/copyleft/gpl.html
*/
#include "skeleton.dtsi"
#include "imx53-pinfunc.h"
#include <dt-bindings/clock/imx5-clock.h>
#include <dt-bindings/gpio/gpio.h>
@ -18,6 +17,9 @@
#include <dt-bindings/interrupt-controller/irq.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &fec;
gpio0 = &gpio1;
@ -131,8 +133,8 @@ ipu: ipu@18000000 {
reg = <0x18000000 0x08000000>;
interrupts = <11 10>;
clocks = <&clks IMX5_CLK_IPU_GATE>,
<&clks IMX5_CLK_IPU_DI0_GATE>,
<&clks IMX5_CLK_IPU_DI1_GATE>;
<&clks IMX5_CLK_IPU_DI0_GATE>,
<&clks IMX5_CLK_IPU_DI1_GATE>;
clock-names = "bus", "di0", "di1";
resets = <&src 2>;
@ -199,8 +201,8 @@ esdhc1: esdhc@50004000 {
reg = <0x50004000 0x4000>;
interrupts = <1>;
clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC1_PER_GATE>;
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC1_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@ -211,8 +213,8 @@ esdhc2: esdhc@50008000 {
reg = <0x50008000 0x4000>;
interrupts = <2>;
clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC2_PER_GATE>;
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC2_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@ -223,7 +225,7 @@ uart3: serial@5000c000 {
reg = <0x5000c000 0x4000>;
interrupts = <33>;
clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
<&clks IMX5_CLK_UART3_PER_GATE>;
<&clks IMX5_CLK_UART3_PER_GATE>;
clock-names = "ipg", "per";
dmas = <&sdma 42 4 0>, <&sdma 43 4 0>;
dma-names = "rx", "tx";
@ -237,7 +239,7 @@ ecspi1: ecspi@50010000 {
reg = <0x50010000 0x4000>;
interrupts = <36>;
clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
<&clks IMX5_CLK_ECSPI1_PER_GATE>;
<&clks IMX5_CLK_ECSPI1_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@ -264,8 +266,8 @@ esdhc3: esdhc@50020000 {
reg = <0x50020000 0x4000>;
interrupts = <3>;
clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC3_PER_GATE>;
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC3_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@ -276,8 +278,8 @@ esdhc4: esdhc@50024000 {
reg = <0x50024000 0x4000>;
interrupts = <4>;
clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC4_PER_GATE>;
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC4_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
@ -419,7 +421,7 @@ gpt: timer@53fa0000 {
reg = <0x53fa0000 0x4000>;
interrupts = <39>;
clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
<&clks IMX5_CLK_GPT_HF_GATE>;
<&clks IMX5_CLK_GPT_HF_GATE>;
clock-names = "ipg", "per";
};
@ -440,11 +442,11 @@ ldb: ldb@53fa8008 {
reg = <0x53fa8008 0x4>;
gpr = <&gpr>;
clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
<&clks IMX5_CLK_LDB_DI1_SEL>,
<&clks IMX5_CLK_IPU_DI0_SEL>,
<&clks IMX5_CLK_IPU_DI1_SEL>,
<&clks IMX5_CLK_LDB_DI0_GATE>,
<&clks IMX5_CLK_LDB_DI1_GATE>;
<&clks IMX5_CLK_LDB_DI1_SEL>,
<&clks IMX5_CLK_IPU_DI0_SEL>,
<&clks IMX5_CLK_IPU_DI1_SEL>,
<&clks IMX5_CLK_LDB_DI0_GATE>,
<&clks IMX5_CLK_LDB_DI1_GATE>;
clock-names = "di0_pll", "di1_pll",
"di0_sel", "di1_sel",
"di0", "di1";
@ -486,7 +488,7 @@ pwm1: pwm@53fb4000 {
compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
reg = <0x53fb4000 0x4000>;
clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
<&clks IMX5_CLK_PWM1_HF_GATE>;
<&clks IMX5_CLK_PWM1_HF_GATE>;
clock-names = "ipg", "per";
interrupts = <61>;
};
@ -496,7 +498,7 @@ pwm2: pwm@53fb8000 {
compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
reg = <0x53fb8000 0x4000>;
clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
<&clks IMX5_CLK_PWM2_HF_GATE>;
<&clks IMX5_CLK_PWM2_HF_GATE>;
clock-names = "ipg", "per";
interrupts = <94>;
};
@ -506,7 +508,7 @@ uart1: serial@53fbc000 {
reg = <0x53fbc000 0x4000>;
interrupts = <31>;
clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
<&clks IMX5_CLK_UART1_PER_GATE>;
<&clks IMX5_CLK_UART1_PER_GATE>;
clock-names = "ipg", "per";
dmas = <&sdma 18 4 0>, <&sdma 19 4 0>;
dma-names = "rx", "tx";
@ -518,7 +520,7 @@ uart2: serial@53fc0000 {
reg = <0x53fc0000 0x4000>;
interrupts = <32>;
clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
<&clks IMX5_CLK_UART2_PER_GATE>;
<&clks IMX5_CLK_UART2_PER_GATE>;
clock-names = "ipg", "per";
dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
dma-names = "rx", "tx";
@ -530,7 +532,7 @@ can1: can@53fc8000 {
reg = <0x53fc8000 0x4000>;
interrupts = <82>;
clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
<&clks IMX5_CLK_CAN1_SERIAL_GATE>;
<&clks IMX5_CLK_CAN1_SERIAL_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@ -540,7 +542,7 @@ can2: can@53fcc000 {
reg = <0x53fcc000 0x4000>;
interrupts = <83>;
clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
<&clks IMX5_CLK_CAN2_SERIAL_GATE>;
<&clks IMX5_CLK_CAN2_SERIAL_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@ -603,7 +605,7 @@ uart4: serial@53ff0000 {
reg = <0x53ff0000 0x4000>;
interrupts = <13>;
clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
<&clks IMX5_CLK_UART4_PER_GATE>;
<&clks IMX5_CLK_UART4_PER_GATE>;
clock-names = "ipg", "per";
dmas = <&sdma 2 4 0>, <&sdma 3 4 0>;
dma-names = "rx", "tx";
@ -635,7 +637,7 @@ uart5: serial@63f90000 {
reg = <0x63f90000 0x4000>;
interrupts = <86>;
clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
<&clks IMX5_CLK_UART5_PER_GATE>;
<&clks IMX5_CLK_UART5_PER_GATE>;
clock-names = "ipg", "per";
dmas = <&sdma 16 4 0>, <&sdma 17 4 0>;
dma-names = "rx", "tx";
@ -656,7 +658,7 @@ ecspi2: ecspi@63fac000 {
reg = <0x63fac000 0x4000>;
interrupts = <37>;
clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
<&clks IMX5_CLK_ECSPI2_PER_GATE>;
<&clks IMX5_CLK_ECSPI2_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@ -666,7 +668,7 @@ sdma: sdma@63fb0000 {
reg = <0x63fb0000 0x4000>;
interrupts = <6>;
clocks = <&clks IMX5_CLK_SDMA_GATE>,
<&clks IMX5_CLK_SDMA_GATE>;
<&clks IMX5_CLK_SDMA_GATE>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
@ -679,7 +681,7 @@ cspi: cspi@63fc0000 {
reg = <0x63fc0000 0x4000>;
interrupts = <38>;
clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
<&clks IMX5_CLK_CSPI_IPG_GATE>;
<&clks IMX5_CLK_CSPI_IPG_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
@ -755,8 +757,8 @@ fec: ethernet@63fec000 {
reg = <0x63fec000 0x4000>;
interrupts = <87>;
clocks = <&clks IMX5_CLK_FEC_GATE>,
<&clks IMX5_CLK_FEC_GATE>,
<&clks IMX5_CLK_FEC_GATE>;
<&clks IMX5_CLK_FEC_GATE>,
<&clks IMX5_CLK_FEC_GATE>;
clock-names = "ipg", "ahb", "ptp";
status = "disabled";
};
@ -766,7 +768,7 @@ tve: tve@63ff0000 {
reg = <0x63ff0000 0x1000>;
interrupts = <92>;
clocks = <&clks IMX5_CLK_TVE_GATE>,
<&clks IMX5_CLK_IPU_DI1_SEL>;
<&clks IMX5_CLK_IPU_DI1_SEL>;
clock-names = "tve", "di_sel";
status = "disabled";
@ -782,7 +784,7 @@ vpu: vpu@63ff4000 {
reg = <0x63ff4000 0x1000>;
interrupts = <9>;
clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
<&clks IMX5_CLK_VPU_GATE>;
<&clks IMX5_CLK_VPU_GATE>;
clock-names = "per", "ahb";
resets = <&src 1>;
iram = <&ocram>;
@ -793,7 +795,7 @@ sahara: crypto@63ff8000 {
reg = <0x63ff8000 0x4000>;
interrupts = <19 20>;
clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
<&clks IMX5_CLK_SAHARA_IPG_GATE>;
<&clks IMX5_CLK_SAHARA_IPG_GATE>;
clock-names = "ipg", "ahb";
};
};

253
arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts Normal file
View File

@ -0,0 +1,253 @@
/*
* Copyright 2014-2016 Toradex AG
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "imx6dl.dtsi"
#include "imx6qdl-colibri.dtsi"
/ {
model = "Toradex Colibri iMX6DL/S on Colibri Evaluation Board V3";
compatible = "toradex,colibri_imx6dl-eval-v3", "toradex,colibri_imx6dl",
"fsl,imx6dl";
aliases {
i2c0 = &i2c2;
i2c1 = &i2c3;
};
aliases {
rtc0 = &rtc_i2c;
rtc1 = &snvs_rtc;
};
clocks {
/* Fixed crystal dedicated to mcp251x */
clk16m: clk@1 {
compatible = "fixed-clock";
reg = <1>;
#clock-cells = <0>;
clock-frequency = <16000000>;
clock-output-names = "clk16m";
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
wakeup {
label = "Wake-Up";
gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* SODIMM 45 */
linux,code = <KEY_WAKEUP>;
debounce-interval = <10>;
wakeup-source;
};
};
lcd_display: display@di0 {
compatible = "fsl,imx-parallel-display";
#address-cells = <1>;
#size-cells = <0>;
interface-pix-fmt = "bgr666";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu1_lcdif>;
status = "okay";
port@0 {
reg = <0>;
lcd_display_in: endpoint {
remote-endpoint = <&ipu1_di0_disp0>;
};
};
port@1 {
reg = <1>;
lcd_display_out: endpoint {
remote-endpoint = <&lcd_panel_in>;
};
};
};
panel: panel {
/*
* edt,et057090dhu: EDT 5.7" LCD TFT
* edt,et070080dh6: EDT 7.0" LCD TFT
*/
compatible = "edt,et057090dhu";
backlight = <&backlight>;
port {
lcd_panel_in: endpoint {
remote-endpoint = <&lcd_display_out>;
};
};
};
};
&backlight {
brightness-levels = <0 127 191 223 239 247 251 255>;
default-brightness-level = <1>;
status = "okay";
};
/* Colibri SSP */
&ecspi4 {
status = "okay";
mcp251x0: mcp251x@1 {
compatible = "microchip,mcp2515";
reg = <0>;
clocks = <&clk16m>;
interrupt-parent = <&gpio3>;
interrupts = <27 0x2>;
spi-max-frequency = <10000000>;
status = "okay";
};
};
&hdmi {
status = "okay";
};
/*
* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
*/
&i2c3 {
status = "okay";
/* M41T0M6 real time clock on carrier board */
rtc_i2c: rtc@68 {
compatible = "st,m41t00";
reg = <0x68>;
};
};
&ipu1_di0_disp0 {
remote-endpoint = <&lcd_display_in>;
};
&pwm1 {
status = "okay";
};
&pwm2 {
status = "okay";
};
&pwm3 {
status = "okay";
};
&pwm4 {
status = "okay";
};
&reg_usb_host_vbus {
status = "okay";
};
&uart1 {
status = "okay";
};
&uart2 {
status = "okay";
};
&uart3 {
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_usb_host_vbus>;
status = "okay";
};
&usbotg {
status = "okay";
};
/* Colibri MMC */
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc_cd>;
cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */
status = "okay";
};
&weim {
status = "okay";
/* weim memory map: 32MB on CS0, 32MB on CS1, 32MB on CS2 */
ranges = <0 0 0x08000000 0x02000000
1 0 0x0a000000 0x02000000
2 0 0x0c000000 0x02000000>;
/* SRAM on Colibri nEXT_CS0 */
sram@0,0 {
compatible = "cypress,cy7c1019dv33-10zsxi, mtd-ram";
reg = <0 0 0x00010000>;
#address-cells = <1>;
#size-cells = <1>;
bank-width = <2>;
fsl,weim-cs-timing = <0x00010081 0x00000000 0x04000000
0x00000000 0x04000040 0x00000000>;
};
/* SRAM on Colibri nEXT_CS1 */
sram@1,0 {
compatible = "cypress,cy7c1019dv33-10zsxi, mtd-ram";
reg = <1 0 0x00010000>;
#address-cells = <1>;
#size-cells = <1>;
bank-width = <2>;
fsl,weim-cs-timing = <0x00010081 0x00000000 0x04000000
0x00000000 0x04000040 0x00000000>;
};
};

59
arch/arm/boot/dts/imx6dl-icore.dts Normal file
View File

@ -0,0 +1,59 @@
/*
* Copyright (C) 2016 Amarula Solutions B.V.
* Copyright (C) 2016 Engicam S.r.l.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-icore.dtsi"
/ {
model = "Engicam i.CoreM6 DualLite/Solo Starter Kit";
compatible = "engicam,imx6-icore", "fsl,imx6dl";
};
&can1 {
status = "okay";
};
&can2 {
status = "okay";
};

2
arch/arm/boot/dts/imx6dl-riotboard.dts
View File

@ -390,7 +390,7 @@ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 /* AR8035 pin strapping: MODE#1: pull
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 /* AR8035 pin strapping: MODE#3: pull up */
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 /* AR8035 pin strapping: MODE#0: pull down */
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* GPIO16 -> AR8035 25MHz */
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x180b0 /* AR8035 interrupt */
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>;

2
arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts
View File

@ -105,7 +105,7 @@ ET070001DM6: CoMTFT { /* same as ET0700 but with inverted pixel clock */
pixelclk-active = <1>;
};
};
};
};
};
&can1 {

2
arch/arm/boot/dts/imx6dl-tx6u-801x.dts
View File

@ -199,7 +199,7 @@ ETQ570 {
pixelclk-active = <0>;
};
};
};
};
};
&ipu1_di0_disp0 {

22
arch/arm/boot/dts/imx6q-apalis-ixora.dts
View File

@ -147,28 +147,6 @@ led5-red {
gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
};
};
pwmleds {
compatible = "pwm-leds";
ledpwm1 {
label = "PWM1";
pwms = <&pwm1 0 50000>;
max-brightness = <255>;
};
ledpwm2 {
label = "PWM2";
pwms = <&pwm2 0 50000>;
max-brightness = <255>;
};
ledpwm3 {
label = "PWM3";
pwms = <&pwm3 0 50000>;
max-brightness = <255>;
};
};
};
&backlight {

6
arch/arm/boot/dts/imx6q-b650v3.dts
View File

@ -98,3 +98,9 @@ P05 {
line-name = "PCA9539-P05";
};
};
&usbphy1 {
fsl,tx-cal-45-dn-ohms = <55>;
fsl,tx-cal-45-dp-ohms = <55>;
fsl,tx-d-cal = <100>;
};

3
arch/arm/boot/dts/imx6q-evi.dts
View File

@ -232,10 +232,7 @@ &usdhc1 {
};
&weim {
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x08000000 0x08000000>;
fsl,weim-cs-gpr = <&gpr>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_weimfpga &pinctrl_weimcs>;
status = "okay";

59
arch/arm/boot/dts/imx6q-icore.dts Normal file
View File

@ -0,0 +1,59 @@
/*
* Copyright (C) 2016 Amarula Solutions B.V.
* Copyright (C) 2016 Engicam S.r.l.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-icore.dtsi"
/ {
model = "Engicam i.CoreM6 Quad/Dual Starter Kit";
compatible = "engicam,imx6-icore", "fsl,imx6q";
};
&can1 {
status = "okay";
};
&can2 {
status = "okay";
};

53
arch/arm/boot/dts/imx6q-nitrogen6_som2.dts Normal file
View File

@ -0,0 +1,53 @@
/*
* Copyright 2016 Boundary Devices, Inc.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-nitrogen6_som2.dtsi"
/ {
model = "Boundary Devices i.MX6 Quad Nitrogen6_SOM2 Board";
compatible = "boundary,imx6q-nitrogen6_som2", "fsl,imx6q";
};
&sata {
status = "okay";
};

4
arch/arm/boot/dts/imx6q-novena.dts
View File

@ -451,6 +451,10 @@ &pcie {
status = "okay";
};
&pwm1 {
status = "okay";
};
&sata {
target-supply = <&reg_sata>;
fsl,transmit-level-mV = <1025>;

2
arch/arm/boot/dts/imx6q-phytec-pbab01.dts
View File

@ -23,5 +23,5 @@ chosen {
};
&sata {
status = "okay";
status = "okay";
};

2
arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts
View File

@ -105,7 +105,7 @@ ET070001DM6: CoMTFT { /* same as ET0700 but with inverted pixel clock */
pixelclk-active = <1>;
};
};
};
};
};
&can1 {

2
arch/arm/boot/dts/imx6q-tx6q-1010.dts
View File

@ -199,7 +199,7 @@ ETQ570 {
pixelclk-active = <0>;
};
};
};
};
};
&ipu1_di0_disp0 {

2
arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts
View File

@ -105,7 +105,7 @@ ET070001DM6: CoMTFT { /* same as ET0700 but with inverted pixel clock */
pixelclk-active = <1>;
};
};
};
};
};
&can1 {

2
arch/arm/boot/dts/imx6q-tx6q-1020.dts
View File

@ -199,7 +199,7 @@ ETQ570 {
pixelclk-active = <0>;
};
};
};
};
};
&ds1339 {

53
arch/arm/boot/dts/imx6q-utilite-pro.dts
View File

@ -68,7 +68,41 @@ power {
label = "Power Button";
gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
gpio-key,wakeup;
wakeup-source;
};
};
i2cmux {
compatible = "i2c-mux-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1mux>;
#address-cells = <1>;
#size-cells = <0>;
mux-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
i2c-parent = <&i2c1>;
i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@50 {
compatible = "at24,24c02";
reg = <0x50>;
pagesize = <16>;
};
em3027: rtc@56 {
compatible = "emmicro,em3027";
reg = <0x56>;
};
};
i2c_dvi_ddc: i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
@ -82,17 +116,6 @@ &i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
eeprom@50 {
compatible = "at24,24c02";
reg = <0x50>;
pagesize = <16>;
};
em3027: rtc@56 {
compatible = "emmicro,em3027";
reg = <0x56>;
};
};
&i2c2 {
@ -115,6 +138,12 @@ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};
pinctrl_i2c1mux: i2c1muxgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1

9
arch/arm/boot/dts/imx6qdl-apalis.dtsi
View File

@ -49,7 +49,10 @@ / {
backlight: backlight {
compatible = "pwm-backlight";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_bl_on>;
pwms = <&pwm4 0 5000000>;
enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
@ -620,6 +623,12 @@ MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
>;
};
pinctrl_gpio_bl_on: gpioblon {
fsl,pins = <
MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0
>;
};
pinctrl_gpio_keys: gpio1io04grp {
fsl,pins = <
/* Power button */

14
arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
View File

@ -347,13 +347,13 @@ pinctrl_gpios: gpiosgrp {
fsl,pins = <
MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x100b1
MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1
MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x100b1
MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x100b1
MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x100b1
MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x100b1
MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x100b1
MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x100b1
MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x100b1
MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x100b1
MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x100b1
MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x100b1
MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x100b1
MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x100b1
MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x100b1
MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x100b1
>;
};

890
arch/arm/boot/dts/imx6qdl-colibri.dtsi Normal file
View File

@ -0,0 +1,890 @@
/*
* Copyright 2014-2016 Toradex AG
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Toradex Colibri iMX6DL/S Module";
compatible = "toradex,colibri_imx6dl", "fsl,imx6dl";
backlight: backlight {
compatible = "pwm-backlight";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_bl_on>;
pwms = <&pwm3 0 5000000>;
enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */
status = "disabled";
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "1P8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
reg_2p5v: regulator-2p5v {
compatible = "regulator-fixed";
regulator-name = "2P5V";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_usb_host_vbus: regulator-usb-host-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
regulator-name = "usb_host_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; /* USBH_PEN */
status = "disabled";
};
sound {
compatible = "fsl,imx-audio-sgtl5000";
model = "imx6dl-colibri-sgtl5000";
ssi-controller = <&ssi1>;
audio-codec = <&codec>;
audio-routing =
"Headphone Jack", "HP_OUT",
"LINE_IN", "Line In Jack",
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias";
mux-int-port = <1>;
mux-ext-port = <5>;
};
/* Optional S/PDIF in on SODIMM 88 and out on SODIMM 90, 137 or 168 */
sound_spdif: sound-spdif {
compatible = "fsl,imx-audio-spdif";
model = "imx-spdif";
spdif-controller = <&spdif>;
spdif-in;
spdif-out;
status = "disabled";
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux &pinctrl_mic_gnd>;
status = "okay";
};
/* Optional on SODIMM 55/63 */
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "disabled";
};
/* Optional on SODIMM 178/188 */
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
status = "disabled";
};
/* Colibri SSP */
&ecspi4 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi4>;
status = "disabled";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rmii";
status = "okay";
};
&hdmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi_ddc>;
status = "disabled";
};
/*
* PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
* touch screen controller
*/
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
pmic: pfuze100@08 {
compatible = "fsl,pfuze100";
reg = <0x08>;
regulators {
sw1a_reg: sw1ab {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw1c_reg: sw1c {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw3a_reg: sw3a {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-boot-on;
regulator-always-on;
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
regulator-boot-on;
regulator-always-on;
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-boot-on;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-boot-on;
regulator-always-on;
};
/* vgen1: unused */
vgen2_reg: vgen2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
regulator-boot-on;
regulator-always-on;
};
/* vgen3: unused */
vgen4_reg: vgen4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
vgen5_reg: vgen5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
vgen6_reg: vgen6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
codec: sgtl5000@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clocks = <&clks IMX6QDL_CLK_CKO>;
VDDA-supply = <&reg_2p5v>;
VDDIO-supply = <&reg_3p3v>;
};
/* STMPE811 touch screen controller */
stmpe811@41 {
compatible = "st,stmpe811";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_touch_int>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x41>;
interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio6>;
interrupt-controller;
id = <0>;
blocks = <0x5>;
irq-trigger = <0x1>;
stmpe_touchscreen {
compatible = "st,stmpe-ts";
reg = <0>;
/* 3.25 MHz ADC clock speed */
st,adc-freq = <1>;
/* 8 sample average control */
st,ave-ctrl = <3>;
/* 7 length fractional part in z */
st,fraction-z = <7>;
/*
* 50 mA typical 80 mA max touchscreen drivers
* current limit value
*/
st,i-drive = <1>;
/* 12-bit ADC */
st,mod-12b = <1>;
/* internal ADC reference */
st,ref-sel = <0>;
/* ADC converstion time: 80 clocks */
st,sample-time = <4>;
/* 1 ms panel driver settling time */
st,settling = <3>;
/* 5 ms touch detect interrupt delay */
st,touch-det-delay = <5>;
};
};
};
/*
* I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
*/
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default", "recovery";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_recovery>;
scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
/* Colibri PWM<B> */
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "disabled";
};
/* Colibri PWM<D> */
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "disabled";
};
/* Colibri PWM<A> */
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "disabled";
};
/* Colibri PWM<C> */
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "disabled";
};
/* Optional S/PDIF out on SODIMM 137 */
&spdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spdif>;
status = "disabled";
};
&ssi1 {
status = "okay";
};
/* Colibri UART_A */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
fsl,dte-mode;
uart-has-rtscts;
status = "disabled";
};
/* Colibri UART_B */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_dte>;
fsl,dte-mode;
uart-has-rtscts;
status = "disabled";
};
/* Colibri UART_C */
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3_dte>;
fsl,dte-mode;
status = "disabled";
};
&usbotg {
pinctrl-names = "default";
disable-over-current;
dr_mode = "peripheral";
status = "disabled";
};
/* Colibri MMC */
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
vqmmc-supply = <&reg_3p3v>;
bus-width = <4>;
voltage-ranges = <3300 3300>;
status = "disabled";
};
/* eMMC */
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
vqmmc-supply = <&reg_3p3v>;
bus-width = <8>;
voltage-ranges = <3300 3300>;
non-removable;
status = "okay";
};
&weim {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_weim_sram &pinctrl_weim_cs0
&pinctrl_weim_cs1 &pinctrl_weim_cs2
&pinctrl_weim_rdnwr &pinctrl_weim_npwe>;
#address-cells = <2>;
#size-cells = <1>;
status = "disabled";
};
&iomuxc {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0
MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0
MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0
/* SGTL5000 sys_mclk */
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0
>;
};
pinctrl_cam_mclk: cammclkgrp {
fsl,pins = <
/* Parallel Camera CAM sys_mclk */
MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0
>;
};
pinctrl_ecspi4: ecspi4grp {
fsl,pins = <
MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
/* SPI CS */
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0)
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
>;
};
pinctrl_gpio_bl_on: gpioblon {
fsl,pins = <
MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0
>;
};
pinctrl_gpio_keys: gpiokeys {
fsl,pins = <
/* Power button */
MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0
>;
};
pinctrl_hdmi_ddc: hdmiddcgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_i2c3_recovery: i2c3recoverygrp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1
MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
>;
};
pinctrl_ipu1_csi0: ipu1csi0grp { /* Parallel Camera */
fsl,pins = <
MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0xb0b1
MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0xb0b1
MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0xb0b1
MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0xb0b1
MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0xb0b1
MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0xb0b1
MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0xb0b1
MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0xb0b1
MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0xb0b1
MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0xb0b1
MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0xb0b1
/* Disable PWM pins on camera interface */
MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x40
MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x40
>;
};
pinctrl_ipu1_lcdif: ipu1lcdifgrp {
fsl,pins = <
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xa1
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xa1
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0xa1
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0xa1
MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xa1
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xa1
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xa1
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xa1
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xa1
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xa1
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xa1
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xa1
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xa1
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xa1
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xa1
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xa1
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xa1
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xa1
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xa1
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xa1
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xa1
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xa1
>;
};
pinctrl_mic_gnd: gpiomicgnd {
fsl,pins = <
/* Controls Mic GND, PU or '1' pull Mic GND to GND */
MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x1b0b0
>;
};
pinctrl_mmc_cd: gpiommccd {
fsl,pins = <
MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x80000000
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x00040
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x00040
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
>;
};
pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
fsl,pins = <
/* USBH_EN */
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0f058
>;
};
pinctrl_spdif: spdifgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
>;
};
pinctrl_touch_int: gpiotouchintgrp {
fsl,pins = <
/* STMPE811 interrupt */
MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x1b0b0
>;
};
pinctrl_uart1_dce: uart1dcegrp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
>;
};
/* DTE mode */
pinctrl_uart1_dte: uart1dtegrp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
>;
};
/* Additional DTR, DSR, DCD */
pinctrl_uart1_ctrl: uart1ctrlgrp {
fsl,pins = <
MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
>;
};
pinctrl_uart2_dte: uart2dtegrp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1
MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1
MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1
>;
};
pinctrl_uart3_dte: uart3dtegrp {
fsl,pins = <
MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1
MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1
>;
};
pinctrl_usbc_det: usbcdetgrp {
fsl,pins = <
/* USBC_DET */
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
/* USBC_DET_EN */
MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x0f058
/* USBC_DET_OVERWRITE */
MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x0f058
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
/* eMMC reset */
MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059
>;
};
pinctrl_usdhc3_100mhz: usdhc3100mhzgrp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
/* eMMC reset */
MX6QDL_PAD_SD3_RST__SD3_RESET 0x170b9
>;
};
pinctrl_usdhc3_200mhz: usdhc3200mhzgrp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
/* eMMC reset */
MX6QDL_PAD_SD3_RST__SD3_RESET 0x170f9
>;
};
pinctrl_weim_cs0: weimcs0grp {
fsl,pins = <
/* nEXT_CS0 */
MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
>;
};
pinctrl_weim_cs1: weimcs1grp {
fsl,pins = <
/* nEXT_CS1 */
MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1
>;
};
pinctrl_weim_cs2: weimcs2grp {
fsl,pins = <
/* nEXT_CS2 */
MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0xb0b1
>;
};
pinctrl_weim_sram: weimsramgrp {
fsl,pins = <
MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
/* Data */
MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0
MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0
MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0
MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0
MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0
MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0
MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0
MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0
MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0
MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0
MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0
MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0
MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0
MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0
MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0
MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0
/* Address */
MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
>;
};
pinctrl_weim_rdnwr: weimrdnwr {
fsl,pins = <
MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x0040
MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x130b0
>;
};
pinctrl_weim_npwe: weimnpwe {
fsl,pins = <
MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x0040
MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x130b0
>;
};
/* ADDRESS[16:18] [25] used as GPIO */
pinctrl_weim_gpio_1: weimgpio-1 {
fsl,pins = <
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0
MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0
MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0
MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
>;
};
/* ADDRESS[19:24] used as GPIO */
pinctrl_weim_gpio_2: weimgpio-2 {
fsl,pins = <
MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0
MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0
MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0
MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
>;
};
/* DATA[16:31] used as GPIO */
pinctrl_weim_gpio_3: weimgpio-3 {
fsl,pins = <
MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0
MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0
MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0
MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0
MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0
MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0
MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0
MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0
MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0
MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
>;
};
/* DQM[0:3] used as GPIO */
pinctrl_weim_gpio_4: weimgpio-4 {
fsl,pins = <
MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0
MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0
MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0
MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
>;
};
/* RDY used as GPIO */
pinctrl_weim_gpio_5: weimgpio-5 {
fsl,pins = <
MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0
>;
};
/* ADDRESS[16] DATA[30] used as GPIO */
pinctrl_weim_gpio_6: weimgpio-6 {
fsl,pins = <
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0
>;
};
};

4
arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
View File

@ -153,9 +153,9 @@ &can1 {
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
};
&ecspi3 {

4
arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
View File

@ -154,9 +154,9 @@ &can1 {
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
};
&fec {

4
arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
View File

@ -144,9 +144,9 @@ &can1 {
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
};
&fec {

2
arch/arm/boot/dts/imx6qdl-gw552x.dtsi
View File

@ -291,7 +291,7 @@ pinctrl_uart5: uart5grp {
MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
>;
};
};
pinctrl_wdog: wdoggrp {
fsl,pins = <

265
arch/arm/boot/dts/imx6qdl-icore.dtsi Normal file
View File

@ -0,0 +1,265 @@
/*
* Copyright (C) 2016 Amarula Solutions B.V.
* Copyright (C) 2016 Engicam S.r.l.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
memory {
reg = <0x10000000 0x80000000>;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
reg_usb_h1_vbus: regulator-usb-h1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
regulator-always-on;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
regulator-always-on;
};
rmii_clk: clock-rmii-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>; /* 25MHz for example */
};
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
xceiver-supply = <&reg_3p3v>;
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
xceiver-supply = <&reg_3p3v>;
};
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>;
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&rmii_clk>;
phy-mode = "rmii";
status = "okay";
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_usb_h1_vbus>;
disable-over-current;
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
no-1-8-v;
status = "okay";
};
&iomuxc {
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b1
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020
MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b020
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b020
MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b020
>;
};
pinctrl_gpmi_nand: gpmi-nand {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17070
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10070
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17070
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17070
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17070
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17070
>;
};
};

32
arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
View File

@ -97,15 +97,6 @@ reg_wlan_vmmc: regulator@3 {
};
};
bt_rfkill {
compatible = "rfkill-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_bt_rfkill>;
gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;
name = "bt_rfkill";
type = <2>;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
@ -160,7 +151,7 @@ j46-pin3 {
};
};
backlight_lcd {
backlight-lcd {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@ -169,7 +160,7 @@ backlight_lcd {
status = "okay";
};
backlight_lvds0: backlight_lvds0 {
backlight_lvds0: backlight-lvds0 {
compatible = "pwm-backlight";
pwms = <&pwm4 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@ -178,7 +169,7 @@ backlight_lvds0: backlight_lvds0 {
status = "okay";
};
panel_lvds0 {
panel-lvds0 {
compatible = "hannstar,hsd100pxn1";
backlight = <&backlight_lvds0>;
@ -328,19 +319,6 @@ MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
>;
};
pinctrl_bt_rfkill: bt_rfkillgrp {
fsl,pins = <
/* BT wake */
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
/* BT reset */
MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0b0b0
/* BT reg en */
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0
/* BT host wake irq */
MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x100b0
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
@ -374,7 +352,7 @@ MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>;
};
pinctrl_gpio_keys: gpio_keysgrp {
pinctrl_gpio_keys: gpio-keysgrp {
fsl,pins = <
/* Home Button: J14 pin 5 */
MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0
@ -457,7 +435,7 @@ MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
>;
};
pinctrl_wlan_vmmc: wlan_vmmcgrp {
pinctrl_wlan_vmmc: wlan-vmmcgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b0
>;

18
arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
View File

@ -229,7 +229,7 @@ ttymxc4-rs232 {
};
};
backlight_lcd: backlight_lcd {
backlight_lcd: backlight-lcd {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@ -238,7 +238,7 @@ backlight_lcd: backlight_lcd {
status = "okay";
};
backlight_lvds0: backlight_lvds0 {
backlight_lvds0: backlight-lvds0 {
compatible = "pwm-backlight";
pwms = <&pwm4 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@ -247,7 +247,7 @@ backlight_lvds0: backlight_lvds0 {
status = "okay";
};
backlight_lvds1: backlight_lvds1 {
backlight_lvds1: backlight-lvds1 {
compatible = "pwm-backlight";
pwms = <&pwm2 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@ -282,7 +282,7 @@ lcd_display_out: endpoint {
};
};
panel_lcd {
panel-lcd {
compatible = "okaya,rs800480t-7x0gp";
backlight = <&backlight_lcd>;
@ -293,7 +293,7 @@ lcd_panel_in: endpoint {
};
};
panel_lvds0 {
panel-lvds0 {
compatible = "hannstar,hsd100pxn1";
backlight = <&backlight_lvds0>;
@ -304,7 +304,7 @@ panel_in_lvds0: endpoint {
};
};
panel_lvds1 {
panel-lvds1 {
compatible = "hannstar,hsd100pxn1";
backlight = <&backlight_lvds1>;
@ -447,7 +447,7 @@ touchscreen@38 {
};
&iomuxc {
imx6q-nitrogen6_max {
imx6q-nitrogen6-max {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
@ -504,7 +504,7 @@ MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>;
};
pinctrl_gpio_keys: gpio_keysgrp {
pinctrl_gpio_keys: gpio-keysgrp {
fsl,pins = <
/* Power Button */
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
@ -720,7 +720,7 @@ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
>;
};
pinctrl_wlan_vmmc: wlan_vmmcgrp {
pinctrl_wlan_vmmc: wlan-vmmcgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0

770
arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi Normal file
View File

@ -0,0 +1,770 @@
/*
* Copyright 2016 Boundary Devices, Inc.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
chosen {
stdout-path = &uart2;
};
memory {
reg = <0x10000000 0x40000000>;
};
backlight_lcd: backlight-lcd {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
power-supply = <&reg_3p3v>;
status = "okay";
};
backlight_lvds0: backlight-lvds0 {
compatible = "pwm-backlight";
pwms = <&pwm4 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
power-supply = <&reg_3p3v>;
status = "okay";
};
backlight_lvds1: backlight-lvds1 {
compatible = "gpio-backlight";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_backlight_lvds1>;
gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>;
default-on;
status = "okay";
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
power {
label = "Power Button";
gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
wakeup-source;
};
menu {
label = "Menu";
gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_MENU>;
};
home {
label = "Home";
gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOME>;
};
back {
label = "Back";
gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_BACK>;
};
volume-up {
label = "Volume Up";
gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
};
volume-down {
label = "Volume Down";
gpios = <&gpio7 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
};
};
lcd_display: display@di0 {
compatible = "fsl,imx-parallel-display";
#address-cells = <1>;
#size-cells = <0>;
interface-pix-fmt = "bgr666";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_j15>;
status = "okay";
port@0 {
reg = <0>;
lcd_display_in: endpoint {
remote-endpoint = <&ipu1_di0_disp0>;
};
};
port@1 {
reg = <1>;
lcd_display_out: endpoint {
remote-endpoint = <&lcd_panel_in>;
};
};
};
panel-lcd {
compatible = "okaya,rs800480t-7x0gp";
backlight = <&backlight_lcd>;
port {
lcd_panel_in: endpoint {
remote-endpoint = <&lcd_display_out>;
};
};
};
panel-lvds0 {
compatible = "hannstar,hsd100pxn1";
backlight = <&backlight_lvds0>;
port {
panel_in_lvds0: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
};
panel-lvds1 {
compatible = "hannstar,hsd100pxn1";
backlight = <&backlight_lvds1>;
port {
panel_in_lvds1: endpoint {
remote-endpoint = <&lvds1_out>;
};
};
};
reg_1p8v: regulator-1v8 {
compatible = "regulator-fixed";
regulator-name = "1P8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
reg_2p5v: regulator-2v5 {
compatible = "regulator-fixed";
regulator-name = "2P5V";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
reg_3p3v: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_can_xcvr: regulator-can-xcvr {
compatible = "regulator-fixed";
regulator-name = "CAN XCVR";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can_xcvr>;
gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
};
reg_usb_h1_vbus: regulator-usb-h1-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>;
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_wlan_vmmc: regulator-wlan-vmmc {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wlan_vmmc>;
regulator-name = "reg_wlan_vmmc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>;
startup-delay-us = <70000>;
enable-active-high;
};
sound {
compatible = "fsl,imx6q-nitrogen6_som2-sgtl5000",
"fsl,imx-audio-sgtl5000";
model = "imx6q-nitrogen6_som2-sgtl5000";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sgtl5000>;
ssi-controller = <&ssi1>;
audio-codec = <&codec>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
mux-int-port = <1>;
mux-ext-port = <3>;
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1>;
xceiver-supply = <&reg_can_xcvr>;
status = "okay";
};
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
};
&ecspi1 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
flash: m25p80@0 {
compatible = "microchip,sst25vf016b";
spi-max-frequency = <20000000>;
reg = <0>;
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
fsl,err006687-workaround-present;
status = "okay";
};
&hdmi {
ddc-i2c-bus = <&i2c2>;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
codec: sgtl5000@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clocks = <&clks IMX6QDL_CLK_CKO>;
VDDA-supply = <&reg_2p5v>;
VDDIO-supply = <&reg_3p3v>;
};
rtc@68 {
compatible = "st,rv4162";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rv4162>;
reg = <0x68>;
interrupts-extended = <&gpio6 7 IRQ_TYPE_LEVEL_LOW>;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
touchscreen@04 {
compatible = "eeti,egalax_ts";
reg = <0x04>;
interrupt-parent = <&gpio1>;
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
};
touchscreen@38 {
compatible = "edt,edt-ft5x06";
reg = <0x38>;
interrupt-parent = <&gpio1>;
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
};
};
&iomuxc {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
>;
};
pinctrl_backlight_lvds1: backlight-lvds1grp {
fsl,pins = <
MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x0b0b0
>;
};
pinctrl_can1: can1grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
>;
};
pinctrl_can_xcvr: can-xcvrgrp {
fsl,pins = <
/* Flexcan XCVR enable */
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0b0b0
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x130b0
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0
MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>;
};
pinctrl_gpio_keys: gpio-keysgrp {
fsl,pins = <
/* Power Button */
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
/* Menu Button */
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
/* Home Button */
MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0
/* Back Button */
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
/* Volume Up Button */
MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0
/* Volume Down Button */
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
>;
};
pinctrl_i2c3mux: i2c3muxgrp {
fsl,pins = <
/* PCIe I2C enable */
MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x000b0
>;
};
pinctrl_j15: j15grp {
fsl,pins = <
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
/* PCIe reset */
MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x030b0
MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x030b0
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x030b1
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x030b1
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x030b1
>;
};
pinctrl_rv4162: rv4162grp {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
>;
};
pinctrl_sgtl5000: sgtl5000grp {
fsl,pins = <
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x130b0
MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x130b0
MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x130b0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
>;
};
pinctrl_usbh1: usbh1grp {
fsl,pins = <
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
/* power enable, high active */
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17071
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17071
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17071
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17071
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17071
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0
>;
};
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
>;
};
pinctrl_wlan_vmmc: wlan-vmmcgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x100b0
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x030b0
MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x030b0
MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0
>;
};
};
&ipu1_di0_disp0 {
remote-endpoint = <&lcd_display_in>;
};
&ldb {
status = "okay";
lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
status = "okay";
port@4 {
reg = <4>;
lvds0_out: endpoint {
remote-endpoint = <&panel_in_lvds0>;
};
};
};
lvds-channel@1 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
status = "okay";
port@4 {
reg = <4>;
lvds1_out: endpoint {
remote-endpoint = <&panel_in_lvds1>;
};
};
};
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio6 31 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
&ssi1 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
uart-has-rtscts;
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_usb_h1_vbus>;
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <4>;
non-removable;
vmmc-supply = <&reg_wlan_vmmc>;
cap-power-off-card;
keep-power-in-suspend;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
wlcore: wlcore@2 {
compatible = "ti,wl1271";
reg = <2>;
interrupt-parent = <&gpio6>;
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
ref-clock-frequency = <38400000>;
};
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
bus-width = <4>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
&usdhc4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4>;
bus-width = <8>;
non-removable;
vmmc-supply = <&reg_1p8v>;
keep-power-in-suspend;
status = "okay";
};

12
arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
View File

@ -167,7 +167,7 @@ sound {
mux-ext-port = <3>;
};
backlight_lcd: backlight_lcd {
backlight_lcd: backlight-lcd {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@ -176,7 +176,7 @@ backlight_lcd: backlight_lcd {
status = "okay";
};
backlight_lvds: backlight_lvds {
backlight_lvds: backlight-lvds {
compatible = "pwm-backlight";
pwms = <&pwm4 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@ -211,7 +211,7 @@ lcd_display_out: endpoint {
};
};
lcd_panel {
panel-lcd {
compatible = "okaya,rs800480t-7x0gp";
backlight = <&backlight_lcd>;
@ -222,7 +222,7 @@ lcd_panel_in: endpoint {
};
};
panel {
panel-lvds0 {
compatible = "hannstar,hsd100pxn1";
backlight = <&backlight_lvds>;
@ -413,7 +413,7 @@ MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>;
};
pinctrl_gpio_keys: gpio_keysgrp {
pinctrl_gpio_keys: gpio-keysgrp {
fsl,pins = <
/* Power Button */
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
@ -561,7 +561,7 @@ MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */
>;
};
pinctrl_wlan_vmmc: wlan_vmmcgrp {
pinctrl_wlan_vmmc: wlan-vmmcgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0

6
arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
View File

@ -427,10 +427,10 @@ &usdhc2 {
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3
&pinctrl_usdhc3_cdwp>;
cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
status = "disabled";
status = "disabled";
};

4
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
View File

@ -283,7 +283,7 @@ codec: cs42888@48 {
VD-supply = <&reg_audio>;
VLS-supply = <&reg_audio>;
VLC-supply = <&reg_audio>;
};
};
};
@ -613,8 +613,6 @@ &usdhc3 {
&weim {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x08000000 0x08000000>;
status = "disabled"; /* pin conflict with SPI NOR */

10
arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
View File

@ -153,7 +153,7 @@ sound {
mux-ext-port = <4>;
};
backlight_lcd: backlight_lcd {
backlight_lcd: backlight-lcd {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@ -162,7 +162,7 @@ backlight_lcd: backlight_lcd {
status = "okay";
};
backlight_lvds: backlight_lvds {
backlight_lvds: backlight-lvds {
compatible = "pwm-backlight";
pwms = <&pwm4 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@ -197,7 +197,7 @@ lcd_display_out: endpoint {
};
};
lcd_panel {
panel-lcd {
compatible = "okaya,rs800480t-7x0gp";
backlight = <&backlight_lcd>;
@ -208,7 +208,7 @@ lcd_panel_in: endpoint {
};
};
panel {
panel-lvds0 {
compatible = "hannstar,hsd100pxn1";
backlight = <&backlight_lvds>;
@ -378,7 +378,7 @@ MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>;
};
pinctrl_gpio_keys: gpio_keysgrp {
pinctrl_gpio_keys: gpio-keysgrp {
fsl,pins = <
/* Power Button */
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0

4
arch/arm/boot/dts/imx6qdl-sabresd.dtsi
View File

@ -129,8 +129,8 @@ leds {
pinctrl-0 = <&pinctrl_gpio_leds>;
red {
gpios = <&gpio1 2 0>;
default-state = "on";
gpios = <&gpio1 2 0>;
default-state = "on";
};
};

32
arch/arm/boot/dts/imx6qdl-tx6.dtsi
View File

@ -429,8 +429,8 @@ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b0 /* SPI CS1 */
pinctrl_edt_ft5x06: edt-ft5x06grp {
fsl,pins = <
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Interrupt */
MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* Reset */
MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* Wake */
MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* Reset */
MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* Wake */
>;
};
@ -481,21 +481,21 @@ MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b0 /* Flexcan XCVR enable */
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1
>;
};

2
arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi
View File

@ -28,7 +28,7 @@ MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE */
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 /* RGMII_nRST */
MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x80000000 /* BT_ON */
MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x80000000 /* BT_WAKE */
MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x80000000 /* BT_HOST_WAKE */
MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x80000000 /* BT_HOST_WAKE */
>;
};
};

4
arch/arm/boot/dts/imx6qdl-wandboard.dtsi
View File

@ -129,8 +129,8 @@ MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};

14
arch/arm/boot/dts/imx6qdl.dtsi
View File

@ -13,9 +13,10 @@
#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &fec;
can0 = &can1;
@ -204,9 +205,9 @@ pcie: pcie@0x01000000 {
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
<0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
<&clks IMX6QDL_CLK_LVDS1_GATE>,
<&clks IMX6QDL_CLK_PCIE_REF_125M>;
@ -1092,10 +1093,13 @@ mmdc1: mmdc@021b4000 { /* MMDC1 */
};
weim: weim@021b8000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,imx6q-weim";
reg = <0x021b8000 0x4000>;
interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
fsl,weim-cs-gpr = <&gpr>;
};
ocotp: ocotp@021bc000 {

7
arch/arm/boot/dts/imx6qp.dtsi
View File

@ -85,5 +85,12 @@ ipu2: ipu@02800000 {
pcie: pcie@0x01000000 {
compatible = "fsl,imx6qp-pcie", "snps,dw-pcie";
};
aips-bus@02100000 {
mmdc0: mmdc@021b0000 { /* MMDC0 */
compatible = "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc";
reg = <0x021b0000 0x4000>;
};
};
};
};

7
arch/arm/boot/dts/imx6sl.dtsi
View File

@ -8,11 +8,13 @@
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include "skeleton.dtsi"
#include "imx6sl-pinfunc.h"
#include <dt-bindings/clock/imx6sl-clock.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &fec;
gpio0 = &gpio1;
@ -893,8 +895,11 @@ rngb: rngb@021b4000 {
};
weim: weim@021b8000 {
#address-cells = <2>;
#size-cells = <1>;
reg = <0x021b8000 0x4000>;
interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
fsl,weim-cs-gpr = <&gpr>;
};
ocotp: ocotp@021bc000 {

16
arch/arm/boot/dts/imx6sx-sdb.dtsi
View File

@ -192,10 +192,10 @@ &i2c3 {
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
codec: wm8962@1a {
compatible = "wlf,wm8962";
@ -290,6 +290,14 @@ &usbotg2 {
status = "okay";
};
&usbphy1 {
fsl,tx-d-cal = <106>;
};
&usbphy2 {
fsl,tx-d-cal = <106>;
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;

69
arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts Normal file
View File

@ -0,0 +1,69 @@
/*
* Copyright (c) 2016 Andreas Färber
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6sx-udoo-neo.dtsi"
/ {
model = "UDOO Neo Basic";
compatible = "udoo,neobasic", "fsl,imx6sx";
memory {
reg = <0x80000000 0x20000000>;
};
};
&fec1 {
phy-handle = <&ethphy1>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
};
};

54
arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts Normal file
View File

@ -0,0 +1,54 @@
/*
* Copyright (c) 2016 Andreas Färber
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6sx-udoo-neo.dtsi"
/ {
model = "UDOO Neo Extended";
compatible = "udoo,neoextended", "fsl,imx6sx";
memory {
reg = <0x80000000 0x40000000>;
};
};

69
arch/arm/boot/dts/imx6sx-udoo-neo-full.dts Normal file
View File

@ -0,0 +1,69 @@
/*
* Copyright (c) 2016 Andreas Färber
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6sx-udoo-neo.dtsi"
/ {
model = "UDOO Neo Full";
compatible = "udoo,neofull", "fsl,imx6sx";
memory {
reg = <0x80000000 0x40000000>;
};
};
&fec1 {
phy-handle = <&ethphy1>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
};
};

293
arch/arm/boot/dts/imx6sx-udoo-neo.dtsi Normal file
View File

@ -0,0 +1,293 @@
/*
* Copyright (c) 2016 Andreas Färber
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "imx6sx.dtsi"
/ {
compatible = "fsl,imx6sx";
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
red {
label = "udoo-neo:red:mmc";
gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "mmc0";
};
orange {
label = "udoo-neo:orange:user";
gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>;
default-state = "keep";
};
};
reg_sdio_pwr: regulator-sdio-pwr {
compatible = "regulator-fixed";
gpio = <&gpio6 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-name = "SDIO_PWR";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
};
&cpu0 {
arm-supply = <&sw1a_reg>;
soc-supply = <&sw1c_reg>;
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clock-frequency = <100000>;
status = "okay";
pmic: pmic@08 {
compatible = "fsl,pfuze3000";
reg = <0x08>;
regulators {
sw1a_reg: sw1a {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1475000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw1c_reg: sw1b {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1475000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw2_reg: sw2 {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1850000>;
regulator-boot-on;
regulator-always-on;
};
sw3a_reg: sw3 {
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1650000>;
regulator-boot-on;
regulator-always-on;
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-boot-on;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-boot-on;
regulator-always-on;
};
vgen1_reg: vldo1 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen2_reg: vldo2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen3_reg: vccsd {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen4_reg: v33 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen5_reg: vldo3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen6_reg: vldo4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
};
&iomuxc {
pinctrl_enet1: enet1grp {
fsl,pins =
<MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0xa0b1>,
<MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1>,
<MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1>,
<MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1>,
<MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1>,
<MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1>,
<MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x3081>,
<MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x3081>,
<MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081>,
<MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081>,
<MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081>,
<MX6SX_PAD_RGMII1_RXC__ENET1_RX_ER 0x3081>,
<MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins =
<MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1>,
<MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1>;
};
pinctrl_uart1: uart1grp {
fsl,pins =
<MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1>,
<MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1>;
};
pinctrl_uart2: uart2grp {
fsl,pins =
<MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1>,
<MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1>;
};
pinctrl_uart5: uart5grp {
fsl,pins =
<MX6SX_PAD_SD4_DATA4__UART5_RX 0x1b0b1>,
<MX6SX_PAD_SD4_DATA5__UART5_TX 0x1b0b1>;
};
pinctrl_uart6: uart6grp {
fsl,pins =
<MX6SX_PAD_CSI_DATA00__UART6_RI_B 0x1b0b1>,
<MX6SX_PAD_CSI_DATA01__UART6_DSR_B 0x1b0b1>,
<MX6SX_PAD_CSI_DATA02__UART6_DTR_B 0x1b0b1>,
<MX6SX_PAD_CSI_DATA03__UART6_DCD_B 0x1b0b1>,
<MX6SX_PAD_CSI_DATA04__UART6_RX 0x1b0b1>,
<MX6SX_PAD_CSI_DATA05__UART6_TX 0x1b0b1>,
<MX6SX_PAD_CSI_DATA06__UART6_RTS_B 0x1b0b1>,
<MX6SX_PAD_CSI_DATA07__UART6_CTS_B 0x1b0b1>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins =
<MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059>,
<MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059>,
<MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059>,
<MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059>,
<MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059>,
<MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059>,
<MX6SX_PAD_SD1_DATA0__GPIO6_IO_2 0x17059>; /* CD */
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
/* Cortex-M4 serial */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "disabled";
};
/* Arduino serial */
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "disabled";
};
&uart6 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart6>;
uart-has-rtscts;
status = "disabled";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
vmmc-supply = <&reg_sdio_pwr>;
bus-width = <4>;
cd-gpios = <&gpio6 2 GPIO_ACTIVE_LOW>;
no-1-8-v;
keep-power-in-suspend;
wakeup-source;
status = "okay";
};

17
arch/arm/boot/dts/imx6sx.dtsi
View File

@ -11,9 +11,11 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "imx6sx-pinfunc.h"
#include "skeleton.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
aliases {
can0 = &flexcan1;
can1 = &flexcan2;
@ -858,7 +860,7 @@ fec1: ethernet@02188000 {
fsl,num-tx-queues=<3>;
fsl,num-rx-queues=<3>;
status = "disabled";
};
};
mlb: mlb@0218c000 {
reg = <0x0218c000 0x4000>;
@ -968,10 +970,13 @@ fec2: ethernet@021b4000 {
};
weim: weim@021b8000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
reg = <0x021b8000 0x4000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
fsl,weim-cs-gpr = <&gpr>;
};
ocotp: ocotp@021bc000 {
@ -1143,7 +1148,7 @@ csi2: csi@0221c000 {
lcdif1: lcdif@02220000 {
compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
reg = <0x02220000 0x4000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>;
clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
<&clks IMX6SX_CLK_LCDIF_APB>,
<&clks IMX6SX_CLK_DISPLAY_AXI>;
@ -1154,7 +1159,7 @@ lcdif1: lcdif@02220000 {
lcdif2: lcdif@02224000 {
compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
reg = <0x02224000 0x4000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>;
clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
<&clks IMX6SX_CLK_LCDIF_APB>,
<&clks IMX6SX_CLK_DISPLAY_AXI>;
@ -1181,7 +1186,7 @@ adc1: adc@02280000 {
fsl,adck-max-frequency = <30000000>, <40000000>,
<20000000>;
status = "disabled";
};
};
adc2: adc@02284000 {
compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
@ -1192,7 +1197,7 @@ adc2: adc@02284000 {
fsl,adck-max-frequency = <30000000>, <40000000>,
<20000000>;
status = "disabled";
};
};
wdog3: wdog@02288000 {
compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";

10
arch/arm/boot/dts/imx6ul-14x14-evk.dts
View File

@ -225,7 +225,7 @@ &uart2 {
};
&usbotg1 {
dr_mode = "peripheral";
dr_mode = "otg";
status = "okay";
};
@ -235,6 +235,14 @@ &usbotg2 {
status = "okay";
};
&usbphy1 {
fsl,tx-d-cal = <106>;
};
&usbphy2 {
fsl,tx-d-cal = <106>;
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;

147
arch/arm/boot/dts/imx6ul-liteboard.dts Normal file
View File

@ -0,0 +1,147 @@
/*
* Copyright 2016 Grinn
*
* Author: Marcin Niestroj <m.niestroj@grinn-global.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6ul-litesom.dtsi"
/ {
model = "Grinn i.MX6UL liteBoard";
compatible = "grinn,imx6ul-liteboard", "grinn,imx6ul-litesom",
"fsl,imx6ul";
chosen {
stdout-path = &uart1;
};
reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg1_vbus>;
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio2 8 GPIO_ACTIVE_LOW>;
};
};
&iomuxc {
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
>;
};
pinctrl_usb_otg1_vbus: usb-otg1-vbus {
fsl,pins = <
MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x79
>;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-mode = "rmii";
phy-handle = <&ethphy0>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
reg = <0>;
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usbotg1 {
vbus-supply = <&reg_usb_otg1_vbus>;
dr_mode = "host";
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
no-1-8-v;
keep-power-in-suspend;
wakeup-source;
status = "okay";
};

82
arch/arm/boot/dts/imx6ul-litesom.dtsi Normal file
View File

@ -0,0 +1,82 @@
/*
* Copyright 2016 Grinn
*
* Author: Marcin Niestroj <m.niestroj@grinn-global.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "imx6ul.dtsi"
/ {
model = "Grinn i.MX6UL liteSOM";
compatible = "grinn,imx6ul-litesom", "fsl,imx6ul";
memory {
reg = <0x80000000 0x20000000>;
};
};
&iomuxc {
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17059
>;
};
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
no-1-8-v;
non-removable;
keep-power-in-suspend;
wakeup-source;
bus-width = <8>;
status = "okay";
};

4
arch/arm/boot/dts/imx6ul.dtsi
View File

@ -11,9 +11,11 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "imx6ul-pinfunc.h"
#include "skeleton.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &fec1;
ethernet1 = &fec2;

52
arch/arm/boot/dts/imx6ull-14x14-evk.dts Normal file
View File

@ -0,0 +1,52 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "imx6ul-14x14-evk.dts"
/ {
model = "Freescale i.MX6 UlltraLite 14x14 EVK Board";
compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";
};
&clks {
assigned-clocks = <&clks IMX6UL_CLK_PLL3_PFD2>;
assigned-clock-rates = <320000000>;
};

56
arch/arm/boot/dts/imx6ull-pinfunc.h Normal file
View File

@ -0,0 +1,56 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __DTS_IMX6ULL_PINFUNC_H
#define __DTS_IMX6ULL_PINFUNC_H
#include "imx6ul-pinfunc.h"
/*
* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
#define MX6ULL_PAD_ENET2_RX_DATA0__EPDC_SDDO08 0x00E4 0x0370 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET2_RX_DATA1__EPDC_SDDO09 0x00E8 0x0374 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET2_RX_EN__EPDC_SDDO10 0x00EC 0x0378 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET2_TX_DATA0__EPDC_SDDO11 0x00F0 0x037C 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET2_TX_DATA1__EPDC_SDDO12 0x00F4 0x0380 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET2_TX_EN__EPDC_SDDO13 0x00F8 0x0384 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET2_TX_CLK__EPDC_SDDO14 0x00FC 0x0388 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET2_RX_ER__EPDC_SDDO15 0x0100 0x038C 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_CLK__EPDC_SDCLK 0x0104 0x0390 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_ENABLE__EPDC_SDLE 0x0108 0x0394 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_HSYNC__EPDC_SDOE 0x010C 0x0398 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_VSYNC__EPDC_SDCE0 0x0110 0x039C 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_RESET__EPDC_GDOE 0x0114 0x03A0 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA00__EPDC_SDDO00 0x0118 0x03A4 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA01__EPDC_SDDO01 0x011C 0x03A8 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA02__EPDC_SDDO02 0x0120 0x03AC 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA03__EPDC_SDDO03 0x0124 0x03B0 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA04__EPDC_SDDO04 0x0128 0x03B4 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA05__EPDC_SDDO05 0x012C 0x03B8 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA06__EPDC_SDDO06 0x0130 0x03BC 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA07__EPDC_SDDO07 0x0134 0x03C0 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA14__EPDC_SDSHR 0x0150 0x03DC 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA15__EPDC_GDRL 0x0154 0x03E0 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA16__EPDC_GDCLK 0x0158 0x03E4 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA17__EPDC_GDSP 0x015C 0x03E8 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA21__EPDC_SDCE1 0x016C 0x03F8 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_MCLK__ESAI_TX3_RX2 0x01D4 0x0460 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_PIXCLK__ESAI_TX2_RX3 0x01D8 0x0464 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_VSYNC__ESAI_TX4_RX1 0x01DC 0x0468 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_HSYNC__ESAI_TX1 0x01E0 0x046C 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_DATA00__ESAI_TX_HF_CLK 0x01E4 0x0470 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_DATA01__ESAI_RX_HF_CLK 0x01E8 0x0474 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_DATA02__ESAI_RX_FS 0x01EC 0x0478 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_DATA03__ESAI_RX_CLK 0x01F0 0x047C 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_DATA04__ESAI_TX_FS 0x01F4 0x0480 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_DATA05__ESAI_TX_CLK 0x01F8 0x0484 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_DATA06__ESAI_TX5_RX0 0x01FC 0x0488 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_DATA07__ESAI_T0 0x0200 0x048C 0x0000 0x9 0x0
#endif /* __DTS_IMX6ULL_PINFUNC_H */

43
arch/arm/boot/dts/imx6ull.dtsi Normal file
View File

@ -0,0 +1,43 @@
/*
* Copyright 2016 Freescale Semiconductor, Inc.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "imx6ul.dtsi"
#include "imx6ull-pinfunc.h"

4
arch/arm/boot/dts/imx7s.dtsi
View File

@ -46,9 +46,11 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "imx7d-pinfunc.h"
#include "skeleton.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
aliases {
gpio0 = &gpio1;
gpio1 = &gpio2;

84
arch/arm/boot/dts/ls1021a.dtsi
View File

@ -47,6 +47,7 @@
#include "skeleton64.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "fsl,ls1021a";
@ -70,14 +71,15 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@f00 {
cpu0: cpu@f00 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0xf00>;
clocks = <&cluster1_clk>;
#cooling-cells = <2>;
};
cpu@f01 {
cpu1: cpu@f01 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0xf01>;
@ -251,6 +253,84 @@ cluster1_clk: clk0c0@0 {
};
};
tmu: tmu@1f00000 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f00000 0x0 0x10000>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x30061>;
fsl,tmu-calibration = <0x00000000 0x0000000f
0x00000001 0x00000017
0x00000002 0x0000001e
0x00000003 0x00000026
0x00000004 0x0000002e
0x00000005 0x00000035
0x00000006 0x0000003d
0x00000007 0x00000044
0x00000008 0x0000004c
0x00000009 0x00000053
0x0000000a 0x0000005b
0x0000000b 0x00000064
0x00010000 0x00000011
0x00010001 0x0000001c
0x00010002 0x00000024
0x00010003 0x0000002b
0x00010004 0x00000034
0x00010005 0x00000039
0x00010006 0x00000042
0x00010007 0x0000004c
0x00010008 0x00000051
0x00010009 0x0000005a
0x0001000a 0x00000063
0x00020000 0x00000013
0x00020001 0x00000019
0x00020002 0x00000024
0x00020003 0x0000002c
0x00020004 0x00000035
0x00020005 0x0000003d
0x00020006 0x00000046
0x00020007 0x00000050
0x00020008 0x00000059
0x00030000 0x00000002
0x00030001 0x0000000d
0x00030002 0x00000019
0x00030003 0x00000024>;
#thermal-sensor-cells = <1>;
};
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 0>;
trips {
cpu_alert: cpu-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit: cpu-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
};
dspi0: dspi@2100000 {
compatible = "fsl,ls1021a-v1.0-dspi";
#address-cells = <1>;

4
arch/arm/boot/dts/vf-colibri.dtsi
View File

@ -108,6 +108,10 @@ &edma0 {
status = "okay";
};
&edma1 {
status = "okay";
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1>;

14
arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
View File

@ -499,13 +499,6 @@ i2c@4 {
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
@ -663,13 +656,6 @@ VF610_PAD_PTA23__I2C2_SDA 0x37ff
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
VF610_PAD_PTA30__I2C3_SCL 0x37ff
VF610_PAD_PTA31__I2C3_SDA 0x37ff
>;
};
pinctrl_leds_debug: pinctrl-leds-debug {
fsl,pins = <
VF610_PAD_PTD20__GPIO_74 0x31c2

18
arch/arm/boot/dts/vfxxx.dtsi
View File

@ -194,6 +194,9 @@ dspi0: dspi0@4002c000 {
clocks = <&clks VF610_CLK_DSPI0>;
clock-names = "dspi";
spi-num-chipselects = <6>;
dmas = <&edma1 1 12>,
<&edma1 1 13>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -206,6 +209,9 @@ dspi1: dspi1@4002d000 {
clocks = <&clks VF610_CLK_DSPI1>;
clock-names = "dspi";
spi-num-chipselects = <4>;
dmas = <&edma1 1 14>,
<&edma1 1 15>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -520,6 +526,12 @@ edma1: dma-controller@40098000 {
status = "disabled";
};
ocotp: ocotp@400a5000 {
compatible = "fsl,vf610-ocotp";
reg = <0x400a5000 0x1000>;
clocks = <&clks VF610_CLK_OCOTP>;
};
snvs0: snvs@400a7000 {
compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
reg = <0x400a7000 0x2000>;
@ -561,6 +573,9 @@ dspi2: dspi2@400ac000 {
clocks = <&clks VF610_CLK_DSPI2>;
clock-names = "dspi";
spi-num-chipselects = <2>;
dmas = <&edma1 0 10>,
<&edma1 0 11>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -573,6 +588,9 @@ dspi3: dspi3@400ad000 {
clocks = <&clks VF610_CLK_DSPI3>;
clock-names = "dspi";
spi-num-chipselects = <2>;
dmas = <&edma1 0 12>,
<&edma1 0 13>;
dma-names = "rx", "tx";
status = "disabled";
};