mirror of https://gitee.com/openkylin/linux.git
ARM: LPAE: use 64-bit accessors for TTBR registers
This patch adds TTBR accessor macros, and modifies cpu_get_pgd() and the LPAE version of cpu_set_reserved_ttbr0() to use these instead. In the process, we also fix these functions to correctly handle cases where the physical address lies beyond the 4G limit of 32-bit addressing. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Acked-by: Nicolas Pitre <nico@linaro.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Subash Patel <subash.rp@samsung.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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@ -116,13 +116,25 @@ extern void cpu_resume(void);
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#define cpu_switch_mm(pgd,mm) cpu_do_switch_mm(virt_to_phys(pgd),mm)
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#define cpu_switch_mm(pgd,mm) cpu_do_switch_mm(virt_to_phys(pgd),mm)
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#ifdef CONFIG_ARM_LPAE
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#ifdef CONFIG_ARM_LPAE
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#define cpu_get_ttbr(nr) \
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({ \
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u64 ttbr; \
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__asm__("mrrc p15, " #nr ", %Q0, %R0, c2" \
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: "=r" (ttbr)); \
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ttbr; \
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})
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#define cpu_set_ttbr(nr, val) \
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do { \
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u64 ttbr = val; \
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__asm__("mcrr p15, " #nr ", %Q0, %R0, c2" \
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: : "r" (ttbr)); \
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} while (0)
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#define cpu_get_pgd() \
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#define cpu_get_pgd() \
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({ \
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({ \
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unsigned long pg, pg2; \
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u64 pg = cpu_get_ttbr(0); \
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__asm__("mrrc p15, 0, %0, %1, c2" \
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: "=r" (pg), "=r" (pg2) \
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: \
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: "cc"); \
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pg &= ~(PTRS_PER_PGD*sizeof(pgd_t)-1); \
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pg &= ~(PTRS_PER_PGD*sizeof(pgd_t)-1); \
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(pgd_t *)phys_to_virt(pg); \
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(pgd_t *)phys_to_virt(pg); \
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})
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})
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@ -20,6 +20,7 @@
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#include <asm/smp_plat.h>
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#include <asm/smp_plat.h>
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#include <asm/thread_notify.h>
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#include <asm/thread_notify.h>
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#include <asm/tlbflush.h>
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#include <asm/tlbflush.h>
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#include <asm/proc-fns.h>
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/*
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/*
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* On ARMv6, we have the following structure in the Context ID:
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* On ARMv6, we have the following structure in the Context ID:
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@ -55,17 +56,11 @@ static cpumask_t tlb_flush_pending;
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#ifdef CONFIG_ARM_LPAE
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#ifdef CONFIG_ARM_LPAE
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static void cpu_set_reserved_ttbr0(void)
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static void cpu_set_reserved_ttbr0(void)
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{
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{
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unsigned long ttbl = __pa(swapper_pg_dir);
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unsigned long ttbh = 0;
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/*
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/*
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* Set TTBR0 to swapper_pg_dir which contains only global entries. The
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* Set TTBR0 to swapper_pg_dir which contains only global entries. The
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* ASID is set to 0.
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* ASID is set to 0.
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*/
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*/
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asm volatile(
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cpu_set_ttbr(0, __pa(swapper_pg_dir));
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" mcrr p15, 0, %0, %1, c2 @ set TTBR0\n"
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:
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: "r" (ttbl), "r" (ttbh));
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isb();
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isb();
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}
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}
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#else
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#else
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