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drm/i915: Don't pass "mem_value" to ilk_compute_fbc_wm 

The FBC watermark doesn't depend on the latency value, so no point in
passing it in.

Note: It actually depends upon the latency, but only through priv_val
...

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Add review comment from Paulo to the commit message.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ville Syrjälä 2013-07-05 11:57:19 +03:00 committed by Daniel Vetter
parent 23297044ac
commit 1fda9882ca
1 changed files with 2 additions and 3 deletions
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5
drivers/gpu/drm/i915/intel_pm.c
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@ -2260,8 +2260,7 @@ static uint32_t ilk_compute_cur_wm(struct hsw_pipe_wm_parameters *params,
/* Only for WM_LP. */
static uint32_t ilk_compute_fbc_wm(struct hsw_pipe_wm_parameters *params,
uint32_t pri_val,
uint32_t mem_value)
uint32_t pri_val)
{
if (!params->active)
return 0;
@ -2284,7 +2283,7 @@ static bool hsw_compute_lp_wm(uint32_t mem_value, struct hsw_wm_maximums *max,
pri_val[pipe] = ilk_compute_pri_wm(p, mem_value, true);
spr_val[pipe] = ilk_compute_spr_wm(p, mem_value);
cur_val[pipe] = ilk_compute_cur_wm(p, mem_value);
fbc_val[pipe] = ilk_compute_fbc_wm(p, pri_val[pipe], mem_value);
fbc_val[pipe] = ilk_compute_fbc_wm(p, pri_val[pipe]);
}
result->pri_val = max3(pri_val[0], pri_val[1], pri_val[2]);