mirror of https://gitee.com/openkylin/linux.git
ARM: S3C24XX: add dma pdata for s3c2410, s3c2440 and s3c2442
s3c2410 and s3c2442 share the same dma channels while s3c2440 has slight differences. But on all three the reachable sources per dma channel has constraints attached and thus encodes the usable combinations using the S3C24XX_DMA_CHANREQ macro. This also fixes the warning about s3c2410_dma_resource being unused as reported by Olof Johansson. Reported-by: Olof Johansson <olof@lixom.net> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Heiko Stuebner
Kukjin Kim
parent
681a2fd260
commit
1fecf8958e
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@ -343,6 +343,50 @@ static struct resource s3c2410_dma_resource[] = {
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};
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#endif
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#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2442)
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static struct s3c24xx_dma_channel s3c2410_dma_channels[DMACH_MAX] = {
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[DMACH_XD0] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 0), },
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[DMACH_XD1] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 1), },
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[DMACH_SDI] = { S3C24XX_DMA_APB, false, S3C24XX_DMA_CHANREQ(2, 0) |
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S3C24XX_DMA_CHANREQ(2, 2) |
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S3C24XX_DMA_CHANREQ(1, 3),
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},
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[DMACH_SPI0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 1), },
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[DMACH_SPI1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 3), },
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[DMACH_UART0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 0), },
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[DMACH_UART1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 1), },
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[DMACH_UART2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 3), },
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[DMACH_TIMER] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 0) |
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S3C24XX_DMA_CHANREQ(3, 2) |
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S3C24XX_DMA_CHANREQ(3, 3),
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},
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[DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 1) |
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S3C24XX_DMA_CHANREQ(1, 2),
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},
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[DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 2), },
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[DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 0), },
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[DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 1), },
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[DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 2), },
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[DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), },
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};
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static struct s3c24xx_dma_platdata s3c2410_dma_platdata = {
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.num_phy_channels = 4,
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.channels = s3c2410_dma_channels,
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.num_channels = DMACH_MAX,
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};
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struct platform_device s3c2410_device_dma = {
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.name = "s3c2410-dma",
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.id = 0,
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.num_resources = ARRAY_SIZE(s3c2410_dma_resource),
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.resource = s3c2410_dma_resource,
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.dev = {
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.platform_data = &s3c2410_dma_platdata,
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},
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};
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#endif
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#ifdef CONFIG_CPU_S3C2412
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static struct s3c24xx_dma_channel s3c2412_dma_channels[DMACH_MAX] = {
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[DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 },
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@ -384,6 +428,62 @@ struct platform_device s3c2412_device_dma = {
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};
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#endif
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#if defined(CONFIG_CPU_S3C2440)
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static struct s3c24xx_dma_channel s3c2440_dma_channels[DMACH_MAX] = {
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[DMACH_XD0] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 0), },
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[DMACH_XD1] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 1), },
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[DMACH_SDI] = { S3C24XX_DMA_APB, false, S3C24XX_DMA_CHANREQ(2, 0) |
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S3C24XX_DMA_CHANREQ(6, 1) |
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S3C24XX_DMA_CHANREQ(2, 2) |
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S3C24XX_DMA_CHANREQ(1, 3),
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},
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[DMACH_SPI0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 1), },
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[DMACH_SPI1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 3), },
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[DMACH_UART0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 0), },
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[DMACH_UART1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 1), },
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[DMACH_UART2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 3), },
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[DMACH_TIMER] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 0) |
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S3C24XX_DMA_CHANREQ(3, 2) |
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S3C24XX_DMA_CHANREQ(3, 3),
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},
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[DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 1) |
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S3C24XX_DMA_CHANREQ(1, 2),
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},
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[DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(5, 0) |
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S3C24XX_DMA_CHANREQ(0, 2),
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},
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[DMACH_PCM_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(6, 0) |
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S3C24XX_DMA_CHANREQ(5, 2),
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},
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[DMACH_PCM_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(5, 1) |
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S3C24XX_DMA_CHANREQ(6, 3),
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},
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[DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(6, 2) |
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S3C24XX_DMA_CHANREQ(5, 3),
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},
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[DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 0), },
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[DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 1), },
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[DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 2), },
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[DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), },
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};
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static struct s3c24xx_dma_platdata s3c2440_dma_platdata = {
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.num_phy_channels = 4,
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.channels = s3c2440_dma_channels,
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.num_channels = DMACH_MAX,
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};
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struct platform_device s3c2440_device_dma = {
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.name = "s3c2410-dma",
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.id = 0,
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.num_resources = ARRAY_SIZE(s3c2410_dma_resource),
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.resource = s3c2410_dma_resource,
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.dev = {
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.platform_data = &s3c2440_dma_platdata,
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},
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};
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#endif
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#if defined(CONFIG_CPUS_3C2443) || defined(CONFIG_CPU_S3C2416)
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static struct resource s3c2443_dma_resource[] = {
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[0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA),
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@ -109,7 +109,9 @@ extern void s3c2443_init_irq(void);
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extern struct syscore_ops s3c24xx_irq_syscore_ops;
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extern struct platform_device s3c2410_device_dma;
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extern struct platform_device s3c2412_device_dma;
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extern struct platform_device s3c2440_device_dma;
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extern struct platform_device s3c2443_device_dma;
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#endif /* __ARCH_ARM_MACH_S3C24XX_COMMON_H */
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@ -9,6 +9,9 @@
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* any later version.
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*/
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/* Helper to encode the source selection constraints for early s3c socs. */
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#define S3C24XX_DMA_CHANREQ(src, chan) ((BIT(3) | src) << chan * 4)
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enum s3c24xx_dma_bus {
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S3C24XX_DMA_APB,
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S3C24XX_DMA_AHB,
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