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clk: exynos5420: Fix incorrect placement of __initdata 

__initdata should be placed between the variable name and equal
sign for the variable to be placed in the intended section.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Sachin Kamat 2013-08-07 10:18:39 +05:30 committed by Mike Turquette
parent b6993ecb87
commit 202e5ae945
1 changed files with 3 additions and 3 deletions
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6
drivers/clk/samsung/clk-exynos5420.c
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@ -147,7 +147,7 @@ enum exynos5420_clks {
* list of controller registers to be saved and restored during a * list of controller registers to be saved and restored during a
* suspend/resume cycle. * suspend/resume cycle.
*/ */
static __initdata unsigned long exynos5420_clk_regs[] = { static unsigned long exynos5420_clk_regs[] __initdata = {
SRC_CPU, SRC_CPU,
DIV_CPU0, DIV_CPU0,
DIV_CPU1, DIV_CPU1,
@ -727,7 +727,7 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
GATE(smmu_mscl2, "smmu_mscl2", "aclk400_mscl", GATE_IP_MSCL, 10, 0, 0), GATE(smmu_mscl2, "smmu_mscl2", "aclk400_mscl", GATE_IP_MSCL, 10, 0, 0),
}; };
static struct __initdata samsung_pll_clock exynos5420_plls[nr_plls] = { static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = {
[apll] = PLL(pll_2550, fout_apll, "fout_apll", "fin_pll", APLL_LOCK, [apll] = PLL(pll_2550, fout_apll, "fout_apll", "fin_pll", APLL_LOCK,
APLL_CON0, NULL), APLL_CON0, NULL),
[cpll] = PLL(pll_2550, fout_mpll, "fout_mpll", "fin_pll", MPLL_LOCK, [cpll] = PLL(pll_2550, fout_mpll, "fout_mpll", "fin_pll", MPLL_LOCK,
@ -752,7 +752,7 @@ static struct __initdata samsung_pll_clock exynos5420_plls[nr_plls] = {
KPLL_CON0, NULL), KPLL_CON0, NULL),
}; };
static __initdata struct of_device_id ext_clk_match[] = { static struct of_device_id ext_clk_match[] __initdata = {
{ .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, }, { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
{ }, { },
}; };