mirror of https://gitee.com/openkylin/linux.git
net: mvpp2: use "dma" instead of "phys" where appropriate
As indicated by Russell King, the mvpp2 driver currently uses a lot "phys" or "phys_addr" to store what really is a DMA address. This commit clarifies this by using "dma" or "dma_addr" where appropriate. This is especially important as we are going to introduce more changes where the distinction between physical address and DMA address will be key. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Thomas Petazzoni
David S. Miller
parent
aee441193e
commit
20396136fb
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@ -746,7 +746,7 @@ struct mvpp2_tx_desc {
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u8 packet_offset; /* the offset from the buffer beginning */
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u8 phys_txq; /* destination queue ID */
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u16 data_size; /* data size of transmitted packet in bytes */
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u32 buf_phys_addr; /* physical addr of transmitted buffer */
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u32 buf_dma_addr; /* physical addr of transmitted buffer */
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u32 buf_cookie; /* cookie for access to TX buffer in tx path */
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u32 reserved1[3]; /* hw_cmd (for future use, BM, PON, PNC) */
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u32 reserved2; /* reserved (for future use) */
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@ -756,7 +756,7 @@ struct mvpp2_rx_desc {
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u32 status; /* info about received packet */
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u16 reserved1; /* parser_info (for future use, PnC) */
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u16 data_size; /* size of received packet in bytes */
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u32 buf_phys_addr; /* physical address of the buffer */
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u32 buf_dma_addr; /* physical address of the buffer */
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u32 buf_cookie; /* cookie for access to RX buffer in rx path */
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u16 reserved2; /* gem_port_id (for future use, PON) */
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u16 reserved3; /* csum_l4 (for future use, PnC) */
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@ -772,7 +772,7 @@ struct mvpp2_txq_pcpu_buf {
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struct sk_buff *skb;
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/* Physical address of transmitted buffer */
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dma_addr_t phys;
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dma_addr_t dma;
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/* Size transmitted */
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size_t size;
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@ -825,7 +825,7 @@ struct mvpp2_tx_queue {
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struct mvpp2_tx_desc *descs;
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/* DMA address of the Tx DMA descriptors array */
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dma_addr_t descs_phys;
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dma_addr_t descs_dma;
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/* Index of the last Tx DMA descriptor */
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int last_desc;
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@ -848,7 +848,7 @@ struct mvpp2_rx_queue {
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struct mvpp2_rx_desc *descs;
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/* DMA address of the RX DMA descriptors array */
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dma_addr_t descs_phys;
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dma_addr_t descs_dma;
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/* Index of the last RX DMA descriptor */
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int last_desc;
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@ -922,15 +922,15 @@ struct mvpp2_bm_pool {
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/* BPPE virtual base address */
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u32 *virt_addr;
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/* BPPE physical base address */
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dma_addr_t phys_addr;
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/* BPPE DMA base address */
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dma_addr_t dma_addr;
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/* Ports using BM pool */
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u32 port_map;
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};
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struct mvpp2_buff_hdr {
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u32 next_buff_phys_addr;
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u32 next_buff_dma_addr;
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u32 next_buff_virt_addr;
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u16 byte_count;
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u16 info;
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@ -982,7 +982,7 @@ static void mvpp2_txq_inc_put(struct mvpp2_txq_pcpu *txq_pcpu,
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txq_pcpu->buffs + txq_pcpu->txq_put_index;
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tx_buf->skb = skb;
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tx_buf->size = tx_desc->data_size;
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tx_buf->phys = tx_desc->buf_phys_addr + tx_desc->packet_offset;
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tx_buf->dma = tx_desc->buf_dma_addr + tx_desc->packet_offset;
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txq_pcpu->txq_put_index++;
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if (txq_pcpu->txq_put_index == txq_pcpu->size)
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txq_pcpu->txq_put_index = 0;
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@ -3383,7 +3383,7 @@ static int mvpp2_bm_pool_create(struct platform_device *pdev,
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size_bytes = sizeof(u32) * size;
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bm_pool->virt_addr = dma_alloc_coherent(&pdev->dev, size_bytes,
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&bm_pool->phys_addr,
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&bm_pool->dma_addr,
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GFP_KERNEL);
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if (!bm_pool->virt_addr)
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return -ENOMEM;
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@ -3391,14 +3391,14 @@ static int mvpp2_bm_pool_create(struct platform_device *pdev,
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if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
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MVPP2_BM_POOL_PTR_ALIGN)) {
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dma_free_coherent(&pdev->dev, size_bytes, bm_pool->virt_addr,
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bm_pool->phys_addr);
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bm_pool->dma_addr);
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dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n",
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bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
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return -ENOMEM;
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}
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mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
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bm_pool->phys_addr);
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bm_pool->dma_addr);
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mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
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val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
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@ -3433,15 +3433,15 @@ static void mvpp2_bm_bufs_free(struct device *dev, struct mvpp2 *priv,
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int i;
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for (i = 0; i < bm_pool->buf_num; i++) {
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dma_addr_t buf_phys_addr;
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dma_addr_t buf_dma_addr;
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unsigned long vaddr;
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/* Get buffer virtual address (indirect access) */
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buf_phys_addr = mvpp2_read(priv,
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MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
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buf_dma_addr = mvpp2_read(priv,
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MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
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vaddr = mvpp2_read(priv, MVPP2_BM_VIRT_ALLOC_REG);
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dma_unmap_single(dev, buf_phys_addr,
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dma_unmap_single(dev, buf_dma_addr,
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bm_pool->buf_size, DMA_FROM_DEVICE);
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if (!vaddr)
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@ -3473,7 +3473,7 @@ static int mvpp2_bm_pool_destroy(struct platform_device *pdev,
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dma_free_coherent(&pdev->dev, sizeof(u32) * bm_pool->size,
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bm_pool->virt_addr,
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bm_pool->phys_addr);
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bm_pool->dma_addr);
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return 0;
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}
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@ -3563,24 +3563,24 @@ static void mvpp2_rxq_short_pool_set(struct mvpp2_port *port,
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static void *mvpp2_buf_alloc(struct mvpp2_port *port,
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struct mvpp2_bm_pool *bm_pool,
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dma_addr_t *buf_phys_addr,
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dma_addr_t *buf_dma_addr,
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gfp_t gfp_mask)
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{
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dma_addr_t phys_addr;
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dma_addr_t dma_addr;
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void *data;
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data = mvpp2_frag_alloc(bm_pool);
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if (!data)
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return NULL;
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phys_addr = dma_map_single(port->dev->dev.parent, data,
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MVPP2_RX_BUF_SIZE(bm_pool->pkt_size),
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DMA_FROM_DEVICE);
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if (unlikely(dma_mapping_error(port->dev->dev.parent, phys_addr))) {
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dma_addr = dma_map_single(port->dev->dev.parent, data,
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MVPP2_RX_BUF_SIZE(bm_pool->pkt_size),
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DMA_FROM_DEVICE);
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if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) {
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mvpp2_frag_free(bm_pool, data);
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return NULL;
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}
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*buf_phys_addr = phys_addr;
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*buf_dma_addr = dma_addr;
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return data;
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}
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@ -3604,16 +3604,16 @@ static inline int mvpp2_bm_cookie_pool_get(unsigned long cookie)
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/* Release buffer to BM */
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static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
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dma_addr_t buf_phys_addr,
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dma_addr_t buf_dma_addr,
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unsigned long buf_virt_addr)
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{
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mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_virt_addr);
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mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_phys_addr);
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mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
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}
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/* Release multicast buffer */
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static void mvpp2_bm_pool_mc_put(struct mvpp2_port *port, int pool,
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dma_addr_t buf_phys_addr,
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dma_addr_t buf_dma_addr,
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unsigned long buf_virt_addr,
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int mc_id)
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{
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@ -3623,18 +3623,18 @@ static void mvpp2_bm_pool_mc_put(struct mvpp2_port *port, int pool,
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mvpp2_write(port->priv, MVPP2_BM_MC_RLS_REG, val);
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mvpp2_bm_pool_put(port, pool,
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buf_phys_addr | MVPP2_BM_PHY_RLS_MC_BUFF_MASK,
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buf_dma_addr | MVPP2_BM_PHY_RLS_MC_BUFF_MASK,
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buf_virt_addr);
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}
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/* Refill BM pool */
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static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm,
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dma_addr_t phys_addr,
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dma_addr_t dma_addr,
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unsigned long cookie)
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{
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int pool = mvpp2_bm_cookie_pool_get(bm);
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mvpp2_bm_pool_put(port, pool, phys_addr, cookie);
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mvpp2_bm_pool_put(port, pool, dma_addr, cookie);
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}
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/* Allocate buffers for the pool */
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@ -3642,7 +3642,7 @@ static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
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struct mvpp2_bm_pool *bm_pool, int buf_num)
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{
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int i, buf_size, total_size;
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dma_addr_t phys_addr;
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dma_addr_t dma_addr;
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void *buf;
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buf_size = MVPP2_RX_BUF_SIZE(bm_pool->pkt_size);
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@ -3657,11 +3657,11 @@ static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
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}
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for (i = 0; i < buf_num; i++) {
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buf = mvpp2_buf_alloc(port, bm_pool, &phys_addr, GFP_KERNEL);
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buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr, GFP_KERNEL);
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if (!buf)
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break;
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mvpp2_bm_pool_put(port, bm_pool->id, phys_addr,
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mvpp2_bm_pool_put(port, bm_pool->id, dma_addr,
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(unsigned long)buf);
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}
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@ -4449,7 +4449,7 @@ static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
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struct mvpp2_txq_pcpu_buf *tx_buf =
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txq_pcpu->buffs + txq_pcpu->txq_get_index;
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dma_unmap_single(port->dev->dev.parent, tx_buf->phys,
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dma_unmap_single(port->dev->dev.parent, tx_buf->dma,
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tx_buf->size, DMA_TO_DEVICE);
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if (tx_buf->skb)
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dev_kfree_skb_any(tx_buf->skb);
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@ -4530,7 +4530,7 @@ static int mvpp2_aggr_txq_init(struct platform_device *pdev,
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/* Allocate memory for TX descriptors */
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aggr_txq->descs = dma_alloc_coherent(&pdev->dev,
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desc_num * MVPP2_DESC_ALIGNED_SIZE,
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&aggr_txq->descs_phys, GFP_KERNEL);
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&aggr_txq->descs_dma, GFP_KERNEL);
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if (!aggr_txq->descs)
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return -ENOMEM;
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@ -4543,7 +4543,7 @@ static int mvpp2_aggr_txq_init(struct platform_device *pdev,
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/* Set Tx descriptors queue starting address */
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/* indirect access */
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mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu),
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aggr_txq->descs_phys);
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aggr_txq->descs_dma);
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mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), desc_num);
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return 0;
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@ -4559,7 +4559,7 @@ static int mvpp2_rxq_init(struct mvpp2_port *port,
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/* Allocate memory for RX descriptors */
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rxq->descs = dma_alloc_coherent(port->dev->dev.parent,
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rxq->size * MVPP2_DESC_ALIGNED_SIZE,
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&rxq->descs_phys, GFP_KERNEL);
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&rxq->descs_dma, GFP_KERNEL);
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if (!rxq->descs)
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return -ENOMEM;
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@ -4570,7 +4570,7 @@ static int mvpp2_rxq_init(struct mvpp2_port *port,
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/* Set Rx descriptors queue starting address - indirect access */
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mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
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mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq->descs_phys);
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mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq->descs_dma);
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mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
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mvpp2_write(port->priv, MVPP2_RXQ_INDEX_REG, 0);
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@ -4601,7 +4601,7 @@ static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
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struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
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u32 bm = mvpp2_bm_cookie_build(rx_desc);
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mvpp2_pool_refill(port, bm, rx_desc->buf_phys_addr,
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mvpp2_pool_refill(port, bm, rx_desc->buf_dma_addr,
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rx_desc->buf_cookie);
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}
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mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
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@ -4617,12 +4617,12 @@ static void mvpp2_rxq_deinit(struct mvpp2_port *port,
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dma_free_coherent(port->dev->dev.parent,
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rxq->size * MVPP2_DESC_ALIGNED_SIZE,
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rxq->descs,
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rxq->descs_phys);
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rxq->descs_dma);
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rxq->descs = NULL;
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rxq->last_desc = 0;
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rxq->next_desc_to_proc = 0;
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rxq->descs_phys = 0;
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rxq->descs_dma = 0;
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/* Clear Rx descriptors queue starting address and size;
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* free descriptor number
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@ -4646,7 +4646,7 @@ static int mvpp2_txq_init(struct mvpp2_port *port,
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/* Allocate memory for Tx descriptors */
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txq->descs = dma_alloc_coherent(port->dev->dev.parent,
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txq->size * MVPP2_DESC_ALIGNED_SIZE,
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&txq->descs_phys, GFP_KERNEL);
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&txq->descs_dma, GFP_KERNEL);
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if (!txq->descs)
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return -ENOMEM;
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@ -4654,7 +4654,7 @@ static int mvpp2_txq_init(struct mvpp2_port *port,
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/* Set Tx descriptors queue starting address - indirect access */
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mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
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mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, txq->descs_phys);
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mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, txq->descs_dma);
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mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, txq->size &
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MVPP2_TXQ_DESC_SIZE_MASK);
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mvpp2_write(port->priv, MVPP2_TXQ_INDEX_REG, 0);
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@ -4716,7 +4716,7 @@ static int mvpp2_txq_init(struct mvpp2_port *port,
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dma_free_coherent(port->dev->dev.parent,
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txq->size * MVPP2_DESC_ALIGNED_SIZE,
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txq->descs, txq->descs_phys);
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txq->descs, txq->descs_dma);
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return -ENOMEM;
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}
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@ -4736,12 +4736,12 @@ static void mvpp2_txq_deinit(struct mvpp2_port *port,
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if (txq->descs)
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dma_free_coherent(port->dev->dev.parent,
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txq->size * MVPP2_DESC_ALIGNED_SIZE,
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txq->descs, txq->descs_phys);
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txq->descs, txq->descs_dma);
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txq->descs = NULL;
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txq->last_desc = 0;
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txq->next_desc_to_proc = 0;
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txq->descs_phys = 0;
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txq->descs_dma = 0;
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/* Set minimum bandwidth for disabled TXQs */
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mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0);
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@ -5031,15 +5031,15 @@ static void mvpp2_rx_csum(struct mvpp2_port *port, u32 status,
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static int mvpp2_rx_refill(struct mvpp2_port *port,
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struct mvpp2_bm_pool *bm_pool, u32 bm)
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{
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dma_addr_t phys_addr;
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dma_addr_t dma_addr;
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void *buf;
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/* No recycle or too many buffers are in use, so allocate a new skb */
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buf = mvpp2_buf_alloc(port, bm_pool, &phys_addr, GFP_ATOMIC);
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buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr, GFP_ATOMIC);
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if (!buf)
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return -ENOMEM;
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mvpp2_pool_refill(port, bm, phys_addr, (unsigned long)buf);
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mvpp2_pool_refill(port, bm, dma_addr, (unsigned long)buf);
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return 0;
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}
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@ -5081,16 +5081,16 @@ static void mvpp2_buff_hdr_rx(struct mvpp2_port *port,
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struct mvpp2_buff_hdr *buff_hdr;
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struct sk_buff *skb;
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u32 rx_status = rx_desc->status;
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dma_addr_t buff_phys_addr;
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dma_addr_t buff_dma_addr;
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unsigned long buff_virt_addr;
|
||||
dma_addr_t buff_phys_addr_next;
|
||||
dma_addr_t buff_dma_addr_next;
|
||||
unsigned long buff_virt_addr_next;
|
||||
int mc_id;
|
||||
int pool_id;
|
||||
|
||||
pool_id = (rx_status & MVPP2_RXD_BM_POOL_ID_MASK) >>
|
||||
MVPP2_RXD_BM_POOL_ID_OFFS;
|
||||
buff_phys_addr = rx_desc->buf_phys_addr;
|
||||
buff_dma_addr = rx_desc->buf_dma_addr;
|
||||
buff_virt_addr = rx_desc->buf_cookie;
|
||||
|
||||
do {
|
||||
|
|
@ -5099,14 +5099,14 @@ static void mvpp2_buff_hdr_rx(struct mvpp2_port *port,
|
|||
|
||||
mc_id = MVPP2_B_HDR_INFO_MC_ID(buff_hdr->info);
|
||||
|
||||
buff_phys_addr_next = buff_hdr->next_buff_phys_addr;
|
||||
buff_dma_addr_next = buff_hdr->next_buff_dma_addr;
|
||||
buff_virt_addr_next = buff_hdr->next_buff_virt_addr;
|
||||
|
||||
/* Release buffer */
|
||||
mvpp2_bm_pool_mc_put(port, pool_id, buff_phys_addr,
|
||||
mvpp2_bm_pool_mc_put(port, pool_id, buff_dma_addr,
|
||||
buff_virt_addr, mc_id);
|
||||
|
||||
buff_phys_addr = buff_phys_addr_next;
|
||||
buff_dma_addr = buff_dma_addr_next;
|
||||
buff_virt_addr = buff_virt_addr_next;
|
||||
|
||||
} while (!MVPP2_B_HDR_INFO_IS_LAST(buff_hdr->info));
|
||||
|
|
@ -5132,7 +5132,7 @@ static int mvpp2_rx(struct mvpp2_port *port, int rx_todo,
|
|||
struct mvpp2_bm_pool *bm_pool;
|
||||
struct sk_buff *skb;
|
||||
unsigned int frag_size;
|
||||
dma_addr_t phys_addr;
|
||||
dma_addr_t dma_addr;
|
||||
u32 bm, rx_status;
|
||||
int pool, rx_bytes, err;
|
||||
void *data;
|
||||
|
|
@ -5140,7 +5140,7 @@ static int mvpp2_rx(struct mvpp2_port *port, int rx_todo,
|
|||
rx_done++;
|
||||
rx_status = rx_desc->status;
|
||||
rx_bytes = rx_desc->data_size - MVPP2_MH_SIZE;
|
||||
phys_addr = rx_desc->buf_phys_addr;
|
||||
dma_addr = rx_desc->buf_dma_addr;
|
||||
data = (void *)(uintptr_t)rx_desc->buf_cookie;
|
||||
|
||||
bm = mvpp2_bm_cookie_build(rx_desc);
|
||||
|
|
@ -5163,7 +5163,7 @@ static int mvpp2_rx(struct mvpp2_port *port, int rx_todo,
|
|||
mvpp2_rx_error(port, rx_desc);
|
||||
/* Return the buffer to the pool */
|
||||
|
||||
mvpp2_pool_refill(port, bm, rx_desc->buf_phys_addr,
|
||||
mvpp2_pool_refill(port, bm, rx_desc->buf_dma_addr,
|
||||
rx_desc->buf_cookie);
|
||||
continue;
|
||||
}
|
||||
|
|
@ -5185,7 +5185,7 @@ static int mvpp2_rx(struct mvpp2_port *port, int rx_todo,
|
|||
goto err_drop_frame;
|
||||
}
|
||||
|
||||
dma_unmap_single(dev->dev.parent, phys_addr,
|
||||
dma_unmap_single(dev->dev.parent, dma_addr,
|
||||
bm_pool->buf_size, DMA_FROM_DEVICE);
|
||||
|
||||
rcvd_pkts++;
|
||||
|
|
@ -5219,7 +5219,7 @@ static inline void
|
|||
tx_desc_unmap_put(struct device *dev, struct mvpp2_tx_queue *txq,
|
||||
struct mvpp2_tx_desc *desc)
|
||||
{
|
||||
dma_unmap_single(dev, desc->buf_phys_addr,
|
||||
dma_unmap_single(dev, desc->buf_dma_addr,
|
||||
desc->data_size, DMA_TO_DEVICE);
|
||||
mvpp2_txq_desc_put(txq);
|
||||
}
|
||||
|
|
@ -5232,7 +5232,7 @@ static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb,
|
|||
struct mvpp2_txq_pcpu *txq_pcpu = this_cpu_ptr(txq->pcpu);
|
||||
struct mvpp2_tx_desc *tx_desc;
|
||||
int i;
|
||||
dma_addr_t buf_phys_addr;
|
||||
dma_addr_t buf_dma_addr;
|
||||
|
||||
for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
|
||||
skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
|
||||
|
|
@ -5242,16 +5242,16 @@ static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb,
|
|||
tx_desc->phys_txq = txq->id;
|
||||
tx_desc->data_size = frag->size;
|
||||
|
||||
buf_phys_addr = dma_map_single(port->dev->dev.parent, addr,
|
||||
tx_desc->data_size,
|
||||
DMA_TO_DEVICE);
|
||||
if (dma_mapping_error(port->dev->dev.parent, buf_phys_addr)) {
|
||||
buf_dma_addr = dma_map_single(port->dev->dev.parent, addr,
|
||||
tx_desc->data_size,
|
||||
DMA_TO_DEVICE);
|
||||
if (dma_mapping_error(port->dev->dev.parent, buf_dma_addr)) {
|
||||
mvpp2_txq_desc_put(txq);
|
||||
goto error;
|
||||
}
|
||||
|
||||
tx_desc->packet_offset = buf_phys_addr & MVPP2_TX_DESC_ALIGN;
|
||||
tx_desc->buf_phys_addr = buf_phys_addr & (~MVPP2_TX_DESC_ALIGN);
|
||||
tx_desc->packet_offset = buf_dma_addr & MVPP2_TX_DESC_ALIGN;
|
||||
tx_desc->buf_dma_addr = buf_dma_addr & (~MVPP2_TX_DESC_ALIGN);
|
||||
|
||||
if (i == (skb_shinfo(skb)->nr_frags - 1)) {
|
||||
/* Last descriptor */
|
||||
|
|
@ -5285,7 +5285,7 @@ static int mvpp2_tx(struct sk_buff *skb, struct net_device *dev)
|
|||
struct mvpp2_tx_queue *txq, *aggr_txq;
|
||||
struct mvpp2_txq_pcpu *txq_pcpu;
|
||||
struct mvpp2_tx_desc *tx_desc;
|
||||
dma_addr_t buf_phys_addr;
|
||||
dma_addr_t buf_dma_addr;
|
||||
int frags = 0;
|
||||
u16 txq_id;
|
||||
u32 tx_cmd;
|
||||
|
|
@ -5310,15 +5310,15 @@ static int mvpp2_tx(struct sk_buff *skb, struct net_device *dev)
|
|||
tx_desc->phys_txq = txq->id;
|
||||
tx_desc->data_size = skb_headlen(skb);
|
||||
|
||||
buf_phys_addr = dma_map_single(dev->dev.parent, skb->data,
|
||||
tx_desc->data_size, DMA_TO_DEVICE);
|
||||
if (unlikely(dma_mapping_error(dev->dev.parent, buf_phys_addr))) {
|
||||
buf_dma_addr = dma_map_single(dev->dev.parent, skb->data,
|
||||
tx_desc->data_size, DMA_TO_DEVICE);
|
||||
if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) {
|
||||
mvpp2_txq_desc_put(txq);
|
||||
frags = 0;
|
||||
goto out;
|
||||
}
|
||||
tx_desc->packet_offset = buf_phys_addr & MVPP2_TX_DESC_ALIGN;
|
||||
tx_desc->buf_phys_addr = buf_phys_addr & ~MVPP2_TX_DESC_ALIGN;
|
||||
tx_desc->packet_offset = buf_dma_addr & MVPP2_TX_DESC_ALIGN;
|
||||
tx_desc->buf_dma_addr = buf_dma_addr & ~MVPP2_TX_DESC_ALIGN;
|
||||
|
||||
tx_cmd = mvpp2_skb_tx_csum(port, skb);
|
||||
|
||||
|
|
@ -6506,7 +6506,7 @@ static int mvpp2_remove(struct platform_device *pdev)
|
|||
dma_free_coherent(&pdev->dev,
|
||||
MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE,
|
||||
aggr_txq->descs,
|
||||
aggr_txq->descs_phys);
|
||||
aggr_txq->descs_dma);
|
||||
}
|
||||
|
||||
clk_disable_unprepare(priv->pp_clk);
|
||||
|
|
|
|||
Loading…
Reference in New Issue