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iommu/io-pgtable-arm: Rationalise MAIR handling 

Between VMSAv8-64 and the various 32-bit formats, there is either one
64-bit MAIR or a pair of 32-bit MAIR0/MAIR1 or NMRR/PMRR registers.
As such, keeping two 64-bit values in io_pgtable_cfg has always been
overkill.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
This commit is contained in:
Robin Murphy 2019-10-25 19:08:36 +01:00 committed by Will Deacon
parent 5fb190b0b5
commit 205577ab6f
6 changed files with 8 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/iommu/arm-smmu-v3.c
View File

@ -2172,7 +2172,7 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain,
cfg->cd.asid = (u16)asid; cfg->cd.asid = (u16)asid;
cfg->cd.ttbr = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0]; cfg->cd.ttbr = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0];
cfg->cd.tcr = pgtbl_cfg->arm_lpae_s1_cfg.tcr; cfg->cd.tcr = pgtbl_cfg->arm_lpae_s1_cfg.tcr;
cfg->cd.mair = pgtbl_cfg->arm_lpae_s1_cfg.mair[0]; cfg->cd.mair = pgtbl_cfg->arm_lpae_s1_cfg.mair;
return 0; return 0;
out_free_asid: out_free_asid:

4
drivers/iommu/arm-smmu.c
View File

@ -552,8 +552,8 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
cb->mair[0] = pgtbl_cfg->arm_v7s_cfg.prrr; cb->mair[0] = pgtbl_cfg->arm_v7s_cfg.prrr;
cb->mair[1] = pgtbl_cfg->arm_v7s_cfg.nmrr; cb->mair[1] = pgtbl_cfg->arm_v7s_cfg.nmrr;
} else { } else {
cb->mair[0] = pgtbl_cfg->arm_lpae_s1_cfg.mair[0]; cb->mair[0] = pgtbl_cfg->arm_lpae_s1_cfg.mair;
cb->mair[1] = pgtbl_cfg->arm_lpae_s1_cfg.mair[1]; cb->mair[1] = pgtbl_cfg->arm_lpae_s1_cfg.mair >> 32;
} }
} }
} }

3
drivers/iommu/io-pgtable-arm.c
View File

@ -861,8 +861,7 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)
(ARM_LPAE_MAIR_ATTR_INC_OWBRWA (ARM_LPAE_MAIR_ATTR_INC_OWBRWA
<< ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE)); << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE));
cfg->arm_lpae_s1_cfg.mair[0] = reg; cfg->arm_lpae_s1_cfg.mair = reg;
cfg->arm_lpae_s1_cfg.mair[1] = 0;
/* Looking good; allocate a pgd */ /* Looking good; allocate a pgd */
data->pgd = __arm_lpae_alloc_pages(ARM_LPAE_PGD_SIZE(data), data->pgd = __arm_lpae_alloc_pages(ARM_LPAE_PGD_SIZE(data),

2
drivers/iommu/ipmmu-vmsa.c
View File

@ -438,7 +438,7 @@ static void ipmmu_domain_setup_context(struct ipmmu_vmsa_domain *domain)
/* MAIR0 */ /* MAIR0 */
ipmmu_ctx_write_root(domain, IMMAIR0, ipmmu_ctx_write_root(domain, IMMAIR0,
domain->cfg.arm_lpae_s1_cfg.mair[0]); domain->cfg.arm_lpae_s1_cfg.mair);
/* IMBUSCR */ /* IMBUSCR */
if (domain->mmu->features->setup_imbuscr) if (domain->mmu->features->setup_imbuscr)

4
drivers/iommu/qcom_iommu.c
View File

@ -284,9 +284,9 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain,
/* MAIRs (stage-1 only) */ /* MAIRs (stage-1 only) */
iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR0, iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR0,
pgtbl_cfg.arm_lpae_s1_cfg.mair[0]); pgtbl_cfg.arm_lpae_s1_cfg.mair);
iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR1, iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR1,
pgtbl_cfg.arm_lpae_s1_cfg.mair[1]); pgtbl_cfg.arm_lpae_s1_cfg.mair >> 32);
/* SCTLR */ /* SCTLR */
reg = SCTLR_CFIE | SCTLR_CFRE | SCTLR_AFE | SCTLR_TRE | reg = SCTLR_CFIE | SCTLR_CFRE | SCTLR_AFE | SCTLR_TRE |

2
include/linux/io-pgtable.h
View File

@ -102,7 +102,7 @@ struct io_pgtable_cfg {
struct { struct {
u64 ttbr[2]; u64 ttbr[2];
u64 tcr; u64 tcr;
u64 mair[2]; u64 mair;
} arm_lpae_s1_cfg; } arm_lpae_s1_cfg;
struct { struct {