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Alpine DT changes for 4.12 

A bunch of clean up for Alpine device trees, nothing fancy.
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Merge tag 'alpine-dt-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/atenart/linux into next/dt

Alpine DT changes for 4.12

A bunch of clean up for Alpine device trees, nothing fancy.

* tag 'alpine-dt-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/atenart/linux:
  ARM: dts: alpine: add valid clock-frequency values
  ARM: dts: alpine: add spaces before the uart node units.
  ARM: dts: alpine: remove 0x's from the uart1 node unit address
  ARM: dts: alpine: fix PCIe node name

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2017-04-19 06:50:30 -07:00
parent d6d9ac9e48 ffdc394e1b
commit 214b8b8e0e
1 changed files with 10 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
arch/arm/boot/dts/alpine.dtsi
View File

@ -41,28 +41,28 @@ cpu@0 {
compatible = "arm,cortex-a15"; compatible = "arm,cortex-a15";
device_type = "cpu"; device_type = "cpu";
reg = <0>; reg = <0>;
clock-frequency = <0>; /* Filled by loader */ clock-frequency = <1700000000>;
}; };
cpu@1 { cpu@1 {
compatible = "arm,cortex-a15"; compatible = "arm,cortex-a15";
device_type = "cpu"; device_type = "cpu";
reg = <1>; reg = <1>;
clock-frequency = <0>; /* Filled by loader */ clock-frequency = <1700000000>;
}; };
cpu@2 { cpu@2 {
compatible = "arm,cortex-a15"; compatible = "arm,cortex-a15";
device_type = "cpu"; device_type = "cpu";
reg = <2>; reg = <2>;
clock-frequency = <0>; /* Filled by loader */ clock-frequency = <1700000000>;
}; };
cpu@3 { cpu@3 {
compatible = "arm,cortex-a15"; compatible = "arm,cortex-a15";
device_type = "cpu"; device_type = "cpu";
reg = <3>; reg = <3>;
clock-frequency = <0>; /* Filled by loader */ clock-frequency = <1700000000>;
}; };
}; };
@ -81,7 +81,7 @@ arch-timer {
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <0>; /* Filled by loader */ clock-frequency = <50000000>;
}; };
/* Interrupt Controller */ /* Interrupt Controller */
@ -123,23 +123,23 @@ pmu {
uart0: uart@fd883000 { uart0: uart@fd883000 {
compatible = "ns16550a"; compatible = "ns16550a";
reg = <0x0 0xfd883000 0x0 0x1000>; reg = <0x0 0xfd883000 0x0 0x1000>;
clock-frequency = <0>; /* Filled by loader */ clock-frequency = <375000000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
}; };
uart1:uart@0xfd884000 { uart1: uart@fd884000 {
compatible = "ns16550a"; compatible = "ns16550a";
reg = <0x0 0xfd884000 0x0 0x1000>; reg = <0x0 0xfd884000 0x0 0x1000>;
clock-frequency = <0>; /* Filled by loader */ clock-frequency = <375000000>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
}; };
/* Internal PCIe Controller */ /* Internal PCIe Controller */
pcie-internal@0xfbc00000 { pcie@fbc00000 {
compatible = "pci-host-ecam-generic"; compatible = "pci-host-ecam-generic";
device_type = "pci"; device_type = "pci";
#size-cells = <2>; #size-cells = <2>;