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arm64: 36 bit VA
36bit VA lets us use 2 level page tables while limiting the available address space to 64GB. Cc: Will Deacon <will.deacon@arm.com> Cc: Steve Capper <steve.capper@linaro.org> Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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@ -170,6 +170,7 @@ config FIX_EARLYCON_MEM
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config PGTABLE_LEVELS
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config PGTABLE_LEVELS
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int
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int
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default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
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default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
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default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
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default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
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default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
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default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
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default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
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@ -391,6 +392,10 @@ choice
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space sizes. The level of translation table is determined by
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space sizes. The level of translation table is determined by
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a combination of page size and virtual address space size.
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a combination of page size and virtual address space size.
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config ARM64_VA_BITS_36
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bool "36-bit"
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depends on ARM64_16K_PAGES
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config ARM64_VA_BITS_39
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config ARM64_VA_BITS_39
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bool "39-bit"
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bool "39-bit"
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depends on ARM64_4K_PAGES
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depends on ARM64_4K_PAGES
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@ -410,6 +415,7 @@ endchoice
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config ARM64_VA_BITS
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config ARM64_VA_BITS
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int
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int
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default 36 if ARM64_VA_BITS_36
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default 39 if ARM64_VA_BITS_39
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default 39 if ARM64_VA_BITS_39
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default 42 if ARM64_VA_BITS_42
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default 42 if ARM64_VA_BITS_42
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default 47 if ARM64_VA_BITS_47
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default 47 if ARM64_VA_BITS_47
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@ -480,7 +486,7 @@ config ARCH_WANT_GENERAL_HUGETLB
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def_bool y
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def_bool y
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config ARCH_WANT_HUGE_PMD_SHARE
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config ARCH_WANT_HUGE_PMD_SHARE
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def_bool y if ARM64_4K_PAGES || ARM64_16K_PAGES
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def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
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config HAVE_ARCH_TRANSPARENT_HUGEPAGE
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config HAVE_ARCH_TRANSPARENT_HUGEPAGE
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def_bool y
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def_bool y
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