mirror of https://gitee.com/openkylin/linux.git
mtd: nand: pxa3xx-nand: fix random command timeouts
When 2 commands are submitted in a row, and the second is very quick, the completion of the second command might never come. This happens especially if the second command is quick, such as a status read after an erase. The issue is that in the interrupt handler, the status bits are cleared after the new command is issued. There is a small temporal window where this happens : - the previous command has set the command done bit - the ready for a command bit is set - the handler submits the next command - just then, the command completes, and the command done bit is still set - the handler clears the "previous" command done bit - the handler exits In this flow, the "command done" of the next command will never trigger a new interrupt to finish the status command, as it was cleared for both commands. Fix this by clearing the status bit before submitting a new command. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Tested-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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@ -678,8 +678,14 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
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is_ready = 1;
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}
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/*
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* Clear all status bit before issuing the next command, which
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* can and will alter the status bits and will deserve a new
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* interrupt on its own. This lets the controller exit the IRQ
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*/
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nand_writel(info, NDSR, status);
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if (status & NDSR_WRCMDREQ) {
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nand_writel(info, NDSR, NDSR_WRCMDREQ);
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status &= ~NDSR_WRCMDREQ;
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info->state = STATE_CMD_HANDLE;
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@ -700,8 +706,6 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
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nand_writel(info, NDCB0, info->ndcb3);
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}
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/* clear NDSR to let the controller exit the IRQ */
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nand_writel(info, NDSR, status);
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if (is_completed)
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complete(&info->cmd_complete);
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if (is_ready)
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