mirror of https://gitee.com/openkylin/linux.git
Merge branch 'for-3.11/deps-for-clk' into for-3.11/dt
This commit is contained in:
Stephen Warren
commit
220cf5fb5c
|
|
@ -12,253 +12,9 @@ Required properties :
|
|||
- clocks : Should contain phandle and clock specifiers for two clocks:
|
||||
the 32 KHz "32k_in", and the board-specific oscillator "osc".
|
||||
- #clock-cells : Should be 1.
|
||||
In clock consumers, this cell represents the clock ID exposed by the CAR.
|
||||
|
||||
The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
|
||||
registers. These IDs often match those in the CAR's RST_DEVICES registers,
|
||||
but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
|
||||
this case, those clocks are assigned IDs above 160 in order to highlight
|
||||
this issue. Implementations that interpret these clock IDs as bit values
|
||||
within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
|
||||
explicitly handle these special cases.
|
||||
|
||||
The balance of the clocks controlled by the CAR are assigned IDs of 160 and
|
||||
above.
|
||||
|
||||
0 unassigned
|
||||
1 unassigned
|
||||
2 unassigned
|
||||
3 unassigned
|
||||
4 rtc
|
||||
5 timer
|
||||
6 uarta
|
||||
7 unassigned (register bit affects uartb and vfir)
|
||||
8 unassigned
|
||||
9 sdmmc2
|
||||
10 unassigned (register bit affects spdif_in and spdif_out)
|
||||
11 i2s1
|
||||
12 i2c1
|
||||
13 ndflash
|
||||
14 sdmmc1
|
||||
15 sdmmc4
|
||||
16 unassigned
|
||||
17 pwm
|
||||
18 i2s2
|
||||
19 epp
|
||||
20 unassigned (register bit affects vi and vi_sensor)
|
||||
21 2d
|
||||
22 usbd
|
||||
23 isp
|
||||
24 3d
|
||||
25 unassigned
|
||||
26 disp2
|
||||
27 disp1
|
||||
28 host1x
|
||||
29 vcp
|
||||
30 i2s0
|
||||
31 unassigned
|
||||
|
||||
32 unassigned
|
||||
33 unassigned
|
||||
34 apbdma
|
||||
35 unassigned
|
||||
36 kbc
|
||||
37 unassigned
|
||||
38 unassigned
|
||||
39 unassigned (register bit affects fuse and fuse_burn)
|
||||
40 kfuse
|
||||
41 sbc1
|
||||
42 nor
|
||||
43 unassigned
|
||||
44 sbc2
|
||||
45 unassigned
|
||||
46 sbc3
|
||||
47 i2c5
|
||||
48 dsia
|
||||
49 unassigned
|
||||
50 mipi
|
||||
51 hdmi
|
||||
52 csi
|
||||
53 unassigned
|
||||
54 i2c2
|
||||
55 uartc
|
||||
56 mipi-cal
|
||||
57 emc
|
||||
58 usb2
|
||||
59 usb3
|
||||
60 msenc
|
||||
61 vde
|
||||
62 bsea
|
||||
63 bsev
|
||||
|
||||
64 unassigned
|
||||
65 uartd
|
||||
66 unassigned
|
||||
67 i2c3
|
||||
68 sbc4
|
||||
69 sdmmc3
|
||||
70 unassigned
|
||||
71 owr
|
||||
72 afi
|
||||
73 csite
|
||||
74 unassigned
|
||||
75 unassigned
|
||||
76 la
|
||||
77 trace
|
||||
78 soc_therm
|
||||
79 dtv
|
||||
80 ndspeed
|
||||
81 i2cslow
|
||||
82 dsib
|
||||
83 tsec
|
||||
84 unassigned
|
||||
85 unassigned
|
||||
86 unassigned
|
||||
87 unassigned
|
||||
88 unassigned
|
||||
89 xusb_host
|
||||
90 unassigned
|
||||
91 msenc
|
||||
92 csus
|
||||
93 unassigned
|
||||
94 unassigned
|
||||
95 unassigned (bit affects xusb_dev and xusb_dev_src)
|
||||
|
||||
96 unassigned
|
||||
97 unassigned
|
||||
98 unassigned
|
||||
99 mselect
|
||||
100 tsensor
|
||||
101 i2s3
|
||||
102 i2s4
|
||||
103 i2c4
|
||||
104 sbc5
|
||||
105 sbc6
|
||||
106 d_audio
|
||||
107 apbif
|
||||
108 dam0
|
||||
109 dam1
|
||||
110 dam2
|
||||
111 hda2codec_2x
|
||||
112 unassigned
|
||||
113 audio0_2x
|
||||
114 audio1_2x
|
||||
115 audio2_2x
|
||||
116 audio3_2x
|
||||
117 audio4_2x
|
||||
118 spdif_2x
|
||||
119 actmon
|
||||
120 extern1
|
||||
121 extern2
|
||||
122 extern3
|
||||
123 unassigned
|
||||
124 unassigned
|
||||
125 hda
|
||||
126 unassigned
|
||||
127 se
|
||||
|
||||
128 hda2hdmi
|
||||
129 unassigned
|
||||
130 unassigned
|
||||
131 unassigned
|
||||
132 unassigned
|
||||
133 unassigned
|
||||
134 unassigned
|
||||
135 unassigned
|
||||
136 unassigned
|
||||
137 unassigned
|
||||
138 unassigned
|
||||
139 unassigned
|
||||
140 unassigned
|
||||
141 unassigned
|
||||
142 unassigned
|
||||
143 unassigned (bit affects xusb_falcon_src, xusb_fs_src,
|
||||
xusb_host_src and xusb_ss_src)
|
||||
144 cilab
|
||||
145 cilcd
|
||||
146 cile
|
||||
147 dsialp
|
||||
148 dsiblp
|
||||
149 unassigned
|
||||
150 dds
|
||||
151 unassigned
|
||||
152 dp2
|
||||
153 amx
|
||||
154 adx
|
||||
155 unassigned (bit affects dfll_ref and dfll_soc)
|
||||
156 xusb_ss
|
||||
|
||||
192 uartb
|
||||
193 vfir
|
||||
194 spdif_in
|
||||
195 spdif_out
|
||||
196 vi
|
||||
197 vi_sensor
|
||||
198 fuse
|
||||
199 fuse_burn
|
||||
200 clk_32k
|
||||
201 clk_m
|
||||
202 clk_m_div2
|
||||
203 clk_m_div4
|
||||
204 pll_ref
|
||||
205 pll_c
|
||||
206 pll_c_out1
|
||||
207 pll_c2
|
||||
208 pll_c3
|
||||
209 pll_m
|
||||
210 pll_m_out1
|
||||
211 pll_p
|
||||
212 pll_p_out1
|
||||
213 pll_p_out2
|
||||
214 pll_p_out3
|
||||
215 pll_p_out4
|
||||
216 pll_a
|
||||
217 pll_a_out0
|
||||
218 pll_d
|
||||
219 pll_d_out0
|
||||
220 pll_d2
|
||||
221 pll_d2_out0
|
||||
222 pll_u
|
||||
223 pll_u_480M
|
||||
224 pll_u_60M
|
||||
225 pll_u_48M
|
||||
226 pll_u_12M
|
||||
227 pll_x
|
||||
228 pll_x_out0
|
||||
229 pll_re_vco
|
||||
230 pll_re_out
|
||||
231 pll_e_out0
|
||||
232 spdif_in_sync
|
||||
233 i2s0_sync
|
||||
234 i2s1_sync
|
||||
235 i2s2_sync
|
||||
236 i2s3_sync
|
||||
237 i2s4_sync
|
||||
238 vimclk_sync
|
||||
239 audio0
|
||||
240 audio1
|
||||
241 audio2
|
||||
242 audio3
|
||||
243 audio4
|
||||
244 spdif
|
||||
245 clk_out_1
|
||||
246 clk_out_2
|
||||
247 clk_out_3
|
||||
248 blink
|
||||
252 xusb_host_src
|
||||
253 xusb_falcon_src
|
||||
254 xusb_fs_src
|
||||
255 xusb_ss_src
|
||||
256 xusb_dev_src
|
||||
257 xusb_dev
|
||||
258 xusb_hs_src
|
||||
259 sclk
|
||||
260 hclk
|
||||
261 pclk
|
||||
262 cclk_g
|
||||
263 cclk_lp
|
||||
264 dfll_ref
|
||||
265 dfll_soc
|
||||
In clock consumers, this cell represents the clock ID exposed by the
|
||||
CAR. The assignments may be found in header file
|
||||
<dt-bindings/clock/tegra114-car.h>.
|
||||
|
||||
Example SoC include file:
|
||||
|
||||
|
|
@ -270,7 +26,7 @@ Example SoC include file:
|
|||
};
|
||||
|
||||
usb@c5004000 {
|
||||
clocks = <&tegra_car 58>; /* usb2 */
|
||||
clocks = <&tegra_car TEGRA114_CLK_USB2>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -12,155 +12,9 @@ Required properties :
|
|||
- clocks : Should contain phandle and clock specifiers for two clocks:
|
||||
the 32 KHz "32k_in", and the board-specific oscillator "osc".
|
||||
- #clock-cells : Should be 1.
|
||||
In clock consumers, this cell represents the clock ID exposed by the CAR.
|
||||
|
||||
The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
|
||||
registers. These IDs often match those in the CAR's RST_DEVICES registers,
|
||||
but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
|
||||
this case, those clocks are assigned IDs above 95 in order to highlight
|
||||
this issue. Implementations that interpret these clock IDs as bit values
|
||||
within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
|
||||
explicitly handle these special cases.
|
||||
|
||||
The balance of the clocks controlled by the CAR are assigned IDs of 96 and
|
||||
above.
|
||||
|
||||
0 cpu
|
||||
1 unassigned
|
||||
2 unassigned
|
||||
3 ac97
|
||||
4 rtc
|
||||
5 tmr
|
||||
6 uart1
|
||||
7 unassigned (register bit affects uart2 and vfir)
|
||||
8 gpio
|
||||
9 sdmmc2
|
||||
10 unassigned (register bit affects spdif_in and spdif_out)
|
||||
11 i2s1
|
||||
12 i2c1
|
||||
13 ndflash
|
||||
14 sdmmc1
|
||||
15 sdmmc4
|
||||
16 twc
|
||||
17 pwm
|
||||
18 i2s2
|
||||
19 epp
|
||||
20 unassigned (register bit affects vi and vi_sensor)
|
||||
21 2d
|
||||
22 usbd
|
||||
23 isp
|
||||
24 3d
|
||||
25 ide
|
||||
26 disp2
|
||||
27 disp1
|
||||
28 host1x
|
||||
29 vcp
|
||||
30 unassigned
|
||||
31 cache2
|
||||
|
||||
32 mem
|
||||
33 ahbdma
|
||||
34 apbdma
|
||||
35 unassigned
|
||||
36 kbc
|
||||
37 stat_mon
|
||||
38 pmc
|
||||
39 fuse
|
||||
40 kfuse
|
||||
41 sbc1
|
||||
42 snor
|
||||
43 spi1
|
||||
44 sbc2
|
||||
45 xio
|
||||
46 sbc3
|
||||
47 dvc
|
||||
48 dsi
|
||||
49 unassigned (register bit affects tvo and cve)
|
||||
50 mipi
|
||||
51 hdmi
|
||||
52 csi
|
||||
53 tvdac
|
||||
54 i2c2
|
||||
55 uart3
|
||||
56 unassigned
|
||||
57 emc
|
||||
58 usb2
|
||||
59 usb3
|
||||
60 mpe
|
||||
61 vde
|
||||
62 bsea
|
||||
63 bsev
|
||||
|
||||
64 speedo
|
||||
65 uart4
|
||||
66 uart5
|
||||
67 i2c3
|
||||
68 sbc4
|
||||
69 sdmmc3
|
||||
70 pcie
|
||||
71 owr
|
||||
72 afi
|
||||
73 csite
|
||||
74 unassigned
|
||||
75 avpucq
|
||||
76 la
|
||||
77 unassigned
|
||||
78 unassigned
|
||||
79 unassigned
|
||||
80 unassigned
|
||||
81 unassigned
|
||||
82 unassigned
|
||||
83 unassigned
|
||||
84 irama
|
||||
85 iramb
|
||||
86 iramc
|
||||
87 iramd
|
||||
88 cram2
|
||||
89 audio_2x a/k/a audio_2x_sync_clk
|
||||
90 clk_d
|
||||
91 unassigned
|
||||
92 sus
|
||||
93 cdev2
|
||||
94 cdev1
|
||||
95 unassigned
|
||||
|
||||
96 uart2
|
||||
97 vfir
|
||||
98 spdif_in
|
||||
99 spdif_out
|
||||
100 vi
|
||||
101 vi_sensor
|
||||
102 tvo
|
||||
103 cve
|
||||
104 osc
|
||||
105 clk_32k a/k/a clk_s
|
||||
106 clk_m
|
||||
107 sclk
|
||||
108 cclk
|
||||
109 hclk
|
||||
110 pclk
|
||||
111 blink
|
||||
112 pll_a
|
||||
113 pll_a_out0
|
||||
114 pll_c
|
||||
115 pll_c_out1
|
||||
116 pll_d
|
||||
117 pll_d_out0
|
||||
118 pll_e
|
||||
119 pll_m
|
||||
120 pll_m_out1
|
||||
121 pll_p
|
||||
122 pll_p_out1
|
||||
123 pll_p_out2
|
||||
124 pll_p_out3
|
||||
125 pll_p_out4
|
||||
126 pll_s
|
||||
127 pll_u
|
||||
128 pll_x
|
||||
129 cop a/k/a avp
|
||||
130 audio a/k/a audio_sync_clk
|
||||
131 pll_ref
|
||||
132 twd
|
||||
In clock consumers, this cell represents the clock ID exposed by the
|
||||
CAR. The assignments may be found in header file
|
||||
<dt-bindings/clock/tegra20-car.h>.
|
||||
|
||||
Example SoC include file:
|
||||
|
||||
|
|
@ -172,7 +26,7 @@ Example SoC include file:
|
|||
};
|
||||
|
||||
usb@c5004000 {
|
||||
clocks = <&tegra_car 58>; /* usb2 */
|
||||
clocks = <&tegra_car TEGRA20_CLK_USB2>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -12,212 +12,9 @@ Required properties :
|
|||
- clocks : Should contain phandle and clock specifiers for two clocks:
|
||||
the 32 KHz "32k_in", and the board-specific oscillator "osc".
|
||||
- #clock-cells : Should be 1.
|
||||
In clock consumers, this cell represents the clock ID exposed by the CAR.
|
||||
|
||||
The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
|
||||
registers. These IDs often match those in the CAR's RST_DEVICES registers,
|
||||
but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
|
||||
this case, those clocks are assigned IDs above 160 in order to highlight
|
||||
this issue. Implementations that interpret these clock IDs as bit values
|
||||
within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
|
||||
explicitly handle these special cases.
|
||||
|
||||
The balance of the clocks controlled by the CAR are assigned IDs of 160 and
|
||||
above.
|
||||
|
||||
0 cpu
|
||||
1 unassigned
|
||||
2 unassigned
|
||||
3 unassigned
|
||||
4 rtc
|
||||
5 timer
|
||||
6 uarta
|
||||
7 unassigned (register bit affects uartb and vfir)
|
||||
8 gpio
|
||||
9 sdmmc2
|
||||
10 unassigned (register bit affects spdif_in and spdif_out)
|
||||
11 i2s1
|
||||
12 i2c1
|
||||
13 ndflash
|
||||
14 sdmmc1
|
||||
15 sdmmc4
|
||||
16 unassigned
|
||||
17 pwm
|
||||
18 i2s2
|
||||
19 epp
|
||||
20 unassigned (register bit affects vi and vi_sensor)
|
||||
21 2d
|
||||
22 usbd
|
||||
23 isp
|
||||
24 3d
|
||||
25 unassigned
|
||||
26 disp2
|
||||
27 disp1
|
||||
28 host1x
|
||||
29 vcp
|
||||
30 i2s0
|
||||
31 cop_cache
|
||||
|
||||
32 mc
|
||||
33 ahbdma
|
||||
34 apbdma
|
||||
35 unassigned
|
||||
36 kbc
|
||||
37 statmon
|
||||
38 pmc
|
||||
39 unassigned (register bit affects fuse and fuse_burn)
|
||||
40 kfuse
|
||||
41 sbc1
|
||||
42 nor
|
||||
43 unassigned
|
||||
44 sbc2
|
||||
45 unassigned
|
||||
46 sbc3
|
||||
47 i2c5
|
||||
48 dsia
|
||||
49 unassigned (register bit affects cve and tvo)
|
||||
50 mipi
|
||||
51 hdmi
|
||||
52 csi
|
||||
53 tvdac
|
||||
54 i2c2
|
||||
55 uartc
|
||||
56 unassigned
|
||||
57 emc
|
||||
58 usb2
|
||||
59 usb3
|
||||
60 mpe
|
||||
61 vde
|
||||
62 bsea
|
||||
63 bsev
|
||||
|
||||
64 speedo
|
||||
65 uartd
|
||||
66 uarte
|
||||
67 i2c3
|
||||
68 sbc4
|
||||
69 sdmmc3
|
||||
70 pcie
|
||||
71 owr
|
||||
72 afi
|
||||
73 csite
|
||||
74 pciex
|
||||
75 avpucq
|
||||
76 la
|
||||
77 unassigned
|
||||
78 unassigned
|
||||
79 dtv
|
||||
80 ndspeed
|
||||
81 i2cslow
|
||||
82 dsib
|
||||
83 unassigned
|
||||
84 irama
|
||||
85 iramb
|
||||
86 iramc
|
||||
87 iramd
|
||||
88 cram2
|
||||
89 unassigned
|
||||
90 audio_2x a/k/a audio_2x_sync_clk
|
||||
91 unassigned
|
||||
92 csus
|
||||
93 cdev2
|
||||
94 cdev1
|
||||
95 unassigned
|
||||
|
||||
96 cpu_g
|
||||
97 cpu_lp
|
||||
98 3d2
|
||||
99 mselect
|
||||
100 tsensor
|
||||
101 i2s3
|
||||
102 i2s4
|
||||
103 i2c4
|
||||
104 sbc5
|
||||
105 sbc6
|
||||
106 d_audio
|
||||
107 apbif
|
||||
108 dam0
|
||||
109 dam1
|
||||
110 dam2
|
||||
111 hda2codec_2x
|
||||
112 atomics
|
||||
113 audio0_2x
|
||||
114 audio1_2x
|
||||
115 audio2_2x
|
||||
116 audio3_2x
|
||||
117 audio4_2x
|
||||
118 audio5_2x
|
||||
119 actmon
|
||||
120 extern1
|
||||
121 extern2
|
||||
122 extern3
|
||||
123 sata_oob
|
||||
124 sata
|
||||
125 hda
|
||||
127 se
|
||||
128 hda2hdmi
|
||||
129 sata_cold
|
||||
|
||||
160 uartb
|
||||
161 vfir
|
||||
162 spdif_in
|
||||
163 spdif_out
|
||||
164 vi
|
||||
165 vi_sensor
|
||||
166 fuse
|
||||
167 fuse_burn
|
||||
168 cve
|
||||
169 tvo
|
||||
|
||||
170 clk_32k
|
||||
171 clk_m
|
||||
172 clk_m_div2
|
||||
173 clk_m_div4
|
||||
174 pll_ref
|
||||
175 pll_c
|
||||
176 pll_c_out1
|
||||
177 pll_m
|
||||
178 pll_m_out1
|
||||
179 pll_p
|
||||
180 pll_p_out1
|
||||
181 pll_p_out2
|
||||
182 pll_p_out3
|
||||
183 pll_p_out4
|
||||
184 pll_a
|
||||
185 pll_a_out0
|
||||
186 pll_d
|
||||
187 pll_d_out0
|
||||
188 pll_d2
|
||||
189 pll_d2_out0
|
||||
190 pll_u
|
||||
191 pll_x
|
||||
192 pll_x_out0
|
||||
193 pll_e
|
||||
194 spdif_in_sync
|
||||
195 i2s0_sync
|
||||
196 i2s1_sync
|
||||
197 i2s2_sync
|
||||
198 i2s3_sync
|
||||
199 i2s4_sync
|
||||
200 vimclk
|
||||
201 audio0
|
||||
202 audio1
|
||||
203 audio2
|
||||
204 audio3
|
||||
205 audio4
|
||||
206 audio5
|
||||
207 clk_out_1 (extern1)
|
||||
208 clk_out_2 (extern2)
|
||||
209 clk_out_3 (extern3)
|
||||
210 sclk
|
||||
211 blink
|
||||
212 cclk_g
|
||||
213 cclk_lp
|
||||
214 twd
|
||||
215 cml0
|
||||
216 cml1
|
||||
217 hclk
|
||||
218 pclk
|
||||
In clock consumers, this cell represents the clock ID exposed by the
|
||||
CAR. The assignments may be found in header file
|
||||
<dt-bindings/clock/tegra30-car.h>.
|
||||
|
||||
Example SoC include file:
|
||||
|
||||
|
|
@ -229,7 +26,7 @@ Example SoC include file:
|
|||
};
|
||||
|
||||
usb@c5004000 {
|
||||
clocks = <&tegra_car 58>; /* usb2 */
|
||||
clocks = <&tegra_car TEGRA30_CLK_USB2>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,342 @@
|
|||
/*
|
||||
* This header provides constants for binding nvidia,tegra114-car.
|
||||
*
|
||||
* The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
|
||||
* registers. These IDs often match those in the CAR's RST_DEVICES registers,
|
||||
* but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
|
||||
* this case, those clocks are assigned IDs above 160 in order to highlight
|
||||
* this issue. Implementations that interpret these clock IDs as bit values
|
||||
* within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
|
||||
* explicitly handle these special cases.
|
||||
*
|
||||
* The balance of the clocks controlled by the CAR are assigned IDs of 160 and
|
||||
* above.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_TEGRA114_CAR_H
|
||||
#define _DT_BINDINGS_CLOCK_TEGRA114_CAR_H
|
||||
|
||||
/* 0 */
|
||||
/* 1 */
|
||||
/* 2 */
|
||||
/* 3 */
|
||||
#define TEGRA114_CLK_RTC 4
|
||||
#define TEGRA114_CLK_TIMER 5
|
||||
#define TEGRA114_CLK_UARTA 6
|
||||
/* 7 (register bit affects uartb and vfir) */
|
||||
/* 8 */
|
||||
#define TEGRA114_CLK_SDMMC2 9
|
||||
/* 10 (register bit affects spdif_in and spdif_out) */
|
||||
#define TEGRA114_CLK_I2S1 11
|
||||
#define TEGRA114_CLK_I2C1 12
|
||||
#define TEGRA114_CLK_NDFLASH 13
|
||||
#define TEGRA114_CLK_SDMMC1 14
|
||||
#define TEGRA114_CLK_SDMMC4 15
|
||||
/* 16 */
|
||||
#define TEGRA114_CLK_PWM 17
|
||||
#define TEGRA114_CLK_I2S2 18
|
||||
#define TEGRA114_CLK_EPP 19
|
||||
/* 20 (register bit affects vi and vi_sensor) */
|
||||
#define TEGRA114_CLK_GR_2D 21
|
||||
#define TEGRA114_CLK_USBD 22
|
||||
#define TEGRA114_CLK_ISP 23
|
||||
#define TEGRA114_CLK_GR_3D 24
|
||||
/* 25 */
|
||||
#define TEGRA114_CLK_DISP2 26
|
||||
#define TEGRA114_CLK_DISP1 27
|
||||
#define TEGRA114_CLK_HOST1X 28
|
||||
#define TEGRA114_CLK_VCP 29
|
||||
#define TEGRA114_CLK_I2S0 30
|
||||
/* 31 */
|
||||
|
||||
/* 32 */
|
||||
/* 33 */
|
||||
#define TEGRA114_CLK_APBDMA 34
|
||||
/* 35 */
|
||||
#define TEGRA114_CLK_KBC 36
|
||||
/* 37 */
|
||||
/* 38 */
|
||||
/* 39 (register bit affects fuse and fuse_burn) */
|
||||
#define TEGRA114_CLK_KFUSE 40
|
||||
#define TEGRA114_CLK_SBC1 41
|
||||
#define TEGRA114_CLK_NOR 42
|
||||
/* 43 */
|
||||
#define TEGRA114_CLK_SBC2 44
|
||||
/* 45 */
|
||||
#define TEGRA114_CLK_SBC3 46
|
||||
#define TEGRA114_CLK_I2C5 47
|
||||
#define TEGRA114_CLK_DSIA 48
|
||||
/* 49 */
|
||||
#define TEGRA114_CLK_MIPI 50
|
||||
#define TEGRA114_CLK_HDMI 51
|
||||
#define TEGRA114_CLK_CSI 52
|
||||
/* 53 */
|
||||
#define TEGRA114_CLK_I2C2 54
|
||||
#define TEGRA114_CLK_UARTC 55
|
||||
#define TEGRA114_CLK_MIPI_CAL 56
|
||||
#define TEGRA114_CLK_EMC 57
|
||||
#define TEGRA114_CLK_USB2 58
|
||||
#define TEGRA114_CLK_USB3 59
|
||||
/* 60 */
|
||||
#define TEGRA114_CLK_VDE 61
|
||||
#define TEGRA114_CLK_BSEA 62
|
||||
#define TEGRA114_CLK_BSEV 63
|
||||
|
||||
/* 64 */
|
||||
#define TEGRA114_CLK_UARTD 65
|
||||
/* 66 */
|
||||
#define TEGRA114_CLK_I2C3 67
|
||||
#define TEGRA114_CLK_SBC4 68
|
||||
#define TEGRA114_CLK_SDMMC3 69
|
||||
/* 70 */
|
||||
#define TEGRA114_CLK_OWR 71
|
||||
/* 72 */
|
||||
#define TEGRA114_CLK_CSITE 73
|
||||
/* 74 */
|
||||
/* 75 */
|
||||
#define TEGRA114_CLK_LA 76
|
||||
#define TEGRA114_CLK_TRACE 77
|
||||
#define TEGRA114_CLK_SOC_THERM 78
|
||||
#define TEGRA114_CLK_DTV 79
|
||||
#define TEGRA114_CLK_NDSPEED 80
|
||||
#define TEGRA114_CLK_I2CSLOW 81
|
||||
#define TEGRA114_CLK_DSIB 82
|
||||
#define TEGRA114_CLK_TSEC 83
|
||||
/* 84 */
|
||||
/* 85 */
|
||||
/* 86 */
|
||||
/* 87 */
|
||||
/* 88 */
|
||||
#define TEGRA114_CLK_XUSB_HOST 89
|
||||
/* 90 */
|
||||
#define TEGRA114_CLK_MSENC 91
|
||||
#define TEGRA114_CLK_CSUS 92
|
||||
/* 93 */
|
||||
/* 94 */
|
||||
/* 95 (bit affects xusb_dev and xusb_dev_src) */
|
||||
|
||||
/* 96 */
|
||||
/* 97 */
|
||||
/* 98 */
|
||||
#define TEGRA114_CLK_MSELECT 99
|
||||
#define TEGRA114_CLK_TSENSOR 100
|
||||
#define TEGRA114_CLK_I2S3 101
|
||||
#define TEGRA114_CLK_I2S4 102
|
||||
#define TEGRA114_CLK_I2C4 103
|
||||
#define TEGRA114_CLK_SBC5 104
|
||||
#define TEGRA114_CLK_SBC6 105
|
||||
#define TEGRA114_CLK_D_AUDIO 106
|
||||
#define TEGRA114_CLK_APBIF 107
|
||||
#define TEGRA114_CLK_DAM0 108
|
||||
#define TEGRA114_CLK_DAM1 109
|
||||
#define TEGRA114_CLK_DAM2 110
|
||||
#define TEGRA114_CLK_HDA2CODEC_2X 111
|
||||
/* 112 */
|
||||
#define TEGRA114_CLK_AUDIO0_2X 113
|
||||
#define TEGRA114_CLK_AUDIO1_2X 114
|
||||
#define TEGRA114_CLK_AUDIO2_2X 115
|
||||
#define TEGRA114_CLK_AUDIO3_2X 116
|
||||
#define TEGRA114_CLK_AUDIO4_2X 117
|
||||
#define TEGRA114_CLK_SPDIF_2X 118
|
||||
#define TEGRA114_CLK_ACTMON 119
|
||||
#define TEGRA114_CLK_EXTERN1 120
|
||||
#define TEGRA114_CLK_EXTERN2 121
|
||||
#define TEGRA114_CLK_EXTERN3 122
|
||||
/* 123 */
|
||||
/* 124 */
|
||||
#define TEGRA114_CLK_HDA 125
|
||||
/* 126 */
|
||||
#define TEGRA114_CLK_SE 127
|
||||
|
||||
#define TEGRA114_CLK_HDA2HDMI 128
|
||||
/* 129 */
|
||||
/* 130 */
|
||||
/* 131 */
|
||||
/* 132 */
|
||||
/* 133 */
|
||||
/* 134 */
|
||||
/* 135 */
|
||||
/* 136 */
|
||||
/* 137 */
|
||||
/* 138 */
|
||||
/* 139 */
|
||||
/* 140 */
|
||||
/* 141 */
|
||||
/* 142 */
|
||||
/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
|
||||
/* xusb_host_src and xusb_ss_src) */
|
||||
#define TEGRA114_CLK_CILAB 144
|
||||
#define TEGRA114_CLK_CILCD 145
|
||||
#define TEGRA114_CLK_CILE 146
|
||||
#define TEGRA114_CLK_DSIALP 147
|
||||
#define TEGRA114_CLK_DSIBLP 148
|
||||
/* 149 */
|
||||
#define TEGRA114_CLK_DDS 150
|
||||
/* 151 */
|
||||
#define TEGRA114_CLK_DP2 152
|
||||
#define TEGRA114_CLK_AMX 153
|
||||
#define TEGRA114_CLK_ADX 154
|
||||
/* 155 (bit affects dfll_ref and dfll_soc) */
|
||||
#define TEGRA114_CLK_XUSB_SS 156
|
||||
/* 157 */
|
||||
/* 158 */
|
||||
/* 159 */
|
||||
|
||||
/* 160 */
|
||||
/* 161 */
|
||||
/* 162 */
|
||||
/* 163 */
|
||||
/* 164 */
|
||||
/* 165 */
|
||||
/* 166 */
|
||||
/* 167 */
|
||||
/* 168 */
|
||||
/* 169 */
|
||||
/* 170 */
|
||||
/* 171 */
|
||||
/* 172 */
|
||||
/* 173 */
|
||||
/* 174 */
|
||||
/* 175 */
|
||||
/* 176 */
|
||||
/* 177 */
|
||||
/* 178 */
|
||||
/* 179 */
|
||||
/* 180 */
|
||||
/* 181 */
|
||||
/* 182 */
|
||||
/* 183 */
|
||||
/* 184 */
|
||||
/* 185 */
|
||||
/* 186 */
|
||||
/* 187 */
|
||||
/* 188 */
|
||||
/* 189 */
|
||||
/* 190 */
|
||||
/* 191 */
|
||||
|
||||
#define TEGRA114_CLK_UARTB 192
|
||||
#define TEGRA114_CLK_VFIR 193
|
||||
#define TEGRA114_CLK_SPDIF_IN 194
|
||||
#define TEGRA114_CLK_SPDIF_OUT 195
|
||||
#define TEGRA114_CLK_VI 196
|
||||
#define TEGRA114_CLK_VI_SENSOR 197
|
||||
#define TEGRA114_CLK_FUSE 198
|
||||
#define TEGRA114_CLK_FUSE_BURN 199
|
||||
#define TEGRA114_CLK_CLK_32K 200
|
||||
#define TEGRA114_CLK_CLK_M 201
|
||||
#define TEGRA114_CLK_CLK_M_DIV2 202
|
||||
#define TEGRA114_CLK_CLK_M_DIV4 203
|
||||
#define TEGRA114_CLK_PLL_REF 204
|
||||
#define TEGRA114_CLK_PLL_C 205
|
||||
#define TEGRA114_CLK_PLL_C_OUT1 206
|
||||
#define TEGRA114_CLK_PLL_C2 207
|
||||
#define TEGRA114_CLK_PLL_C3 208
|
||||
#define TEGRA114_CLK_PLL_M 209
|
||||
#define TEGRA114_CLK_PLL_M_OUT1 210
|
||||
#define TEGRA114_CLK_PLL_P 211
|
||||
#define TEGRA114_CLK_PLL_P_OUT1 212
|
||||
#define TEGRA114_CLK_PLL_P_OUT2 213
|
||||
#define TEGRA114_CLK_PLL_P_OUT3 214
|
||||
#define TEGRA114_CLK_PLL_P_OUT4 215
|
||||
#define TEGRA114_CLK_PLL_A 216
|
||||
#define TEGRA114_CLK_PLL_A_OUT0 217
|
||||
#define TEGRA114_CLK_PLL_D 218
|
||||
#define TEGRA114_CLK_PLL_D_OUT0 219
|
||||
#define TEGRA114_CLK_PLL_D2 220
|
||||
#define TEGRA114_CLK_PLL_D2_OUT0 221
|
||||
#define TEGRA114_CLK_PLL_U 222
|
||||
#define TEGRA114_CLK_PLL_U_480M 223
|
||||
|
||||
#define TEGRA114_CLK_PLL_U_60M 224
|
||||
#define TEGRA114_CLK_PLL_U_48M 225
|
||||
#define TEGRA114_CLK_PLL_U_12M 226
|
||||
#define TEGRA114_CLK_PLL_X 227
|
||||
#define TEGRA114_CLK_PLL_X_OUT0 228
|
||||
#define TEGRA114_CLK_PLL_RE_VCO 229
|
||||
#define TEGRA114_CLK_PLL_RE_OUT 230
|
||||
#define TEGRA114_CLK_PLL_E_OUT0 231
|
||||
#define TEGRA114_CLK_SPDIF_IN_SYNC 232
|
||||
#define TEGRA114_CLK_I2S0_SYNC 233
|
||||
#define TEGRA114_CLK_I2S1_SYNC 234
|
||||
#define TEGRA114_CLK_I2S2_SYNC 235
|
||||
#define TEGRA114_CLK_I2S3_SYNC 236
|
||||
#define TEGRA114_CLK_I2S4_SYNC 237
|
||||
#define TEGRA114_CLK_VIMCLK_SYNC 238
|
||||
#define TEGRA114_CLK_AUDIO0 239
|
||||
#define TEGRA114_CLK_AUDIO1 240
|
||||
#define TEGRA114_CLK_AUDIO2 241
|
||||
#define TEGRA114_CLK_AUDIO3 242
|
||||
#define TEGRA114_CLK_AUDIO4 243
|
||||
#define TEGRA114_CLK_SPDIF 244
|
||||
#define TEGRA114_CLK_CLK_OUT_1 245
|
||||
#define TEGRA114_CLK_CLK_OUT_2 246
|
||||
#define TEGRA114_CLK_CLK_OUT_3 247
|
||||
#define TEGRA114_CLK_BLINK 248
|
||||
/* 249 */
|
||||
/* 250 */
|
||||
/* 251 */
|
||||
#define TEGRA114_CLK_XUSB_HOST_SRC 252
|
||||
#define TEGRA114_CLK_XUSB_FALCON_SRC 253
|
||||
#define TEGRA114_CLK_XUSB_FS_SRC 254
|
||||
#define TEGRA114_CLK_XUSB_SS_SRC 255
|
||||
|
||||
#define TEGRA114_CLK_XUSB_DEV_SRC 256
|
||||
#define TEGRA114_CLK_XUSB_DEV 257
|
||||
#define TEGRA114_CLK_XUSB_HS_SRC 258
|
||||
#define TEGRA114_CLK_SCLK 259
|
||||
#define TEGRA114_CLK_HCLK 260
|
||||
#define TEGRA114_CLK_PCLK 261
|
||||
#define TEGRA114_CLK_CCLK_G 262
|
||||
#define TEGRA114_CLK_CCLK_LP 263
|
||||
/* 264 */
|
||||
/* 265 */
|
||||
/* 266 */
|
||||
/* 267 */
|
||||
/* 268 */
|
||||
/* 269 */
|
||||
/* 270 */
|
||||
/* 271 */
|
||||
/* 272 */
|
||||
/* 273 */
|
||||
/* 274 */
|
||||
/* 275 */
|
||||
/* 276 */
|
||||
/* 277 */
|
||||
/* 278 */
|
||||
/* 279 */
|
||||
/* 280 */
|
||||
/* 281 */
|
||||
/* 282 */
|
||||
/* 283 */
|
||||
/* 284 */
|
||||
/* 285 */
|
||||
/* 286 */
|
||||
/* 287 */
|
||||
|
||||
/* 288 */
|
||||
/* 289 */
|
||||
/* 290 */
|
||||
/* 291 */
|
||||
/* 292 */
|
||||
/* 293 */
|
||||
/* 294 */
|
||||
/* 295 */
|
||||
/* 296 */
|
||||
/* 297 */
|
||||
/* 298 */
|
||||
/* 299 */
|
||||
#define TEGRA114_CLK_AUDIO0_MUX 300
|
||||
#define TEGRA114_CLK_AUDIO1_MUX 301
|
||||
#define TEGRA114_CLK_AUDIO2_MUX 302
|
||||
#define TEGRA114_CLK_AUDIO3_MUX 303
|
||||
#define TEGRA114_CLK_AUDIO4_MUX 304
|
||||
#define TEGRA114_CLK_SPDIF_MUX 305
|
||||
#define TEGRA114_CLK_CLK_OUT_1_MUX 306
|
||||
#define TEGRA114_CLK_CLK_OUT_2_MUX 307
|
||||
#define TEGRA114_CLK_CLK_OUT_3_MUX 308
|
||||
#define TEGRA114_CLK_DSIA_MUX 309
|
||||
#define TEGRA114_CLK_DSIB_MUX 310
|
||||
#define TEGRA114_CLK_CLK_MAX 311
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */
|
||||
|
|
@ -0,0 +1,158 @@
|
|||
/*
|
||||
* This header provides constants for binding nvidia,tegra20-car.
|
||||
*
|
||||
* The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
|
||||
* registers. These IDs often match those in the CAR's RST_DEVICES registers,
|
||||
* but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
|
||||
* this case, those clocks are assigned IDs above 95 in order to highlight
|
||||
* this issue. Implementations that interpret these clock IDs as bit values
|
||||
* within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
|
||||
* explicitly handle these special cases.
|
||||
*
|
||||
* The balance of the clocks controlled by the CAR are assigned IDs of 96 and
|
||||
* above.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_TEGRA20_CAR_H
|
||||
#define _DT_BINDINGS_CLOCK_TEGRA20_CAR_H
|
||||
|
||||
#define TEGRA20_CLK_CPU 0
|
||||
/* 1 */
|
||||
/* 2 */
|
||||
#define TEGRA20_CLK_AC97 3
|
||||
#define TEGRA20_CLK_RTC 4
|
||||
#define TEGRA20_CLK_TIMER 5
|
||||
#define TEGRA20_CLK_UARTA 6
|
||||
/* 7 (register bit affects uart2 and vfir) */
|
||||
#define TEGRA20_CLK_GPIO 8
|
||||
#define TEGRA20_CLK_SDMMC2 9
|
||||
/* 10 (register bit affects spdif_in and spdif_out) */
|
||||
#define TEGRA20_CLK_I2S1 11
|
||||
#define TEGRA20_CLK_I2C1 12
|
||||
#define TEGRA20_CLK_NDFLASH 13
|
||||
#define TEGRA20_CLK_SDMMC1 14
|
||||
#define TEGRA20_CLK_SDMMC4 15
|
||||
#define TEGRA20_CLK_TWC 16
|
||||
#define TEGRA20_CLK_PWM 17
|
||||
#define TEGRA20_CLK_I2S2 18
|
||||
#define TEGRA20_CLK_EPP 19
|
||||
/* 20 (register bit affects vi and vi_sensor) */
|
||||
#define TEGRA20_CLK_GR2D 21
|
||||
#define TEGRA20_CLK_USBD 22
|
||||
#define TEGRA20_CLK_ISP 23
|
||||
#define TEGRA20_CLK_GR3D 24
|
||||
#define TEGRA20_CLK_IDE 25
|
||||
#define TEGRA20_CLK_DISP2 26
|
||||
#define TEGRA20_CLK_DISP1 27
|
||||
#define TEGRA20_CLK_HOST1X 28
|
||||
#define TEGRA20_CLK_VCP 29
|
||||
/* 30 */
|
||||
#define TEGRA20_CLK_CACHE2 31
|
||||
|
||||
#define TEGRA20_CLK_MEM 32
|
||||
#define TEGRA20_CLK_AHBDMA 33
|
||||
#define TEGRA20_CLK_APBDMA 34
|
||||
/* 35 */
|
||||
#define TEGRA20_CLK_KBC 36
|
||||
#define TEGRA20_CLK_STAT_MON 37
|
||||
#define TEGRA20_CLK_PMC 38
|
||||
#define TEGRA20_CLK_FUSE 39
|
||||
#define TEGRA20_CLK_KFUSE 40
|
||||
#define TEGRA20_CLK_SBC1 41
|
||||
#define TEGRA20_CLK_NOR 42
|
||||
#define TEGRA20_CLK_SPI 43
|
||||
#define TEGRA20_CLK_SBC2 44
|
||||
#define TEGRA20_CLK_XIO 45
|
||||
#define TEGRA20_CLK_SBC3 46
|
||||
#define TEGRA20_CLK_DVC 47
|
||||
#define TEGRA20_CLK_DSI 48
|
||||
/* 49 (register bit affects tvo and cve) */
|
||||
#define TEGRA20_CLK_MIPI 50
|
||||
#define TEGRA20_CLK_HDMI 51
|
||||
#define TEGRA20_CLK_CSI 52
|
||||
#define TEGRA20_CLK_TVDAC 53
|
||||
#define TEGRA20_CLK_I2C2 54
|
||||
#define TEGRA20_CLK_UARTC 55
|
||||
/* 56 */
|
||||
#define TEGRA20_CLK_EMC 57
|
||||
#define TEGRA20_CLK_USB2 58
|
||||
#define TEGRA20_CLK_USB3 59
|
||||
#define TEGRA20_CLK_MPE 60
|
||||
#define TEGRA20_CLK_VDE 61
|
||||
#define TEGRA20_CLK_BSEA 62
|
||||
#define TEGRA20_CLK_BSEV 63
|
||||
|
||||
#define TEGRA20_CLK_SPEEDO 64
|
||||
#define TEGRA20_CLK_UARTD 65
|
||||
#define TEGRA20_CLK_UARTE 66
|
||||
#define TEGRA20_CLK_I2C3 67
|
||||
#define TEGRA20_CLK_SBC4 68
|
||||
#define TEGRA20_CLK_SDMMC3 69
|
||||
#define TEGRA20_CLK_PEX 70
|
||||
#define TEGRA20_CLK_OWR 71
|
||||
#define TEGRA20_CLK_AFI 72
|
||||
#define TEGRA20_CLK_CSITE 73
|
||||
#define TEGRA20_CLK_PCIE_XCLK 74
|
||||
#define TEGRA20_CLK_AVPUCQ 75
|
||||
#define TEGRA20_CLK_LA 76
|
||||
/* 77 */
|
||||
/* 78 */
|
||||
/* 79 */
|
||||
/* 80 */
|
||||
/* 81 */
|
||||
/* 82 */
|
||||
/* 83 */
|
||||
#define TEGRA20_CLK_IRAMA 84
|
||||
#define TEGRA20_CLK_IRAMB 85
|
||||
#define TEGRA20_CLK_IRAMC 86
|
||||
#define TEGRA20_CLK_IRAMD 87
|
||||
#define TEGRA20_CLK_CRAM2 88
|
||||
#define TEGRA20_CLK_AUDIO_2X 89 /* a/k/a audio_2x_sync_clk */
|
||||
#define TEGRA20_CLK_CLK_D 90
|
||||
/* 91 */
|
||||
#define TEGRA20_CLK_CSUS 92
|
||||
#define TEGRA20_CLK_CDEV2 93
|
||||
#define TEGRA20_CLK_CDEV1 94
|
||||
/* 95 */
|
||||
|
||||
#define TEGRA20_CLK_UARTB 96
|
||||
#define TEGRA20_CLK_VFIR 97
|
||||
#define TEGRA20_CLK_SPDIF_IN 98
|
||||
#define TEGRA20_CLK_SPDIF_OUT 99
|
||||
#define TEGRA20_CLK_VI 100
|
||||
#define TEGRA20_CLK_VI_SENSOR 101
|
||||
#define TEGRA20_CLK_TVO 102
|
||||
#define TEGRA20_CLK_CVE 103
|
||||
#define TEGRA20_CLK_OSC 104
|
||||
#define TEGRA20_CLK_CLK_32K 105 /* a/k/a clk_s */
|
||||
#define TEGRA20_CLK_CLK_M 106
|
||||
#define TEGRA20_CLK_SCLK 107
|
||||
#define TEGRA20_CLK_CCLK 108
|
||||
#define TEGRA20_CLK_HCLK 109
|
||||
#define TEGRA20_CLK_PCLK 110
|
||||
#define TEGRA20_CLK_BLINK 111
|
||||
#define TEGRA20_CLK_PLL_A 112
|
||||
#define TEGRA20_CLK_PLL_A_OUT0 113
|
||||
#define TEGRA20_CLK_PLL_C 114
|
||||
#define TEGRA20_CLK_PLL_C_OUT1 115
|
||||
#define TEGRA20_CLK_PLL_D 116
|
||||
#define TEGRA20_CLK_PLL_D_OUT0 117
|
||||
#define TEGRA20_CLK_PLL_E 118
|
||||
#define TEGRA20_CLK_PLL_M 119
|
||||
#define TEGRA20_CLK_PLL_M_OUT1 120
|
||||
#define TEGRA20_CLK_PLL_P 121
|
||||
#define TEGRA20_CLK_PLL_P_OUT1 122
|
||||
#define TEGRA20_CLK_PLL_P_OUT2 123
|
||||
#define TEGRA20_CLK_PLL_P_OUT3 124
|
||||
#define TEGRA20_CLK_PLL_P_OUT4 125
|
||||
#define TEGRA20_CLK_PLL_S 126
|
||||
#define TEGRA20_CLK_PLL_U 127
|
||||
|
||||
#define TEGRA20_CLK_PLL_X 128
|
||||
#define TEGRA20_CLK_COP 129 /* a/k/a avp */
|
||||
#define TEGRA20_CLK_AUDIO 130 /* a/k/a audio_sync_clk */
|
||||
#define TEGRA20_CLK_PLL_REF 131
|
||||
#define TEGRA20_CLK_TWD 132
|
||||
#define TEGRA20_CLK_CLK_MAX 133
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_TEGRA20_CAR_H */
|
||||
|
|
@ -0,0 +1,265 @@
|
|||
/*
|
||||
* This header provides constants for binding nvidia,tegra30-car.
|
||||
*
|
||||
* The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
|
||||
* registers. These IDs often match those in the CAR's RST_DEVICES registers,
|
||||
* but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
|
||||
* this case, those clocks are assigned IDs above 160 in order to highlight
|
||||
* this issue. Implementations that interpret these clock IDs as bit values
|
||||
* within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
|
||||
* explicitly handle these special cases.
|
||||
*
|
||||
* The balance of the clocks controlled by the CAR are assigned IDs of 160 and
|
||||
* above.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_TEGRA30_CAR_H
|
||||
#define _DT_BINDINGS_CLOCK_TEGRA30_CAR_H
|
||||
|
||||
#define TEGRA30_CLK_CPU 0
|
||||
/* 1 */
|
||||
/* 2 */
|
||||
/* 3 */
|
||||
#define TEGRA30_CLK_RTC 4
|
||||
#define TEGRA30_CLK_TIMER 5
|
||||
#define TEGRA30_CLK_UARTA 6
|
||||
/* 7 (register bit affects uartb and vfir) */
|
||||
#define TEGRA30_CLK_GPIO 8
|
||||
#define TEGRA30_CLK_SDMMC2 9
|
||||
/* 10 (register bit affects spdif_in and spdif_out) */
|
||||
#define TEGRA30_CLK_I2S1 11
|
||||
#define TEGRA30_CLK_I2C1 12
|
||||
#define TEGRA30_CLK_NDFLASH 13
|
||||
#define TEGRA30_CLK_SDMMC1 14
|
||||
#define TEGRA30_CLK_SDMMC4 15
|
||||
/* 16 */
|
||||
#define TEGRA30_CLK_PWM 17
|
||||
#define TEGRA30_CLK_I2S2 18
|
||||
#define TEGRA30_CLK_EPP 19
|
||||
/* 20 (register bit affects vi and vi_sensor) */
|
||||
#define TEGRA30_CLK_GR2D 21
|
||||
#define TEGRA30_CLK_USBD 22
|
||||
#define TEGRA30_CLK_ISP 23
|
||||
#define TEGRA30_CLK_GR3D 24
|
||||
/* 25 */
|
||||
#define TEGRA30_CLK_DISP2 26
|
||||
#define TEGRA30_CLK_DISP1 27
|
||||
#define TEGRA30_CLK_HOST1X 28
|
||||
#define TEGRA30_CLK_VCP 29
|
||||
#define TEGRA30_CLK_I2S0 30
|
||||
#define TEGRA30_CLK_COP_CACHE 31
|
||||
|
||||
#define TEGRA30_CLK_MC 32
|
||||
#define TEGRA30_CLK_AHBDMA 33
|
||||
#define TEGRA30_CLK_APBDMA 34
|
||||
/* 35 */
|
||||
#define TEGRA30_CLK_KBC 36
|
||||
#define TEGRA30_CLK_STATMON 37
|
||||
#define TEGRA30_CLK_PMC 38
|
||||
/* 39 (register bit affects fuse and fuse_burn) */
|
||||
#define TEGRA30_CLK_KFUSE 40
|
||||
#define TEGRA30_CLK_SBC1 41
|
||||
#define TEGRA30_CLK_NOR 42
|
||||
/* 43 */
|
||||
#define TEGRA30_CLK_SBC2 44
|
||||
/* 45 */
|
||||
#define TEGRA30_CLK_SBC3 46
|
||||
#define TEGRA30_CLK_I2C5 47
|
||||
#define TEGRA30_CLK_DSIA 48
|
||||
/* 49 (register bit affects cve and tvo) */
|
||||
#define TEGRA30_CLK_MIPI 50
|
||||
#define TEGRA30_CLK_HDMI 51
|
||||
#define TEGRA30_CLK_CSI 52
|
||||
#define TEGRA30_CLK_TVDAC 53
|
||||
#define TEGRA30_CLK_I2C2 54
|
||||
#define TEGRA30_CLK_UARTC 55
|
||||
/* 56 */
|
||||
#define TEGRA30_CLK_EMC 57
|
||||
#define TEGRA30_CLK_USB2 58
|
||||
#define TEGRA30_CLK_USB3 59
|
||||
#define TEGRA30_CLK_MPE 60
|
||||
#define TEGRA30_CLK_VDE 61
|
||||
#define TEGRA30_CLK_BSEA 62
|
||||
#define TEGRA30_CLK_BSEV 63
|
||||
|
||||
#define TEGRA30_CLK_SPEEDO 64
|
||||
#define TEGRA30_CLK_UARTD 65
|
||||
#define TEGRA30_CLK_UARTE 66
|
||||
#define TEGRA30_CLK_I2C3 67
|
||||
#define TEGRA30_CLK_SBC4 68
|
||||
#define TEGRA30_CLK_SDMMC3 69
|
||||
#define TEGRA30_CLK_PCIE 70
|
||||
#define TEGRA30_CLK_OWR 71
|
||||
#define TEGRA30_CLK_AFI 72
|
||||
#define TEGRA30_CLK_CSITE 73
|
||||
#define TEGRA30_CLK_PCIEX 74
|
||||
#define TEGRA30_CLK_AVPUCQ 75
|
||||
#define TEGRA30_CLK_LA 76
|
||||
/* 77 */
|
||||
/* 78 */
|
||||
#define TEGRA30_CLK_DTV 79
|
||||
#define TEGRA30_CLK_NDSPEED 80
|
||||
#define TEGRA30_CLK_I2CSLOW 81
|
||||
#define TEGRA30_CLK_DSIB 82
|
||||
/* 83 */
|
||||
#define TEGRA30_CLK_IRAMA 84
|
||||
#define TEGRA30_CLK_IRAMB 85
|
||||
#define TEGRA30_CLK_IRAMC 86
|
||||
#define TEGRA30_CLK_IRAMD 87
|
||||
#define TEGRA30_CLK_CRAM2 88
|
||||
/* 89 */
|
||||
#define TEGRA30_CLK_AUDIO_2X 90 /* a/k/a audio_2x_sync_clk */
|
||||
/* 91 */
|
||||
#define TEGRA30_CLK_CSUS 92
|
||||
#define TEGRA30_CLK_CDEV2 93
|
||||
#define TEGRA30_CLK_CDEV1 94
|
||||
/* 95 */
|
||||
|
||||
#define TEGRA30_CLK_CPU_G 96
|
||||
#define TEGRA30_CLK_CPU_LP 97
|
||||
#define TEGRA30_CLK_GR3D2 98
|
||||
#define TEGRA30_CLK_MSELECT 99
|
||||
#define TEGRA30_CLK_TSENSOR 100
|
||||
#define TEGRA30_CLK_I2S3 101
|
||||
#define TEGRA30_CLK_I2S4 102
|
||||
#define TEGRA30_CLK_I2C4 103
|
||||
#define TEGRA30_CLK_SBC5 104
|
||||
#define TEGRA30_CLK_SBC6 105
|
||||
#define TEGRA30_CLK_D_AUDIO 106
|
||||
#define TEGRA30_CLK_APBIF 107
|
||||
#define TEGRA30_CLK_DAM0 108
|
||||
#define TEGRA30_CLK_DAM1 109
|
||||
#define TEGRA30_CLK_DAM2 110
|
||||
#define TEGRA30_CLK_HDA2CODEC_2X 111
|
||||
#define TEGRA30_CLK_ATOMICS 112
|
||||
#define TEGRA30_CLK_AUDIO0_2X 113
|
||||
#define TEGRA30_CLK_AUDIO1_2X 114
|
||||
#define TEGRA30_CLK_AUDIO2_2X 115
|
||||
#define TEGRA30_CLK_AUDIO3_2X 116
|
||||
#define TEGRA30_CLK_AUDIO4_2X 117
|
||||
#define TEGRA30_CLK_SPDIF_2X 118
|
||||
#define TEGRA30_CLK_ACTMON 119
|
||||
#define TEGRA30_CLK_EXTERN1 120
|
||||
#define TEGRA30_CLK_EXTERN2 121
|
||||
#define TEGRA30_CLK_EXTERN3 122
|
||||
#define TEGRA30_CLK_SATA_OOB 123
|
||||
#define TEGRA30_CLK_SATA 124
|
||||
#define TEGRA30_CLK_HDA 125
|
||||
/* 126 */
|
||||
#define TEGRA30_CLK_SE 127
|
||||
|
||||
#define TEGRA30_CLK_HDA2HDMI 128
|
||||
#define TEGRA30_CLK_SATA_COLD 129
|
||||
/* 130 */
|
||||
/* 131 */
|
||||
/* 132 */
|
||||
/* 133 */
|
||||
/* 134 */
|
||||
/* 135 */
|
||||
/* 136 */
|
||||
/* 137 */
|
||||
/* 138 */
|
||||
/* 139 */
|
||||
/* 140 */
|
||||
/* 141 */
|
||||
/* 142 */
|
||||
/* 143 */
|
||||
/* 144 */
|
||||
/* 145 */
|
||||
/* 146 */
|
||||
/* 147 */
|
||||
/* 148 */
|
||||
/* 149 */
|
||||
/* 150 */
|
||||
/* 151 */
|
||||
/* 152 */
|
||||
/* 153 */
|
||||
/* 154 */
|
||||
/* 155 */
|
||||
/* 156 */
|
||||
/* 157 */
|
||||
/* 158 */
|
||||
/* 159 */
|
||||
|
||||
#define TEGRA30_CLK_UARTB 160
|
||||
#define TEGRA30_CLK_VFIR 161
|
||||
#define TEGRA30_CLK_SPDIF_IN 162
|
||||
#define TEGRA30_CLK_SPDIF_OUT 163
|
||||
#define TEGRA30_CLK_VI 164
|
||||
#define TEGRA30_CLK_VI_SENSOR 165
|
||||
#define TEGRA30_CLK_FUSE 166
|
||||
#define TEGRA30_CLK_FUSE_BURN 167
|
||||
#define TEGRA30_CLK_CVE 168
|
||||
#define TEGRA30_CLK_TVO 169
|
||||
#define TEGRA30_CLK_CLK_32K 170
|
||||
#define TEGRA30_CLK_CLK_M 171
|
||||
#define TEGRA30_CLK_CLK_M_DIV2 172
|
||||
#define TEGRA30_CLK_CLK_M_DIV4 173
|
||||
#define TEGRA30_CLK_PLL_REF 174
|
||||
#define TEGRA30_CLK_PLL_C 175
|
||||
#define TEGRA30_CLK_PLL_C_OUT1 176
|
||||
#define TEGRA30_CLK_PLL_M 177
|
||||
#define TEGRA30_CLK_PLL_M_OUT1 178
|
||||
#define TEGRA30_CLK_PLL_P 179
|
||||
#define TEGRA30_CLK_PLL_P_OUT1 180
|
||||
#define TEGRA30_CLK_PLL_P_OUT2 181
|
||||
#define TEGRA30_CLK_PLL_P_OUT3 182
|
||||
#define TEGRA30_CLK_PLL_P_OUT4 183
|
||||
#define TEGRA30_CLK_PLL_A 184
|
||||
#define TEGRA30_CLK_PLL_A_OUT0 185
|
||||
#define TEGRA30_CLK_PLL_D 186
|
||||
#define TEGRA30_CLK_PLL_D_OUT0 187
|
||||
#define TEGRA30_CLK_PLL_D2 188
|
||||
#define TEGRA30_CLK_PLL_D2_OUT0 189
|
||||
#define TEGRA30_CLK_PLL_U 190
|
||||
#define TEGRA30_CLK_PLL_X 191
|
||||
|
||||
#define TEGRA30_CLK_PLL_X_OUT0 192
|
||||
#define TEGRA30_CLK_PLL_E 193
|
||||
#define TEGRA30_CLK_SPDIF_IN_SYNC 194
|
||||
#define TEGRA30_CLK_I2S0_SYNC 195
|
||||
#define TEGRA30_CLK_I2S1_SYNC 196
|
||||
#define TEGRA30_CLK_I2S2_SYNC 197
|
||||
#define TEGRA30_CLK_I2S3_SYNC 198
|
||||
#define TEGRA30_CLK_I2S4_SYNC 199
|
||||
#define TEGRA30_CLK_VIMCLK_SYNC 200
|
||||
#define TEGRA30_CLK_AUDIO0 201
|
||||
#define TEGRA30_CLK_AUDIO1 202
|
||||
#define TEGRA30_CLK_AUDIO2 203
|
||||
#define TEGRA30_CLK_AUDIO3 204
|
||||
#define TEGRA30_CLK_AUDIO4 205
|
||||
#define TEGRA30_CLK_SPDIF 206
|
||||
#define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */
|
||||
#define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */
|
||||
#define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */
|
||||
#define TEGRA30_CLK_SCLK 210
|
||||
#define TEGRA30_CLK_BLINK 211
|
||||
#define TEGRA30_CLK_CCLK_G 212
|
||||
#define TEGRA30_CLK_CCLK_LP 213
|
||||
#define TEGRA30_CLK_TWD 214
|
||||
#define TEGRA30_CLK_CML0 215
|
||||
#define TEGRA30_CLK_CML1 216
|
||||
#define TEGRA30_CLK_HCLK 217
|
||||
#define TEGRA30_CLK_PCLK 218
|
||||
/* 219 */
|
||||
/* 220 */
|
||||
/* 221 */
|
||||
/* 222 */
|
||||
/* 223 */
|
||||
|
||||
/* 288 */
|
||||
/* 289 */
|
||||
/* 290 */
|
||||
/* 291 */
|
||||
/* 292 */
|
||||
/* 293 */
|
||||
/* 294 */
|
||||
/* 295 */
|
||||
/* 296 */
|
||||
/* 297 */
|
||||
/* 298 */
|
||||
/* 299 */
|
||||
#define TEGRA30_CLK_CLK_OUT_1_MUX 300
|
||||
#define TEGRA30_CLK_CLK_MAX 301
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */
|
||||
Loading…
Reference in New Issue