mirror of https://gitee.com/openkylin/linux.git
pinctrl: avoid duplicated calling enable_pinmux_setting for a pin
What the patch does: 1. Call pinmux_disable_setting ahead of pinmux_enable_setting each time pinctrl_select_state is called 2. Remove the HW disable operation in pinmux_disable_setting function. 3. Remove the disable ops in struct pinmux_ops 4. Remove all the disable ops users in current code base. Notes: 1. Great thanks for the suggestion from Linus, Tony Lindgren and Stephen Warren and Everyone that shared comments on this patch. 2. The patch also includes comment fixes from Stephen Warren. The reason why we do this: 1. To avoid duplicated calling of the enable_setting operation without disabling operation inbetween which will let the pin descriptor desc->mux_usecount increase monotonously. 2. The HW pin disable operation is not useful for any of the existing platforms. And this can be used to avoid the HW glitch after using the item #1 modification. In the following case, the issue can be reproduced: 1. There is a driver that need to switch pin state dynamically, e.g. between "sleep" and "default" state 2. The pin setting configuration in a DTS node may be like this: component a { pinctrl-names = "default", "sleep"; pinctrl-0 = <&a_grp_setting &c_grp_setting>; pinctrl-1 = <&b_grp_setting &c_grp_setting>; } The "c_grp_setting" config node is totally identical, maybe like following one: c_grp_setting: c_grp_setting { pinctrl-single,pins = <GPIO48 AF6>; } 3. When switching the pin state in the following official pinctrl sequence: pin = pinctrl_get(); state = pinctrl_lookup_state(wanted_state); pinctrl_select_state(state); pinctrl_put(); Test Result: 1. The switch is completed as expected, that is: the device's pin configuration is changed according to the description in the "wanted_state" group setting 2. The "desc->mux_usecount" of the corresponding pins in "c_group" is increased without being decreased, because the "desc" is for each physical pin while the setting is for each setting node in the DTS. Thus, if the "c_grp_setting" in pinctrl-0 is not disabled ahead of enabling "c_grp_setting" in pinctrl-1, the desc->mux_usecount will keep increasing without any chance to be decreased. According to the comments in the original code, only the setting, in old state but not in new state, will be "disabled" (calling pinmux_disable_setting), which is correct logic but not intact. We still need consider case that the setting is in both old state and new state. We can do this in the following two ways: 1. Avoid to "enable"(calling pinmux_enable_setting) the "same pin setting" repeatedly 2. "Disable"(calling pinmux_disable_setting) the "same pin setting", actually two setting instances, ahead of enabling them. Analysis: 1. The solution #2 is better because it can avoid too much iteration. 2. If we disable all of the settings in the old state and one of the setting(s) exist in the new state, the pins mux function change may happen when some SoC vendors defined the "pinctrl-single,function-off" in their DTS file. old_setting => disabled_setting => new_setting. 3. In the pinmux framework, when a pin state is switched, the setting in the old state should be marked as "disabled". Conclusion: 1. To Remove the HW disabling operation to above the glitch mentioned above. 2. Handle the issue mentioned above by disabling all of the settings in old state and then enable the all of the settings in new state. Signed-off-by: Fan Wu <fwu@marvell.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
parent
607af165c0
commit
2243a87d90
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@ -992,29 +992,15 @@ int pinctrl_select_state(struct pinctrl *p, struct pinctrl_state *state)
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if (p->state) {
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/*
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* The set of groups with a mux configuration in the old state
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* may not be identical to the set of groups with a mux setting
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* in the new state. While this might be unusual, it's entirely
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* possible for the "user"-supplied mapping table to be written
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* that way. For each group that was configured in the old state
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* but not in the new state, this code puts that group into a
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* safe/disabled state.
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* For each pinmux setting in the old state, forget SW's record
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* of mux owner for that pingroup. Any pingroups which are
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* still owned by the new state will be re-acquired by the call
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* to pinmux_enable_setting() in the loop below.
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*/
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list_for_each_entry(setting, &p->state->settings, node) {
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bool found = false;
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if (setting->type != PIN_MAP_TYPE_MUX_GROUP)
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continue;
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list_for_each_entry(setting2, &state->settings, node) {
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if (setting2->type != PIN_MAP_TYPE_MUX_GROUP)
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continue;
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if (setting2->data.mux.group ==
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setting->data.mux.group) {
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found = true;
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break;
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}
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}
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if (!found)
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pinmux_disable_setting(setting);
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pinmux_disable_setting(setting);
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}
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}
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@ -737,20 +737,6 @@ static int abx500_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
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return ret;
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}
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static void abx500_pmx_disable(struct pinctrl_dev *pctldev,
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unsigned function, unsigned group)
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{
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struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
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const struct abx500_pingroup *g;
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g = &pct->soc->groups[group];
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if (g->altsetting < 0)
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return;
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/* FIXME: poke out the mux, set the pin to some default state? */
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dev_dbg(pct->dev, "disable group %s, %u pins\n", g->name, g->npins);
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}
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static int abx500_gpio_request_enable(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned offset)
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@ -799,7 +785,6 @@ static const struct pinmux_ops abx500_pinmux_ops = {
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.get_function_name = abx500_pmx_get_func_name,
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.get_function_groups = abx500_pmx_get_func_groups,
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.enable = abx500_pmx_enable,
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.disable = abx500_pmx_disable,
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.gpio_request_enable = abx500_gpio_request_enable,
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.gpio_disable_free = abx500_gpio_disable_free,
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};
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@ -652,35 +652,6 @@ static int adi_pinmux_enable(struct pinctrl_dev *pctldev, unsigned func_id,
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return 0;
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}
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static void adi_pinmux_disable(struct pinctrl_dev *pctldev, unsigned func_id,
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unsigned group_id)
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{
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struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
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struct gpio_port *port;
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struct pinctrl_gpio_range *range;
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unsigned long flags;
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unsigned short *mux, pin;
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mux = (unsigned short *)pinctrl->soc->groups[group_id].mux;
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while (*mux) {
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pin = P_IDENT(*mux);
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range = pinctrl_find_gpio_range_from_pin(pctldev, pin);
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if (range == NULL) /* should not happen */
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return;
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port = container_of(range->gc, struct gpio_port, chip);
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spin_lock_irqsave(&port->lock, flags);
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port_setup(port, pin_to_offset(range, pin), true);
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mux++;
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spin_unlock_irqrestore(&port->lock, flags);
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}
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}
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static int adi_pinmux_get_funcs_count(struct pinctrl_dev *pctldev)
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{
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struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
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@ -728,7 +699,6 @@ static int adi_pinmux_request_gpio(struct pinctrl_dev *pctldev,
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static struct pinmux_ops adi_pinmux_ops = {
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.enable = adi_pinmux_enable,
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.disable = adi_pinmux_disable,
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.get_functions_count = adi_pinmux_get_funcs_count,
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.get_function_name = adi_pinmux_get_func_name,
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.get_function_groups = adi_pinmux_get_groups,
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@ -611,26 +611,6 @@ static int at91_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
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return 0;
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}
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static void at91_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector,
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unsigned group)
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{
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struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
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const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
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const struct at91_pmx_pin *pin;
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uint32_t npins = info->groups[group].npins;
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int i;
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unsigned mask;
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void __iomem *pio;
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for (i = 0; i < npins; i++) {
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pin = &pins_conf[i];
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at91_pin_dbg(info->dev, pin);
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pio = pin_to_controller(info, pin->bank);
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mask = pin_to_mask(pin->pin);
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at91_mux_gpio_enable(pio, mask, 1);
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}
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}
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static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
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{
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struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
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@ -705,7 +685,6 @@ static const struct pinmux_ops at91_pmx_ops = {
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.get_function_name = at91_pmx_get_func_name,
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.get_function_groups = at91_pmx_get_groups,
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.enable = at91_pmx_enable,
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.disable = at91_pmx_disable,
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.gpio_request_enable = at91_gpio_request_enable,
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.gpio_disable_free = at91_gpio_disable_free,
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};
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@ -841,16 +841,6 @@ static int bcm2835_pmx_enable(struct pinctrl_dev *pctldev,
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return 0;
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}
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static void bcm2835_pmx_disable(struct pinctrl_dev *pctldev,
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unsigned func_selector,
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unsigned group_selector)
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{
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struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
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/* disable by setting to GPIO_IN */
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bcm2835_pinctrl_fsel_set(pc, group_selector, BCM2835_FSEL_GPIO_IN);
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}
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static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned offset)
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.get_function_name = bcm2835_pmx_get_function_name,
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.get_function_groups = bcm2835_pmx_get_function_groups,
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.enable = bcm2835_pmx_enable,
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.disable = bcm2835_pmx_disable,
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.gpio_disable_free = bcm2835_pmx_gpio_disable_free,
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.gpio_set_direction = bcm2835_pmx_gpio_set_direction,
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};
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@ -371,13 +371,6 @@ static int exynos5440_pinmux_enable(struct pinctrl_dev *pctldev, unsigned select
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return 0;
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}
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/* disable a specified pinmux by writing to registers */
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static void exynos5440_pinmux_disable(struct pinctrl_dev *pctldev,
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unsigned selector, unsigned group)
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{
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exynos5440_pinmux_setup(pctldev, selector, group, false);
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}
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/*
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* The calls to gpio_direction_output() and gpio_direction_input()
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* leads to this function call (via the pinctrl_gpio_direction_{input|output}()
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.get_function_name = exynos5440_pinmux_get_fname,
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.get_function_groups = exynos5440_pinmux_get_groups,
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.enable = exynos5440_pinmux_enable,
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.disable = exynos5440_pinmux_disable,
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.gpio_set_direction = exynos5440_pinmux_gpio_set_direction,
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};
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@ -165,36 +165,11 @@ static int msm_pinmux_enable(struct pinctrl_dev *pctldev,
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return 0;
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}
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static void msm_pinmux_disable(struct pinctrl_dev *pctldev,
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unsigned function,
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unsigned group)
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{
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struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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const struct msm_pingroup *g;
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unsigned long flags;
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u32 val;
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g = &pctrl->soc->groups[group];
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if (WARN_ON(g->mux_bit < 0))
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return;
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spin_lock_irqsave(&pctrl->lock, flags);
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/* Clear the mux bits to select gpio mode */
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val = readl(pctrl->regs + g->ctl_reg);
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val &= ~(0x7 << g->mux_bit);
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writel(val, pctrl->regs + g->ctl_reg);
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spin_unlock_irqrestore(&pctrl->lock, flags);
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}
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static const struct pinmux_ops msm_pinmux_ops = {
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.get_functions_count = msm_get_functions_count,
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.get_function_name = msm_get_function_name,
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.get_function_groups = msm_get_function_groups,
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.enable = msm_pinmux_enable,
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.disable = msm_pinmux_disable,
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};
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static int msm_config_reg(struct msm_pinctrl *pctrl,
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@ -1765,21 +1765,6 @@ static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
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return ret;
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}
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static void nmk_pmx_disable(struct pinctrl_dev *pctldev,
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unsigned function, unsigned group)
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{
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struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
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const struct nmk_pingroup *g;
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g = &npct->soc->groups[group];
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if (g->altsetting < 0)
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return;
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/* Poke out the mux, set the pin to some default state? */
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dev_dbg(npct->dev, "disable group %s, %u pins\n", g->name, g->npins);
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}
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static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned offset)
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.get_function_name = nmk_pmx_get_func_name,
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.get_function_groups = nmk_pmx_get_func_groups,
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.enable = nmk_pmx_enable,
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.disable = nmk_pmx_disable,
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.gpio_request_enable = nmk_gpio_request_enable,
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.gpio_disable_free = nmk_gpio_disable_free,
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};
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@ -657,23 +657,6 @@ static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
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return 0;
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}
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static void rockchip_pmx_disable(struct pinctrl_dev *pctldev,
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unsigned selector, unsigned group)
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{
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struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
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const unsigned int *pins = info->groups[group].pins;
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struct rockchip_pin_bank *bank;
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int cnt;
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dev_dbg(info->dev, "disable function %s group %s\n",
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info->functions[selector].name, info->groups[group].name);
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for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
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bank = pin_to_bank(info, pins[cnt]);
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rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
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}
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}
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/*
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* The calls to gpio_direction_output() and gpio_direction_input()
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* leads to this function call (via the pinctrl_gpio_direction_{input|output}()
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.get_function_name = rockchip_pmx_get_func_name,
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.get_function_groups = rockchip_pmx_get_groups,
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.enable = rockchip_pmx_enable,
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.disable = rockchip_pmx_disable,
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.gpio_set_direction = rockchip_pmx_gpio_set_direction,
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};
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@ -333,13 +333,6 @@ static int samsung_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector,
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return 0;
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}
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/* disable a specified pinmux by writing to registers */
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static void samsung_pinmux_disable(struct pinctrl_dev *pctldev,
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unsigned selector, unsigned group)
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{
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samsung_pinmux_setup(pctldev, selector, group, false);
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}
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/*
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* The calls to gpio_direction_output() and gpio_direction_input()
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* leads to this function call (via the pinctrl_gpio_direction_{input|output}()
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.get_function_name = samsung_pinmux_get_fname,
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.get_function_groups = samsung_pinmux_get_groups,
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.enable = samsung_pinmux_enable,
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.disable = samsung_pinmux_disable,
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.gpio_set_direction = samsung_pinmux_gpio_set_direction,
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};
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@ -488,61 +488,6 @@ static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector,
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return 0;
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}
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static void pcs_disable(struct pinctrl_dev *pctldev, unsigned fselector,
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unsigned group)
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{
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struct pcs_device *pcs;
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struct pcs_function *func;
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int i;
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pcs = pinctrl_dev_get_drvdata(pctldev);
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/* If function mask is null, needn't disable it. */
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if (!pcs->fmask)
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return;
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func = radix_tree_lookup(&pcs->ftree, fselector);
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if (!func) {
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dev_err(pcs->dev, "%s could not find function%i\n",
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__func__, fselector);
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return;
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}
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/*
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* Ignore disable if function-off is not specified. Some hardware
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* does not have clearly defined disable function. For pin specific
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* off modes, you can use alternate named states as described in
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* pinctrl-bindings.txt.
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*/
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if (pcs->foff == PCS_OFF_DISABLED) {
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dev_dbg(pcs->dev, "ignoring disable for %s function%i\n",
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func->name, fselector);
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return;
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}
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dev_dbg(pcs->dev, "disabling function%i %s\n",
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fselector, func->name);
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for (i = 0; i < func->nvals; i++) {
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struct pcs_func_vals *vals;
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unsigned long flags;
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unsigned val, mask;
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vals = &func->vals[i];
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raw_spin_lock_irqsave(&pcs->lock, flags);
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val = pcs->read(vals->reg);
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if (pcs->bits_per_mux)
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mask = vals->mask;
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else
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mask = pcs->fmask;
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val &= ~mask;
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val |= pcs->foff << pcs->fshift;
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||||
pcs->write(val, vals->reg);
|
||||
raw_spin_unlock_irqrestore(&pcs->lock, flags);
|
||||
}
|
||||
}
|
||||
|
||||
static int pcs_request_gpio(struct pinctrl_dev *pctldev,
|
||||
struct pinctrl_gpio_range *range, unsigned pin)
|
||||
{
|
||||
|
@ -575,7 +520,6 @@ static const struct pinmux_ops pcs_pinmux_ops = {
|
|||
.get_function_name = pcs_get_function_name,
|
||||
.get_function_groups = pcs_get_function_groups,
|
||||
.enable = pcs_enable,
|
||||
.disable = pcs_disable,
|
||||
.gpio_request_enable = pcs_request_gpio,
|
||||
};
|
||||
|
||||
|
|
|
@ -930,11 +930,6 @@ static int st_pmx_enable(struct pinctrl_dev *pctldev, unsigned fselector,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void st_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector,
|
||||
unsigned group)
|
||||
{
|
||||
}
|
||||
|
||||
static int st_pmx_set_gpio_direction(struct pinctrl_dev *pctldev,
|
||||
struct pinctrl_gpio_range *range, unsigned gpio,
|
||||
bool input)
|
||||
|
@ -957,7 +952,6 @@ static struct pinmux_ops st_pmxops = {
|
|||
.get_function_name = st_pmx_get_fname,
|
||||
.get_function_groups = st_pmx_get_groups,
|
||||
.enable = st_pmx_enable,
|
||||
.disable = st_pmx_disable,
|
||||
.gpio_set_direction = st_pmx_set_gpio_direction,
|
||||
};
|
||||
|
||||
|
|
|
@ -738,22 +738,6 @@ static int tb10x_pctl_enable(struct pinctrl_dev *pctl,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void tb10x_pctl_disable(struct pinctrl_dev *pctl,
|
||||
unsigned func_selector, unsigned group_selector)
|
||||
{
|
||||
struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
|
||||
const struct tb10x_pinfuncgrp *grp = &state->pingroups[group_selector];
|
||||
|
||||
if (grp->port < 0)
|
||||
return;
|
||||
|
||||
mutex_lock(&state->mutex);
|
||||
|
||||
state->ports[grp->port].count--;
|
||||
|
||||
mutex_unlock(&state->mutex);
|
||||
}
|
||||
|
||||
static struct pinmux_ops tb10x_pinmux_ops = {
|
||||
.get_functions_count = tb10x_get_functions_count,
|
||||
.get_function_name = tb10x_get_function_name,
|
||||
|
@ -761,7 +745,6 @@ static struct pinmux_ops tb10x_pinmux_ops = {
|
|||
.gpio_request_enable = tb10x_gpio_request_enable,
|
||||
.gpio_disable_free = tb10x_gpio_disable_free,
|
||||
.enable = tb10x_pctl_enable,
|
||||
.disable = tb10x_pctl_disable,
|
||||
};
|
||||
|
||||
static struct pinctrl_desc tb10x_pindesc = {
|
||||
|
|
|
@ -290,24 +290,11 @@ static int tegra_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev,
|
||||
unsigned function, unsigned group)
|
||||
{
|
||||
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
|
||||
const struct tegra_pingroup *g;
|
||||
|
||||
g = &pmx->soc->groups[group];
|
||||
|
||||
if (WARN_ON(g->mux_reg < 0))
|
||||
return;
|
||||
}
|
||||
|
||||
static const struct pinmux_ops tegra_pinmux_ops = {
|
||||
.get_functions_count = tegra_pinctrl_get_funcs_count,
|
||||
.get_function_name = tegra_pinctrl_get_func_name,
|
||||
.get_function_groups = tegra_pinctrl_get_func_groups,
|
||||
.enable = tegra_pinctrl_enable,
|
||||
.disable = tegra_pinctrl_disable,
|
||||
};
|
||||
|
||||
static int tegra_pinconf_reg(struct tegra_pmx *pmx,
|
||||
|
|
|
@ -574,33 +574,6 @@ static int tz1090_pdc_pinctrl_enable(struct pinctrl_dev *pctldev,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void tz1090_pdc_pinctrl_disable(struct pinctrl_dev *pctldev,
|
||||
unsigned int function,
|
||||
unsigned int group)
|
||||
{
|
||||
struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
|
||||
const struct tz1090_pdc_pingroup *grp = &tz1090_pdc_groups[group];
|
||||
|
||||
dev_dbg(pctldev->dev, "%s(func=%u (%s), group=%u (%s))\n",
|
||||
__func__,
|
||||
function, tz1090_pdc_functions[function].name,
|
||||
group, tz1090_pdc_groups[group].name);
|
||||
|
||||
/* is it even a mux? */
|
||||
if (grp->drv)
|
||||
return;
|
||||
|
||||
/* does this group even control the function? */
|
||||
if (function != grp->func)
|
||||
return;
|
||||
|
||||
/* record the pin being unmuxed and update mux bit */
|
||||
spin_lock(&pmx->lock);
|
||||
pmx->mux_en &= ~BIT(grp->pins[0]);
|
||||
tz1090_pdc_pinctrl_mux(pmx, grp);
|
||||
spin_unlock(&pmx->lock);
|
||||
}
|
||||
|
||||
static const struct tz1090_pdc_pingroup *find_mux_group(
|
||||
struct tz1090_pdc_pmx *pmx,
|
||||
unsigned int pin)
|
||||
|
@ -662,7 +635,6 @@ static struct pinmux_ops tz1090_pdc_pinmux_ops = {
|
|||
.get_function_name = tz1090_pdc_pinctrl_get_func_name,
|
||||
.get_function_groups = tz1090_pdc_pinctrl_get_func_groups,
|
||||
.enable = tz1090_pdc_pinctrl_enable,
|
||||
.disable = tz1090_pdc_pinctrl_disable,
|
||||
.gpio_request_enable = tz1090_pdc_pinctrl_gpio_request_enable,
|
||||
.gpio_disable_free = tz1090_pdc_pinctrl_gpio_disable_free,
|
||||
};
|
||||
|
|
|
@ -1478,63 +1478,6 @@ static int tz1090_pinctrl_enable(struct pinctrl_dev *pctldev,
|
|||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* tz1090_pinctrl_disable() - Disable a function on a pin group.
|
||||
* @pctldev: Pin control data
|
||||
* @function: Function index to disable
|
||||
* @group: Group index to disable
|
||||
*
|
||||
* Disable a particular function on a group of pins. The per GPIO pin pseudo pin
|
||||
* groups can be used (in which case the pin will be taken out of peripheral
|
||||
* mode. Some convenience pin groups can also be used in which case the effect
|
||||
* is the same as enabling the function on each individual pin in the group.
|
||||
*/
|
||||
static void tz1090_pinctrl_disable(struct pinctrl_dev *pctldev,
|
||||
unsigned int function, unsigned int group)
|
||||
{
|
||||
struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
|
||||
struct tz1090_pingroup *grp;
|
||||
unsigned int pin_num, mux_group, i, npins;
|
||||
const unsigned int *pins;
|
||||
|
||||
/* group of pins? */
|
||||
if (group < ARRAY_SIZE(tz1090_groups)) {
|
||||
grp = &tz1090_groups[group];
|
||||
npins = grp->npins;
|
||||
pins = grp->pins;
|
||||
/*
|
||||
* All pins in the group must belong to the same mux group,
|
||||
* which allows us to just use the mux group of the first pin.
|
||||
* By explicitly listing permitted pingroups for each function
|
||||
* the pinmux core should ensure this is always the case.
|
||||
*/
|
||||
} else {
|
||||
pin_num = group - ARRAY_SIZE(tz1090_groups);
|
||||
npins = 1;
|
||||
pins = &pin_num;
|
||||
}
|
||||
mux_group = tz1090_mux_pins[*pins];
|
||||
|
||||
/* no mux group, but can still be individually muxed to peripheral */
|
||||
if (mux_group >= TZ1090_MUX_GROUP_MAX) {
|
||||
if (function == TZ1090_MUX_PERIP)
|
||||
goto unmux_pins;
|
||||
return;
|
||||
}
|
||||
|
||||
/* mux group already set to a different function? */
|
||||
grp = &tz1090_mux_groups[mux_group];
|
||||
dev_dbg(pctldev->dev, "%s: unmuxing %u pin(s) in '%s' from '%s'\n",
|
||||
__func__, npins, grp->name, tz1090_functions[function].name);
|
||||
|
||||
/* subtract pins from ref count and unmux individually */
|
||||
WARN_ON(grp->func_count < npins);
|
||||
grp->func_count -= npins;
|
||||
unmux_pins:
|
||||
for (i = 0; i < npins; ++i)
|
||||
tz1090_pinctrl_perip_select(pmx, pins[i], false);
|
||||
}
|
||||
|
||||
/**
|
||||
* tz1090_pinctrl_gpio_request_enable() - Put pin in GPIO mode.
|
||||
* @pctldev: Pin control data
|
||||
|
@ -1575,7 +1518,6 @@ static struct pinmux_ops tz1090_pinmux_ops = {
|
|||
.get_function_name = tz1090_pinctrl_get_func_name,
|
||||
.get_function_groups = tz1090_pinctrl_get_func_groups,
|
||||
.enable = tz1090_pinctrl_enable,
|
||||
.disable = tz1090_pinctrl_disable,
|
||||
.gpio_request_enable = tz1090_pinctrl_gpio_request_enable,
|
||||
.gpio_disable_free = tz1090_pinctrl_gpio_disable_free,
|
||||
};
|
||||
|
|
|
@ -970,19 +970,6 @@ static int u300_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void u300_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector,
|
||||
unsigned group)
|
||||
{
|
||||
struct u300_pmx *upmx;
|
||||
|
||||
/* There is nothing to do with the power pins */
|
||||
if (selector == 0)
|
||||
return;
|
||||
|
||||
upmx = pinctrl_dev_get_drvdata(pctldev);
|
||||
u300_pmx_endisable(upmx, selector, false);
|
||||
}
|
||||
|
||||
static int u300_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
|
||||
{
|
||||
return ARRAY_SIZE(u300_pmx_functions);
|
||||
|
@ -1008,7 +995,6 @@ static const struct pinmux_ops u300_pmx_ops = {
|
|||
.get_function_name = u300_pmx_get_func_name,
|
||||
.get_function_groups = u300_pmx_get_groups,
|
||||
.enable = u300_pmx_enable,
|
||||
.disable = u300_pmx_disable,
|
||||
};
|
||||
|
||||
static int u300_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
|
||||
|
|
|
@ -471,7 +471,6 @@ void pinmux_disable_setting(struct pinctrl_setting const *setting)
|
|||
{
|
||||
struct pinctrl_dev *pctldev = setting->pctldev;
|
||||
const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
|
||||
const struct pinmux_ops *ops = pctldev->desc->pmxops;
|
||||
int ret = 0;
|
||||
const unsigned *pins = NULL;
|
||||
unsigned num_pins = 0;
|
||||
|
@ -518,9 +517,6 @@ void pinmux_disable_setting(struct pinctrl_setting const *setting)
|
|||
pins[i], desc->name, gname);
|
||||
}
|
||||
}
|
||||
|
||||
if (ops->disable)
|
||||
ops->disable(pctldev, setting->data.mux.func, setting->data.mux.group);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
|
|
|
@ -345,27 +345,6 @@ static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector,
|
|||
return ret;
|
||||
}
|
||||
|
||||
static void sh_pfc_func_disable(struct pinctrl_dev *pctldev, unsigned selector,
|
||||
unsigned group)
|
||||
{
|
||||
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
|
||||
struct sh_pfc *pfc = pmx->pfc;
|
||||
const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
|
||||
unsigned long flags;
|
||||
unsigned int i;
|
||||
|
||||
spin_lock_irqsave(&pfc->lock, flags);
|
||||
|
||||
for (i = 0; i < grp->nr_pins; ++i) {
|
||||
int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
|
||||
struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
|
||||
|
||||
cfg->type = PINMUX_TYPE_NONE;
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&pfc->lock, flags);
|
||||
}
|
||||
|
||||
static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
|
||||
struct pinctrl_gpio_range *range,
|
||||
unsigned offset)
|
||||
|
@ -464,7 +443,6 @@ static const struct pinmux_ops sh_pfc_pinmux_ops = {
|
|||
.get_function_name = sh_pfc_get_function_name,
|
||||
.get_function_groups = sh_pfc_get_function_groups,
|
||||
.enable = sh_pfc_func_enable,
|
||||
.disable = sh_pfc_func_disable,
|
||||
.gpio_request_enable = sh_pfc_gpio_request_enable,
|
||||
.gpio_disable_free = sh_pfc_gpio_disable_free,
|
||||
.gpio_set_direction = sh_pfc_gpio_set_direction,
|
||||
|
|
|
@ -186,15 +186,6 @@ static int sirfsoc_pinmux_enable(struct pinctrl_dev *pmxdev, unsigned selector,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void sirfsoc_pinmux_disable(struct pinctrl_dev *pmxdev, unsigned selector,
|
||||
unsigned group)
|
||||
{
|
||||
struct sirfsoc_pmx *spmx;
|
||||
|
||||
spmx = pinctrl_dev_get_drvdata(pmxdev);
|
||||
sirfsoc_pinmux_endisable(spmx, selector, false);
|
||||
}
|
||||
|
||||
static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev)
|
||||
{
|
||||
return sirfsoc_pmxfunc_cnt;
|
||||
|
@ -240,7 +231,6 @@ static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
|
|||
|
||||
static struct pinmux_ops sirfsoc_pinmux_ops = {
|
||||
.enable = sirfsoc_pinmux_enable,
|
||||
.disable = sirfsoc_pinmux_disable,
|
||||
.get_functions_count = sirfsoc_pinmux_get_funcs_count,
|
||||
.get_function_name = sirfsoc_pinmux_get_func_name,
|
||||
.get_function_groups = sirfsoc_pinmux_get_groups,
|
||||
|
|
|
@ -274,12 +274,6 @@ static int spear_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
|
|||
return spear_pinctrl_endisable(pctldev, function, group, true);
|
||||
}
|
||||
|
||||
static void spear_pinctrl_disable(struct pinctrl_dev *pctldev,
|
||||
unsigned function, unsigned group)
|
||||
{
|
||||
spear_pinctrl_endisable(pctldev, function, group, false);
|
||||
}
|
||||
|
||||
/* gpio with pinmux */
|
||||
static struct spear_gpio_pingroup *get_gpio_pingroup(struct spear_pmx *pmx,
|
||||
unsigned pin)
|
||||
|
@ -345,7 +339,6 @@ static const struct pinmux_ops spear_pinmux_ops = {
|
|||
.get_function_name = spear_pinctrl_get_func_name,
|
||||
.get_function_groups = spear_pinctrl_get_func_groups,
|
||||
.enable = spear_pinctrl_enable,
|
||||
.disable = spear_pinctrl_disable,
|
||||
.gpio_request_enable = gpio_request_enable,
|
||||
.gpio_disable_free = gpio_disable_free,
|
||||
};
|
||||
|
|
|
@ -141,17 +141,6 @@ static int wmt_pmx_enable(struct pinctrl_dev *pctldev,
|
|||
return wmt_set_pinmux(data, func_selector, pinnum);
|
||||
}
|
||||
|
||||
static void wmt_pmx_disable(struct pinctrl_dev *pctldev,
|
||||
unsigned func_selector,
|
||||
unsigned group_selector)
|
||||
{
|
||||
struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev);
|
||||
u32 pinnum = data->pins[group_selector].number;
|
||||
|
||||
/* disable by setting GPIO_IN */
|
||||
wmt_set_pinmux(data, WMT_FSEL_GPIO_IN, pinnum);
|
||||
}
|
||||
|
||||
static void wmt_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
|
||||
struct pinctrl_gpio_range *range,
|
||||
unsigned offset)
|
||||
|
@ -180,7 +169,6 @@ static struct pinmux_ops wmt_pinmux_ops = {
|
|||
.get_function_name = wmt_pmx_get_function_name,
|
||||
.get_function_groups = wmt_pmx_get_function_groups,
|
||||
.enable = wmt_pmx_enable,
|
||||
.disable = wmt_pmx_disable,
|
||||
.gpio_disable_free = wmt_pmx_gpio_disable_free,
|
||||
.gpio_set_direction = wmt_pmx_gpio_set_direction,
|
||||
};
|
||||
|
|
|
@ -70,8 +70,6 @@ struct pinmux_ops {
|
|||
unsigned * const num_groups);
|
||||
int (*enable) (struct pinctrl_dev *pctldev, unsigned func_selector,
|
||||
unsigned group_selector);
|
||||
void (*disable) (struct pinctrl_dev *pctldev, unsigned func_selector,
|
||||
unsigned group_selector);
|
||||
int (*gpio_request_enable) (struct pinctrl_dev *pctldev,
|
||||
struct pinctrl_gpio_range *range,
|
||||
unsigned offset);
|
||||
|
|
Loading…
Reference in New Issue