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clk: samsung: exynos5260: fix typo in clock name
The parent name added in parent list as mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p, is different than the defined parent due to typo. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: Chander Kashyap <k.chander@samsung.com> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
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@ -1581,7 +1581,7 @@ struct samsung_fixed_rate_clock fixed_rate_clks[] __initdata = {
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FRATE(PHYCLK_HDMI_LINK_O_TMDS_CLKHI, "phyclk_hdmi_link_o_tmds_clkhi",
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NULL, CLK_IS_ROOT, 125000000),
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FRATE(PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS,
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"phyclk_mipi_dphy_4l_m_txbyteclkhs" , NULL,
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"phyclk_mipi_dphy_4l_m_txbyte_clkhs" , NULL,
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CLK_IS_ROOT, 187500000),
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FRATE(PHYCLK_DPTX_PHY_O_REF_CLK_24M, "phyclk_dptx_phy_o_ref_clk_24m",
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NULL, CLK_IS_ROOT, 24000000),
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