mirror of https://gitee.com/openkylin/linux.git
ARM: shmobile: r8a7790: Add clocks
Declare all core clocks and DIV6 clocks, as well as all MSTP clocks currently used by r8a7790 boards. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Laurent Pinchart
Simon Horman
parent
90c2434daa
commit
22a1f59547
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@ -8,6 +8,7 @@
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* kind, whether express or implied.
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*/
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#include <dt-bindings/clock/r8a7790-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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@ -287,4 +288,321 @@ sdhi3: sd@ee160000 {
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cap-sd-highspeed;
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status = "disabled";
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};
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clocks {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* External root clock */
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extal_clk: extal_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overriden by the board. */
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clock-frequency = <0>;
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clock-output-names = "extal";
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};
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/* Special CPG clocks */
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cpg_clocks: cpg_clocks@e6150000 {
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compatible = "renesas,r8a7790-cpg-clocks",
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"renesas,rcar-gen2-cpg-clocks";
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reg = <0 0xe6150000 0 0x1000>;
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clocks = <&extal_clk>;
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#clock-cells = <1>;
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clock-output-names = "main", "pll0", "pll1", "pll3",
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"lb", "qspi", "sdh", "sd0", "sd1",
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"z";
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};
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/* Variable factor clocks */
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sd2_clk: sd2_clk@e6150078 {
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compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe6150078 0 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "sd2";
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};
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sd3_clk: sd3_clk@e615007c {
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compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe615007c 0 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "sd3";
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};
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mmc0_clk: mmc0_clk@e6150240 {
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compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe6150240 0 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "mmc0";
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};
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mmc1_clk: mmc1_clk@e6150244 {
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compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe6150244 0 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "mmc1";
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};
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ssp_clk: ssp_clk@e6150248 {
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compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe6150248 0 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "ssp";
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};
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ssprs_clk: ssprs_clk@e615024c {
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compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe615024c 0 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "ssprs";
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};
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/* Fixed factor clocks */
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pll1_div2_clk: pll1_div2_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <2>;
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clock-mult = <1>;
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clock-output-names = "pll1_div2";
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};
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z2_clk: z2_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <2>;
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clock-mult = <1>;
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clock-output-names = "z2";
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};
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zg_clk: zg_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <3>;
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clock-mult = <1>;
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clock-output-names = "zg";
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};
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zx_clk: zx_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <3>;
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clock-mult = <1>;
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clock-output-names = "zx";
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};
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zs_clk: zs_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <6>;
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clock-mult = <1>;
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clock-output-names = "zs";
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};
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hp_clk: hp_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <12>;
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clock-mult = <1>;
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clock-output-names = "hp";
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};
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i_clk: i_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <2>;
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clock-mult = <1>;
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clock-output-names = "i";
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};
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b_clk: b_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <12>;
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clock-mult = <1>;
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clock-output-names = "b";
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};
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p_clk: p_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <24>;
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clock-mult = <1>;
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clock-output-names = "p";
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};
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cl_clk: cl_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <48>;
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clock-mult = <1>;
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clock-output-names = "cl";
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};
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m2_clk: m2_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <8>;
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clock-mult = <1>;
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clock-output-names = "m2";
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};
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imp_clk: imp_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <4>;
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clock-mult = <1>;
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clock-output-names = "imp";
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};
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rclk_clk: rclk_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <(48 * 1024)>;
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clock-mult = <1>;
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clock-output-names = "rclk";
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};
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oscclk_clk: oscclk_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <(12 * 1024)>;
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clock-mult = <1>;
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clock-output-names = "oscclk";
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};
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zb3_clk: zb3_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
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#clock-cells = <0>;
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clock-div = <4>;
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clock-mult = <1>;
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clock-output-names = "zb3";
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};
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zb3d2_clk: zb3d2_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
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#clock-cells = <0>;
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clock-div = <8>;
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clock-mult = <1>;
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clock-output-names = "zb3d2";
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};
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ddr_clk: ddr_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
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#clock-cells = <0>;
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clock-div = <8>;
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clock-mult = <1>;
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clock-output-names = "ddr";
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};
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mp_clk: mp_clk {
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compatible = "fixed-factor-clock";
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-div = <15>;
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clock-mult = <1>;
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clock-output-names = "mp";
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};
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cp_clk: cp_clk {
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compatible = "fixed-factor-clock";
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clocks = <&extal_clk>;
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#clock-cells = <0>;
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clock-div = <2>;
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clock-mult = <1>;
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clock-output-names = "cp";
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};
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/* Gate clocks */
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mstp1_clks: mstp1_clks@e6150134 {
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compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
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clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
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<&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
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<&zs_clk>;
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#clock-cells = <1>;
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renesas,clock-indices = <
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R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2
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R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1
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R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_RT R8A7790_CLK_VSP1_SY
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>;
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clock-output-names =
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"tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
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"vsp1-du0", "vsp1-rt", "vsp1-sy";
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};
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mstp2_clks: mstp2_clks@e6150138 {
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compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
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clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
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<&mp_clk>;
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#clock-cells = <1>;
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renesas,clock-indices = <
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R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
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R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1 R8A7790_CLK_SCIFB2
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>;
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clock-output-names =
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"scifa2", "scifa1", "scifa0", "scifb0", "scifb1",
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"scifb2";
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};
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mstp3_clks: mstp3_clks@e615013c {
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compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
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clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>,
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<&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>,
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<&mmc0_clk>, <&rclk_clk>;
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#clock-cells = <1>;
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renesas,clock-indices = <
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R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
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R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0
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R8A7790_CLK_MMCIF0 R8A7790_CLK_CMT1
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>;
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clock-output-names =
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"tpu0", "mmcif1", "sdhi3", "sdhi2",
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"sdhi1", "sdhi0", "mmcif0", "cmt1";
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};
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mstp5_clks: mstp5_clks@e6150144 {
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compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
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clocks = <&extal_clk>, <&p_clk>;
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#clock-cells = <1>;
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renesas,clock-indices = <R8A7790_CLK_THERMAL R8A7790_CLK_PWM>;
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clock-output-names = "thermal", "pwm";
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};
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mstp7_clks: mstp7_clks@e615014c {
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compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
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clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
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<&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
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<&zx_clk>;
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#clock-cells = <1>;
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renesas,clock-indices = <
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R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
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R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
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R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
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R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
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>;
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clock-output-names =
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"ehci", "hsusb", "hscif1", "hscif0", "scif1",
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"scif0", "du2", "du1", "du0", "lvds1", "lvds0";
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};
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mstp8_clks: mstp8_clks@e6150990 {
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compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
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clocks = <&p_clk>;
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#clock-cells = <1>;
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renesas,clock-indices = <R8A7790_CLK_ETHER>;
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clock-output-names = "ether";
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};
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mstp9_clks: mstp9_clks@e6150994 {
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compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
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clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>;
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#clock-cells = <1>;
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renesas,clock-indices = <
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R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_I2C3
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R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0
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>;
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clock-output-names = "rcan1", "rcan0", "i2c3", "i2c2", "i2c1", "i2c0";
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};
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};
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};
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