mirror of https://gitee.com/openkylin/linux.git
[media] adv7604: Replace *_and_or() functions with *_clr_set()
The *_and_or() functions take an 'and' bitmask to be ANDed with the register value before ORing it with th 'or' bitmask. As the functions are used to mask and set bits selectively, this requires the caller to invert the 'and' bitmask and is thus error prone. Replace those functions with a *_clr_set() variant that takes a mask of bits to be cleared instead of a mask of bits to be kept. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
This commit is contained in:
Laurent Pinchart
Mauro Carvalho Chehab
parent
05cacb1767
commit
22d97e561d
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@ -429,9 +429,9 @@ static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
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return adv_smbus_write_byte_data(state, ADV7604_PAGE_IO, reg, val);
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}
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static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
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static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
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{
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return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
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return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
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}
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static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
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@ -462,9 +462,9 @@ static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
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return adv_smbus_write_byte_data(state, ADV7604_PAGE_CEC, reg, val);
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}
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static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
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static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
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{
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return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val);
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return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val);
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}
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static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
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@ -538,9 +538,9 @@ static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
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return adv_smbus_write_byte_data(state, ADV7604_PAGE_REP, reg, val);
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}
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static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
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static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
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{
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return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);
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return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val);
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}
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static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
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@ -629,9 +629,9 @@ static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
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return adv_smbus_write_byte_data(state, ADV7604_PAGE_HDMI, reg, val);
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}
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static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
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static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
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{
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return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val);
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return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val);
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}
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static inline int test_read(struct v4l2_subdev *sd, u8 reg)
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@ -667,9 +667,9 @@ static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
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return adv_smbus_write_byte_data(state, ADV7604_PAGE_CP, reg, val);
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}
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static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
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static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
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{
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return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);
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return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val);
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}
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static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
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@ -947,7 +947,7 @@ static int configure_predefined_video_timings(struct v4l2_subdev *sd,
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io_write(sd, 0x17, 0x5a);
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}
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/* disable embedded syncs for auto graphics mode */
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cp_write_and_or(sd, 0x81, 0xef, 0x00);
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cp_write_clr_set(sd, 0x81, 0x10, 0x00);
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cp_write(sd, 0x8f, 0x00);
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cp_write(sd, 0x90, 0x00);
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cp_write(sd, 0xa2, 0x00);
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@ -1005,7 +1005,7 @@ static void configure_custom_video_timings(struct v4l2_subdev *sd,
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io_write(sd, 0x00, 0x07); /* video std */
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io_write(sd, 0x01, 0x02); /* prim mode */
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/* enable embedded syncs for auto graphics mode */
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cp_write_and_or(sd, 0x81, 0xef, 0x10);
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cp_write_clr_set(sd, 0x81, 0x10, 0x10);
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/* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
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/* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
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@ -1115,21 +1115,21 @@ static void set_rgb_quantization_range(struct v4l2_subdev *sd)
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if (state->selected_input == ADV7604_PAD_VGA_RGB) {
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/* Receiving analog RGB signal
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* Set RGB full range (0-255) */
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io_write_and_or(sd, 0x02, 0x0f, 0x10);
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io_write_clr_set(sd, 0x02, 0xf0, 0x10);
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break;
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}
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if (state->selected_input == ADV7604_PAD_VGA_COMP) {
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/* Receiving analog YPbPr signal
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* Set automode */
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io_write_and_or(sd, 0x02, 0x0f, 0xf0);
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io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
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break;
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}
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if (hdmi_signal) {
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/* Receiving HDMI signal
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* Set automode */
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io_write_and_or(sd, 0x02, 0x0f, 0xf0);
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io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
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break;
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}
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@ -1138,10 +1138,10 @@ static void set_rgb_quantization_range(struct v4l2_subdev *sd)
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* input format (CE/IT) in automatic mode */
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if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
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/* RGB limited range (16-235) */
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io_write_and_or(sd, 0x02, 0x0f, 0x00);
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io_write_clr_set(sd, 0x02, 0xf0, 0x00);
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} else {
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/* RGB full range (0-255) */
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io_write_and_or(sd, 0x02, 0x0f, 0x10);
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io_write_clr_set(sd, 0x02, 0xf0, 0x10);
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if (is_digital_input(sd) && rgb_output) {
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adv7604_set_offset(sd, false, 0x40, 0x40, 0x40);
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@ -1154,23 +1154,23 @@ static void set_rgb_quantization_range(struct v4l2_subdev *sd)
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case V4L2_DV_RGB_RANGE_LIMITED:
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if (state->selected_input == ADV7604_PAD_VGA_COMP) {
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/* YCrCb limited range (16-235) */
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io_write_and_or(sd, 0x02, 0x0f, 0x20);
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io_write_clr_set(sd, 0x02, 0xf0, 0x20);
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break;
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}
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/* RGB limited range (16-235) */
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io_write_and_or(sd, 0x02, 0x0f, 0x00);
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io_write_clr_set(sd, 0x02, 0xf0, 0x00);
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break;
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case V4L2_DV_RGB_RANGE_FULL:
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if (state->selected_input == ADV7604_PAD_VGA_COMP) {
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/* YCrCb full range (0-255) */
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io_write_and_or(sd, 0x02, 0x0f, 0x60);
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io_write_clr_set(sd, 0x02, 0xf0, 0x60);
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break;
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}
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/* RGB full range (0-255) */
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io_write_and_or(sd, 0x02, 0x0f, 0x10);
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io_write_clr_set(sd, 0x02, 0xf0, 0x10);
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if (is_analog_input(sd) || hdmi_signal)
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break;
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@ -1222,7 +1222,7 @@ static int adv7604_s_ctrl(struct v4l2_ctrl *ctrl)
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case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
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/* Use the default blue color for free running mode,
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or supply your own. */
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cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));
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cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2);
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return 0;
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case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
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cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
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@ -1605,11 +1605,11 @@ static int adv7604_query_dv_timings(struct v4l2_subdev *sd,
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v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
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/* TODO restart STDI for Sync Channel 2 */
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/* enter one-shot mode */
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cp_write_and_or(sd, 0x86, 0xf9, 0x00);
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cp_write_clr_set(sd, 0x86, 0x06, 0x00);
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/* trigger STDI restart */
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cp_write_and_or(sd, 0x86, 0xf9, 0x04);
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cp_write_clr_set(sd, 0x86, 0x06, 0x04);
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/* reset to continuous mode */
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cp_write_and_or(sd, 0x86, 0xf9, 0x02);
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cp_write_clr_set(sd, 0x86, 0x06, 0x02);
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state->restart_stdi_once = false;
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return -ENOLINK;
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}
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@ -1668,7 +1668,7 @@ static int adv7604_s_dv_timings(struct v4l2_subdev *sd,
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state->timings = *timings;
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cp_write_and_or(sd, 0x91, 0xbf, bt->interlaced ? 0x40 : 0x00);
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cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00);
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/* Use prim_mode and vid_std when available */
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err = configure_predefined_video_timings(sd, timings);
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@ -1712,10 +1712,10 @@ static void enable_input(struct v4l2_subdev *sd)
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if (is_analog_input(sd)) {
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io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
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} else if (is_digital_input(sd)) {
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hdmi_write_and_or(sd, 0x00, 0xfc, state->selected_input);
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hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input);
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state->info->set_termination(sd, true);
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io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
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hdmi_write_and_or(sd, 0x1a, 0xef, 0x00); /* Unmute audio */
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hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */
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} else {
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v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
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__func__, state->selected_input);
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@ -1726,7 +1726,7 @@ static void disable_input(struct v4l2_subdev *sd)
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{
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struct adv7604_state *state = to_state(sd);
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hdmi_write_and_or(sd, 0x1a, 0xef, 0x10); /* Mute audio */
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hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */
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msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */
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io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
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state->info->set_termination(sd, false);
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@ -1857,12 +1857,12 @@ static void adv7604_setup_format(struct adv7604_state *state)
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{
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struct v4l2_subdev *sd = &state->sd;
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io_write_and_or(sd, 0x02, 0xfd,
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io_write_clr_set(sd, 0x02, 0x02,
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state->format->rgb_out ? ADV7604_RGB_OUT : 0);
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io_write(sd, 0x03, state->format->op_format_sel |
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state->pdata.op_format_mode_sel);
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io_write_and_or(sd, 0x04, 0x1f, adv7604_op_ch_sel(state));
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io_write_and_or(sd, 0x05, 0xfe,
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io_write_clr_set(sd, 0x04, 0xe0, adv7604_op_ch_sel(state));
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io_write_clr_set(sd, 0x05, 0x01,
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state->format->swap_cb_cr ? ADV7604_OP_SWAP_CB_CR : 0);
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}
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@ -2059,7 +2059,7 @@ static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
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/* Disable hotplug and I2C access to EDID RAM from DDC port */
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state->edid.present &= ~(1 << edid->pad);
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v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&state->edid.present);
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rep_write_and_or(sd, info->edid_enable_reg, 0xf0, state->edid.present);
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rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
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/* Fall back to a 16:9 aspect ratio */
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state->aspect_ratio.numerator = 16;
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@ -2083,7 +2083,7 @@ static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
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/* Disable hotplug and I2C access to EDID RAM from DDC port */
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cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
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v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&tmp);
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rep_write_and_or(sd, info->edid_enable_reg, 0xf0, 0x00);
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rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00);
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spa_loc = get_edid_spa_location(edid->edid);
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if (spa_loc < 0)
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@ -2112,10 +2112,10 @@ static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
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if (info->type == ADV7604) {
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rep_write(sd, 0x76, spa_loc & 0xff);
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rep_write_and_or(sd, 0x77, 0xbf, (spa_loc & 0x100) >> 2);
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rep_write_clr_set(sd, 0x77, 0x40, (spa_loc & 0x100) >> 2);
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} else {
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/* FIXME: Where is the SPA location LSB register ? */
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rep_write_and_or(sd, 0x71, 0xfe, (spa_loc & 0x100) >> 8);
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rep_write_clr_set(sd, 0x71, 0x01, (spa_loc & 0x100) >> 8);
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}
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edid->edid[spa_loc] = state->spa_port_a[0];
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@ -2135,7 +2135,7 @@ static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
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/* adv7604 calculates the checksums and enables I2C access to internal
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EDID RAM from DDC port. */
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rep_write_and_or(sd, info->edid_enable_reg, 0xf0, state->edid.present);
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rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
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for (i = 0; i < 1000; i++) {
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if (rep_read(sd, info->edid_status_reg) & state->edid.present)
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@ -2431,11 +2431,11 @@ static int adv7604_core_init(struct v4l2_subdev *sd)
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cp_write(sd, 0xcf, 0x01); /* Power down macrovision */
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/* video format */
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io_write_and_or(sd, 0x02, 0xf0,
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io_write_clr_set(sd, 0x02, 0x0f,
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pdata->alt_gamma << 3 |
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pdata->op_656_range << 2 |
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pdata->alt_data_sat << 0);
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io_write_and_or(sd, 0x05, 0xf1, pdata->blank_data << 3 |
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io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 |
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pdata->insert_av_codes << 2 |
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pdata->replicate_av_codes << 1);
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adv7604_setup_format(state);
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@ -2460,16 +2460,16 @@ static int adv7604_core_init(struct v4l2_subdev *sd)
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for digital formats */
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/* HDMI audio */
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hdmi_write_and_or(sd, 0x15, 0xfc, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */
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hdmi_write_and_or(sd, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */
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hdmi_write_and_or(sd, 0x68, 0xf9, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */
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hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */
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hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */
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hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */
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/* TODO from platform data */
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afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
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if (adv7604_has_afe(state)) {
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afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
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io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);
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io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4);
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}
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/* interrupts */
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