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DTS changes to enable Ethernet on the Gemini boards. 

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Merge tag 'gemini-dts-update-3' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into next/dt

Pull "DTS changes to enable Ethernet on the Gemini boards" from Linus Walleij:

I realize it's late. Like really late. But Dmiller merged the ethernet
bindings and the driver for Gemini ethernet, and Gemini is all about
networking.

So for a late merge consideration here are the two patches giving
ethernet on Gemini, on top of what is already merged.

* tag 'gemini-dts-update-3' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik:
  ARM: dts: Add ethernet to a bunch of platforms
  ARM: dts: Add ethernet to the Gemini SoC
This commit is contained in:
Arnd Bergmann 2018-01-19 16:09:49 +01:00
parent 1ebf790bef 95220046a6
commit 232e9d4c95
6 changed files with 205 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

62
arch/arm/boot/dts/gemini-dlink-dns-313.dts
View File

@ -214,6 +214,56 @@ mux {
groups = "gpio1dgrp";
};
};
pinctrl-gmii {
mux {
function = "gmii";
groups = "gmii_gmac0_grp";
};
/*
* In the vendor Linux tree, these values are set for the C3
* version of the SL3512 ASIC with the comment "benson suggest"
*/
conf0 {
pins = "R8 GMAC0 RXDV", "U11 GMAC1 RXDV";
skew-delay = <0>;
};
conf1 {
pins = "T8 GMAC0 RXC";
skew-delay = <10>;
};
conf2 {
pins = "T11 GMAC1 RXC";
skew-delay = <15>;
};
conf3 {
pins = "P8 GMAC0 TXEN", "V11 GMAC1 TXEN";
skew-delay = <7>;
};
conf4 {
pins = "V7 GMAC0 TXC", "P10 GMAC1 TXC";
skew-delay = <10>;
};
conf5 {
/* The data lines all have default skew */
pins = "U8 GMAC0 RXD0", "V8 GMAC0 RXD1",
"P9 GMAC0 RXD2", "R9 GMAC0 RXD3",
"R11 GMAC1 RXD0", "P11 GMAC1 RXD1",
"V12 GMAC1 RXD2", "U12 GMAC1 RXD3",
"R10 GMAC1 TXD0", "T10 GMAC1 TXD1",
"U10 GMAC1 TXD2", "V10 GMAC1 TXD3";
skew-delay = <7>;
};
conf6 {
pins = "U7 GMAC0 TXD0", "T7 GMAC0 TXD1",
"R7 GMAC0 TXD2", "P7 GMAC0 TXD3";
skew-delay = <5>;
};
/* Set up drive strength on GMAC0 to 16 mA */
conf7 {
groups = "gmii_gmac0_grp";
drive-strength = <16>;
};
};
};
};
@ -234,6 +284,18 @@ gpio1: gpio@4e000000 {
pinctrl-0 = <&gpio1_default_pins>;
};
ethernet@60000000 {
status = "okay";
ethernet-port@0 {
phy-mode = "rgmii";
phy-handle = <&phy0>;
};
ethernet-port@1 {
/* Not used in this platform */
};
};
ata@63000000 {
status = "okay";
};

56
arch/arm/boot/dts/gemini-nas4220b.dts
View File

@ -129,6 +129,50 @@ mux {
groups = "gpio1dgrp";
};
};
pinctrl-gmii {
mux {
function = "gmii";
groups = "gmii_gmac0_grp";
};
/* Settings come from OpenWRT */
conf0 {
pins = "R8 GMAC0 RXDV", "U11 GMAC1 RXDV";
skew-delay = <0>;
};
conf1 {
pins = "T8 GMAC0 RXC", "T11 GMAC1 RXC";
skew-delay = <15>;
};
conf2 {
pins = "P8 GMAC0 TXEN", "V11 GMAC1 TXEN";
skew-delay = <7>;
};
conf3 {
pins = "V7 GMAC0 TXC";
skew-delay = <11>;
};
conf4 {
pins = "P10 GMAC1 TXC";
skew-delay = <10>;
};
conf5 {
/* The data lines all have default skew */
pins = "U8 GMAC0 RXD0", "V8 GMAC0 RXD1",
"P9 GMAC0 RXD2", "R9 GMAC0 RXD3",
"U7 GMAC0 TXD0", "T7 GMAC0 TXD1",
"R7 GMAC0 TXD2", "P7 GMAC0 TXD3",
"R11 GMAC1 RXD0", "P11 GMAC1 RXD1",
"V12 GMAC1 RXD2", "U12 GMAC1 RXD3",
"R10 GMAC1 TXD0", "T10 GMAC1 TXD1",
"U10 GMAC1 TXD2", "V10 GMAC1 TXD3";
skew-delay = <7>;
};
/* Set up drive strength on GMAC0 to 16 mA */
conf6 {
groups = "gmii_gmac0_grp";
drive-strength = <16>;
};
};
};
};
@ -143,6 +187,18 @@ gpio1: gpio@4e000000 {
pinctrl-0 = <&gpio1_default_pins>;
};
ethernet@60000000 {
status = "okay";
ethernet-port@0 {
phy-mode = "rgmii";
phy-handle = <&phy0>;
};
ethernet-port@1 {
/* Not used in this platform */
};
};
ata@63000000 {
status = "okay";
};

12
arch/arm/boot/dts/gemini-rut1xx.dts
View File

@ -114,5 +114,17 @@ gpio1: gpio@4e000000 {
pinctrl-names = "default";
pinctrl-0 = <&gpio1_default_pins>;
};
ethernet@60000000 {
status = "okay";
ethernet-port@0 {
phy-mode = "rgmii";
phy-handle = <&phy0>;
};
ethernet-port@1 {
/* Not used in this platform */
};
};
};
};

12
arch/arm/boot/dts/gemini-wbd111.dts
View File

@ -160,5 +160,17 @@ pci@50000000 {
<0x6000 0 0 3 &pci_intc 1>,
<0x6000 0 0 4 &pci_intc 2>;
};
ethernet@60000000 {
status = "okay";
ethernet-port@0 {
phy-mode = "rgmii";
phy-handle = <&phy0>;
};
ethernet-port@1 {
/* Not used in this platform */
};
};
};
};

20
arch/arm/boot/dts/gemini-wbd222.dts
View File

@ -136,6 +136,13 @@ mux {
"gpio0bgrp";
};
};
pinctrl-gmii {
/* This platform use both the ethernet ports */
mux {
function = "gmii";
groups = "gmii_gmac0_grp", "gmii_gmac1_grp";
};
};
};
};
@ -165,5 +172,18 @@ pci@50000000 {
<0x6000 0 0 3 &pci_intc 1>,
<0x6000 0 0 4 &pci_intc 2>;
};
ethernet@60000000 {
status = "okay";
ethernet-port@0 {
phy-mode = "rgmii";
phy-handle = <&phy0>;
};
ethernet-port@1 {
phy-mode = "rgmii";
phy-handle = <&phy1>;
};
};
};
};

44
arch/arm/boot/dts/gemini.dtsi
View File

@ -114,9 +114,16 @@ mux {
};
};
gmii_default_pins: pinctrl-gmii {
/*
* Only activate GMAC0 by default since
* GMAC1 will overlap with 8 GPIO lines
* gpio2a, gpio2b. Overlay groups with
* "gmii_gmac0_grp", "gmii_gmac1_grp" for
* both ethernet interfaces.
*/
mux {
function = "gmii";
groups = "gmiigrp";
groups = "gmii_gmac0_grp";
};
};
pci_default_pins: pinctrl-pci {
@ -316,6 +323,41 @@ pci_intc: interrupt-controller {
};
};
ethernet@60000000 {
compatible = "cortina,gemini-ethernet";
reg = <0x60000000 0x4000>, /* Global registers, queue */
<0x60004000 0x2000>, /* V-bit */
<0x60006000 0x2000>; /* A-bit */
pinctrl-names = "default";
pinctrl-0 = <&gmii_default_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges;
gmac0: ethernet-port@0 {
compatible = "cortina,gemini-ethernet-port";
reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */
<0x6000a000 0x2000>; /* Port 0 GMAC */
interrupt-parent = <&intcon>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
resets = <&syscon GEMINI_RESET_GMAC0>;
clocks = <&syscon GEMINI_CLK_GATE_GMAC0>;
clock-names = "PCLK";
};
gmac1: ethernet-port@1 {
compatible = "cortina,gemini-ethernet-port";
reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */
<0x6000e000 0x2000>; /* Port 1 GMAC */
interrupt-parent = <&intcon>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
resets = <&syscon GEMINI_RESET_GMAC1>;
clocks = <&syscon GEMINI_CLK_GATE_GMAC1>;
clock-names = "PCLK";
};
};
ata@63000000 {
compatible = "cortina,gemini-pata", "faraday,ftide010";
reg = <0x63000000 0x1000>;