mirror of https://gitee.com/openkylin/linux.git
[PATCH] serial uartlite driver
Add a driver for the Xilinx uartlite serial controller used in boards with the PPC405 core in the Xilinx V2P/V4 fpgas. The hardware is very simple (baudrate/start/stopbits fixed and no break support). See the datasheet for details: http://www.xilinx.com/bvdocs/ipcenter/data_sheet/opb_uartlite.pdf See http://thread.gmane.org/gmane.linux.serial/1237/ for the email thread. Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk> Acked-by: Olof Johansson <olof@lixom.net> Cc: Russell King <rmk@arm.linux.org.uk> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Peter Korsgaard
Linus Torvalds
parent
57881dd9df
commit
238b8721a5
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@ -3454,6 +3454,12 @@ W: http://oss.sgi.com/projects/xfs
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T: git git://oss.sgi.com:8090/xfs/xfs-2.6
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S: Supported
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XILINX UARTLITE SERIAL DRIVER
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P: Peter Korsgaard
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M: jacmet@sunsite.dk
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L: linux-serial@vger.kernel.org
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S: Maintained
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X86 3-LEVEL PAGING (PAE) SUPPORT
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P: Ingo Molnar
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M: mingo@redhat.com
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@ -511,6 +511,25 @@ config SERIAL_IMX_CONSOLE
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your boot loader (lilo or loadlin) about how to pass options to the
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kernel at boot time.)
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config SERIAL_UARTLITE
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tristate "Xilinx uartlite serial port support"
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depends on PPC32
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select SERIAL_CORE
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help
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Say Y here if you want to use the Xilinx uartlite serial controller.
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To compile this driver as a module, choose M here: the
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module will be called uartlite.ko.
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config SERIAL_UARTLITE_CONSOLE
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bool "Support for console on Xilinx uartlite serial port"
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depends on SERIAL_UARTLITE=y
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select SERIAL_CORE_CONSOLE
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help
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Say Y here if you wish to use a Xilinx uartlite as the system
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console (the system console is the device which receives all kernel
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messages and warnings and which allows logins in single user mode).
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config SERIAL_SUNCORE
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bool
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depends on SPARC
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@ -55,4 +55,5 @@ obj-$(CONFIG_SERIAL_VR41XX) += vr41xx_siu.o
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obj-$(CONFIG_SERIAL_SGI_IOC4) += ioc4_serial.o
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obj-$(CONFIG_SERIAL_SGI_IOC3) += ioc3_serial.o
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obj-$(CONFIG_SERIAL_ATMEL) += atmel_serial.o
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obj-$(CONFIG_SERIAL_UARTLITE) += uartlite.o
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obj-$(CONFIG_SERIAL_NETX) += netx-serial.o
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@ -0,0 +1,505 @@
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/*
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* uartlite.c: Serial driver for Xilinx uartlite serial controller
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*
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* Peter Korsgaard <jacmet@sunsite.dk>
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <linux/platform_device.h>
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#include <linux/module.h>
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#include <linux/console.h>
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#include <linux/serial.h>
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#include <linux/serial_core.h>
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#include <linux/tty.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <asm/io.h>
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#define ULITE_MAJOR 204
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#define ULITE_MINOR 187
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#define ULITE_NR_UARTS 4
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/* For register details see datasheet:
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http://www.xilinx.com/bvdocs/ipcenter/data_sheet/opb_uartlite.pdf
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*/
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#define ULITE_RX 0x00
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#define ULITE_TX 0x04
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#define ULITE_STATUS 0x08
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#define ULITE_CONTROL 0x0c
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#define ULITE_REGION 16
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#define ULITE_STATUS_RXVALID 0x01
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#define ULITE_STATUS_RXFULL 0x02
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#define ULITE_STATUS_TXEMPTY 0x04
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#define ULITE_STATUS_TXFULL 0x08
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#define ULITE_STATUS_IE 0x10
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#define ULITE_STATUS_OVERRUN 0x20
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#define ULITE_STATUS_FRAME 0x40
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#define ULITE_STATUS_PARITY 0x80
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#define ULITE_CONTROL_RST_TX 0x01
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#define ULITE_CONTROL_RST_RX 0x02
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#define ULITE_CONTROL_IE 0x10
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static struct uart_port ports[ULITE_NR_UARTS];
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static int ulite_receive(struct uart_port *port, int stat)
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{
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struct tty_struct *tty = port->info->tty;
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unsigned char ch = 0;
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char flag = TTY_NORMAL;
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if ((stat & (ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN
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| ULITE_STATUS_FRAME)) == 0)
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return 0;
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/* stats */
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if (stat & ULITE_STATUS_RXVALID) {
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port->icount.rx++;
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ch = readb(port->membase + ULITE_RX);
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if (stat & ULITE_STATUS_PARITY)
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port->icount.parity++;
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}
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if (stat & ULITE_STATUS_OVERRUN)
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port->icount.overrun++;
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if (stat & ULITE_STATUS_FRAME)
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port->icount.frame++;
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/* drop byte with parity error if IGNPAR specificed */
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if (stat & port->ignore_status_mask & ULITE_STATUS_PARITY)
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stat &= ~ULITE_STATUS_RXVALID;
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stat &= port->read_status_mask;
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if (stat & ULITE_STATUS_PARITY)
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flag = TTY_PARITY;
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stat &= ~port->ignore_status_mask;
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if (stat & ULITE_STATUS_RXVALID)
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tty_insert_flip_char(tty, ch, flag);
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if (stat & ULITE_STATUS_FRAME)
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tty_insert_flip_char(tty, 0, TTY_FRAME);
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if (stat & ULITE_STATUS_OVERRUN)
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tty_insert_flip_char(tty, 0, TTY_OVERRUN);
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return 1;
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}
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static int ulite_transmit(struct uart_port *port, int stat)
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{
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struct circ_buf *xmit = &port->info->xmit;
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if (stat & ULITE_STATUS_TXFULL)
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return 0;
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if (port->x_char) {
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writeb(port->x_char, port->membase + ULITE_TX);
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port->x_char = 0;
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port->icount.tx++;
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return 1;
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}
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if (uart_circ_empty(xmit) || uart_tx_stopped(port))
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return 0;
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writeb(xmit->buf[xmit->tail], port->membase + ULITE_TX);
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE-1);
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port->icount.tx++;
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/* wake up */
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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uart_write_wakeup(port);
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return 1;
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}
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static irqreturn_t ulite_isr(int irq, void *dev_id)
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{
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struct uart_port *port = (struct uart_port *)dev_id;
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int busy;
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do {
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int stat = readb(port->membase + ULITE_STATUS);
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busy = ulite_receive(port, stat);
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busy |= ulite_transmit(port, stat);
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} while (busy);
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tty_flip_buffer_push(port->info->tty);
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return IRQ_HANDLED;
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}
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static unsigned int ulite_tx_empty(struct uart_port *port)
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{
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unsigned long flags;
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unsigned int ret;
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spin_lock_irqsave(&port->lock, flags);
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ret = readb(port->membase + ULITE_STATUS);
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spin_unlock_irqrestore(&port->lock, flags);
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return ret & ULITE_STATUS_TXEMPTY ? TIOCSER_TEMT : 0;
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}
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static unsigned int ulite_get_mctrl(struct uart_port *port)
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{
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return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
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}
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static void ulite_set_mctrl(struct uart_port *port, unsigned int mctrl)
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{
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/* N/A */
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}
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static void ulite_stop_tx(struct uart_port *port)
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{
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/* N/A */
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}
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static void ulite_start_tx(struct uart_port *port)
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{
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ulite_transmit(port, readb(port->membase + ULITE_STATUS));
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}
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static void ulite_stop_rx(struct uart_port *port)
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{
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/* don't forward any more data (like !CREAD) */
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port->ignore_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY
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| ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
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}
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static void ulite_enable_ms(struct uart_port *port)
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{
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/* N/A */
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}
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static void ulite_break_ctl(struct uart_port *port, int ctl)
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{
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/* N/A */
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}
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static int ulite_startup(struct uart_port *port)
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{
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int ret;
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ret = request_irq(port->irq, ulite_isr,
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IRQF_DISABLED | IRQF_SAMPLE_RANDOM, "uartlite", port);
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if (ret)
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return ret;
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writeb(ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX,
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port->membase + ULITE_CONTROL);
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writeb(ULITE_CONTROL_IE, port->membase + ULITE_CONTROL);
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return 0;
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}
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static void ulite_shutdown(struct uart_port *port)
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{
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writeb(0, port->membase + ULITE_CONTROL);
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readb(port->membase + ULITE_CONTROL); /* dummy */
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free_irq(port->irq, port);
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}
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static void ulite_set_termios(struct uart_port *port, struct termios *termios,
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struct termios *old)
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{
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unsigned long flags;
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unsigned int baud;
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spin_lock_irqsave(&port->lock, flags);
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port->read_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN
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| ULITE_STATUS_TXFULL;
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if (termios->c_iflag & INPCK)
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port->read_status_mask |=
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ULITE_STATUS_PARITY | ULITE_STATUS_FRAME;
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port->ignore_status_mask = 0;
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if (termios->c_iflag & IGNPAR)
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port->ignore_status_mask |= ULITE_STATUS_PARITY
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| ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
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/* ignore all characters if CREAD is not set */
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if ((termios->c_cflag & CREAD) == 0)
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port->ignore_status_mask |=
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ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY
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| ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
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/* update timeout */
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baud = uart_get_baud_rate(port, termios, old, 0, 460800);
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uart_update_timeout(port, termios->c_cflag, baud);
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spin_unlock_irqrestore(&port->lock, flags);
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}
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static const char *ulite_type(struct uart_port *port)
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{
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return port->type == PORT_UARTLITE ? "uartlite" : NULL;
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}
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static void ulite_release_port(struct uart_port *port)
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{
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release_mem_region(port->mapbase, ULITE_REGION);
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iounmap(port->membase);
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port->membase = 0;
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}
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static int ulite_request_port(struct uart_port *port)
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{
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if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) {
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dev_err(port->dev, "Memory region busy\n");
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return -EBUSY;
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}
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port->membase = ioremap(port->mapbase, ULITE_REGION);
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if (!port->membase) {
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dev_err(port->dev, "Unable to map registers\n");
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release_mem_region(port->mapbase, ULITE_REGION);
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return -EBUSY;
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}
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return 0;
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}
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static void ulite_config_port(struct uart_port *port, int flags)
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{
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ulite_request_port(port);
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port->type = PORT_UARTLITE;
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}
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static int ulite_verify_port(struct uart_port *port, struct serial_struct *ser)
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{
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/* we don't want the core code to modify any port params */
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return -EINVAL;
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}
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static struct uart_ops ulite_ops = {
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.tx_empty = ulite_tx_empty,
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.set_mctrl = ulite_set_mctrl,
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.get_mctrl = ulite_get_mctrl,
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.stop_tx = ulite_stop_tx,
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.start_tx = ulite_start_tx,
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.stop_rx = ulite_stop_rx,
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.enable_ms = ulite_enable_ms,
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.break_ctl = ulite_break_ctl,
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.startup = ulite_startup,
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.shutdown = ulite_shutdown,
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.set_termios = ulite_set_termios,
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.type = ulite_type,
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.release_port = ulite_release_port,
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.request_port = ulite_request_port,
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.config_port = ulite_config_port,
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.verify_port = ulite_verify_port
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};
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#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
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static void ulite_console_wait_tx(struct uart_port *port)
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{
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int i;
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/* wait up to 10ms for the character(s) to be sent */
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for (i = 0; i < 10000; i++) {
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if (readb(port->membase + ULITE_STATUS) & ULITE_STATUS_TXEMPTY)
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break;
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udelay(1);
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}
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}
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static void ulite_console_putchar(struct uart_port *port, int ch)
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{
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ulite_console_wait_tx(port);
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writeb(ch, port->membase + ULITE_TX);
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}
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static void ulite_console_write(struct console *co, const char *s,
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unsigned int count)
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{
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struct uart_port *port = &ports[co->index];
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unsigned long flags;
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unsigned int ier;
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int locked = 1;
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if (oops_in_progress) {
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locked = spin_trylock_irqsave(&port->lock, flags);
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} else
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spin_lock_irqsave(&port->lock, flags);
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/* save and disable interrupt */
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ier = readb(port->membase + ULITE_STATUS) & ULITE_STATUS_IE;
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writeb(0, port->membase + ULITE_CONTROL);
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uart_console_write(port, s, count, ulite_console_putchar);
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ulite_console_wait_tx(port);
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/* restore interrupt state */
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if (ier)
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writeb(ULITE_CONTROL_IE, port->membase + ULITE_CONTROL);
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if (locked)
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spin_unlock_irqrestore(&port->lock, flags);
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}
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static int __init ulite_console_setup(struct console *co, char *options)
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{
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struct uart_port *port;
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int baud = 9600;
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int bits = 8;
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int parity = 'n';
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int flow = 'n';
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if (co->index < 0 || co->index >= ULITE_NR_UARTS)
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return -EINVAL;
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port = &ports[co->index];
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/* not initialized yet? */
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if (!port->membase)
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return -ENODEV;
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if (options)
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uart_parse_options(options, &baud, &parity, &bits, &flow);
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return uart_set_options(port, co, baud, parity, bits, flow);
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}
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static struct uart_driver ulite_uart_driver;
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static struct console ulite_console = {
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.name = "ttyUL",
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.write = ulite_console_write,
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.device = uart_console_device,
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.setup = ulite_console_setup,
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.flags = CON_PRINTBUFFER,
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.index = -1, /* Specified on the cmdline (e.g. console=ttyUL0 ) */
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.data = &ulite_uart_driver,
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};
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static int __init ulite_console_init(void)
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{
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register_console(&ulite_console);
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return 0;
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}
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console_initcall(ulite_console_init);
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#endif /* CONFIG_SERIAL_UARTLITE_CONSOLE */
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static struct uart_driver ulite_uart_driver = {
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.owner = THIS_MODULE,
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.driver_name = "uartlite",
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.dev_name = "ttyUL",
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.major = ULITE_MAJOR,
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.minor = ULITE_MINOR,
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.nr = ULITE_NR_UARTS,
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#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
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.cons = &ulite_console,
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#endif
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};
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static int __devinit ulite_probe(struct platform_device *pdev)
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{
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struct resource *res, *res2;
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struct uart_port *port;
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if (pdev->id < 0 || pdev->id >= ULITE_NR_UARTS)
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return -EINVAL;
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|
||||
if (ports[pdev->id].membase)
|
||||
return -EBUSY;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res)
|
||||
return -ENODEV;
|
||||
|
||||
res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
||||
if (!res2)
|
||||
return -ENODEV;
|
||||
|
||||
port = &ports[pdev->id];
|
||||
|
||||
port->fifosize = 16;
|
||||
port->regshift = 2;
|
||||
port->iotype = UPIO_MEM;
|
||||
port->iobase = 1; /* mark port in use */
|
||||
port->mapbase = res->start;
|
||||
port->membase = 0;
|
||||
port->ops = &ulite_ops;
|
||||
port->irq = res2->start;
|
||||
port->flags = UPF_BOOT_AUTOCONF;
|
||||
port->dev = &pdev->dev;
|
||||
port->type = PORT_UNKNOWN;
|
||||
port->line = pdev->id;
|
||||
|
||||
uart_add_one_port(&ulite_uart_driver, port);
|
||||
platform_set_drvdata(pdev, port);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ulite_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct uart_port *port = platform_get_drvdata(pdev);
|
||||
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
|
||||
if (port)
|
||||
uart_remove_one_port(&ulite_uart_driver, port);
|
||||
|
||||
/* mark port as free */
|
||||
port->membase = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver ulite_platform_driver = {
|
||||
.probe = ulite_probe,
|
||||
.remove = ulite_remove,
|
||||
.driver = {
|
||||
.owner = THIS_MODULE,
|
||||
.name = "uartlite",
|
||||
},
|
||||
};
|
||||
|
||||
int __init ulite_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = uart_register_driver(&ulite_uart_driver);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = platform_driver_register(&ulite_platform_driver);
|
||||
if (ret)
|
||||
uart_unregister_driver(&ulite_uart_driver);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void __exit ulite_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&ulite_platform_driver);
|
||||
uart_unregister_driver(&ulite_uart_driver);
|
||||
}
|
||||
|
||||
module_init(ulite_init);
|
||||
module_exit(ulite_exit);
|
||||
|
||||
MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
|
||||
MODULE_DESCRIPTION("Xilinx uartlite serial driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -132,6 +132,8 @@
|
|||
|
||||
#define PORT_S3C2412 73
|
||||
|
||||
/* Xilinx uartlite */
|
||||
#define PORT_UARTLITE 74
|
||||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue