mirror of https://gitee.com/openkylin/linux.git
isci: fix interrupt disable
There is a (dubious?) lost irq workaround in sci_controller_isr() that effectively nullifies attempts to disable interrupts. Until the workaround can be re-evaluated add some infrastructure to prevent the interrupt handler from inadvertantly re-enabling interrupts. The failure mode was interrupts continuing to run after the driver had been removed and its iomappings torn down. Reported-by: Jacek Danecki <jacek.danecki@intel.com> Tested-by: Jacek Danecki <jacek.danecki@intel.com> [richard: clear remaining interrupts at the end of reset] Acked-by: Richard Boyd <richard.g.boyd@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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50a92d9314
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2396a2650a
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@ -192,22 +192,27 @@ static bool sci_controller_completion_queue_has_entries(struct isci_host *ihost)
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static bool sci_controller_isr(struct isci_host *ihost)
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static bool sci_controller_isr(struct isci_host *ihost)
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{
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{
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if (sci_controller_completion_queue_has_entries(ihost)) {
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if (sci_controller_completion_queue_has_entries(ihost))
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return true;
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return true;
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} else {
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/*
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* we have a spurious interrupt it could be that we have already
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* emptied the completion queue from a previous interrupt */
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writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status);
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/*
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/* we have a spurious interrupt it could be that we have already
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* There is a race in the hardware that could cause us not to be notified
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* emptied the completion queue from a previous interrupt
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* of an interrupt completion if we do not take this step. We will mask
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* FIXME: really!?
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* then unmask the interrupts so if there is another interrupt pending
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*/
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* the clearing of the interrupt source we get the next interrupt message. */
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writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status);
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/* There is a race in the hardware that could cause us not to be
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* notified of an interrupt completion if we do not take this
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* step. We will mask then unmask the interrupts so if there is
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* another interrupt pending the clearing of the interrupt
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* source we get the next interrupt message.
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*/
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spin_lock(&ihost->scic_lock);
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if (test_bit(IHOST_IRQ_ENABLED, &ihost->flags)) {
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writel(0xFF000000, &ihost->smu_registers->interrupt_mask);
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writel(0xFF000000, &ihost->smu_registers->interrupt_mask);
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writel(0, &ihost->smu_registers->interrupt_mask);
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writel(0, &ihost->smu_registers->interrupt_mask);
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}
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}
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spin_unlock(&ihost->scic_lock);
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return false;
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return false;
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}
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}
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@ -698,14 +703,15 @@ static u32 sci_controller_get_suggested_start_timeout(struct isci_host *ihost)
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static void sci_controller_enable_interrupts(struct isci_host *ihost)
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static void sci_controller_enable_interrupts(struct isci_host *ihost)
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{
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{
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BUG_ON(ihost->smu_registers == NULL);
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set_bit(IHOST_IRQ_ENABLED, &ihost->flags);
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writel(0, &ihost->smu_registers->interrupt_mask);
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writel(0, &ihost->smu_registers->interrupt_mask);
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}
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}
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void sci_controller_disable_interrupts(struct isci_host *ihost)
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void sci_controller_disable_interrupts(struct isci_host *ihost)
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{
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{
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BUG_ON(ihost->smu_registers == NULL);
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clear_bit(IHOST_IRQ_ENABLED, &ihost->flags);
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writel(0xffffffff, &ihost->smu_registers->interrupt_mask);
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writel(0xffffffff, &ihost->smu_registers->interrupt_mask);
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readl(&ihost->smu_registers->interrupt_mask); /* flush */
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}
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}
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static void sci_controller_enable_port_task_scheduler(struct isci_host *ihost)
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static void sci_controller_enable_port_task_scheduler(struct isci_host *ihost)
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@ -1318,7 +1324,9 @@ void isci_host_deinit(struct isci_host *ihost)
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*/
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*/
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writel(0, &ihost->scu_registers->peg0.sgpio.interface_control);
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writel(0, &ihost->scu_registers->peg0.sgpio.interface_control);
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spin_lock_irq(&ihost->scic_lock);
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sci_controller_reset(ihost);
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sci_controller_reset(ihost);
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spin_unlock_irq(&ihost->scic_lock);
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/* Cancel any/all outstanding port timers */
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/* Cancel any/all outstanding port timers */
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for (i = 0; i < ihost->logical_port_entries; i++) {
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for (i = 0; i < ihost->logical_port_entries; i++) {
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@ -1605,6 +1613,9 @@ static void sci_controller_reset_hardware(struct isci_host *ihost)
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/* The write to the UFQGP clears the UFQPR */
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/* The write to the UFQGP clears the UFQPR */
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writel(0, &ihost->scu_registers->sdma.unsolicited_frame_get_pointer);
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writel(0, &ihost->scu_registers->sdma.unsolicited_frame_get_pointer);
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/* clear all interrupts */
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writel(~SMU_INTERRUPT_STATUS_RESERVED_MASK, &ihost->smu_registers->interrupt_status);
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}
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}
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static void sci_controller_resetting_state_enter(struct sci_base_state_machine *sm)
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static void sci_controller_resetting_state_enter(struct sci_base_state_machine *sm)
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@ -2391,7 +2402,9 @@ int isci_host_init(struct isci_host *ihost)
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int i, err;
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int i, err;
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enum sci_status status;
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enum sci_status status;
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spin_lock_irq(&ihost->scic_lock);
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status = sci_controller_construct(ihost, scu_base(ihost), smu_base(ihost));
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status = sci_controller_construct(ihost, scu_base(ihost), smu_base(ihost));
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spin_unlock_irq(&ihost->scic_lock);
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if (status != SCI_SUCCESS) {
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if (status != SCI_SUCCESS) {
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dev_err(&ihost->pdev->dev,
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dev_err(&ihost->pdev->dev,
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"%s: sci_controller_construct failed - status = %x\n",
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"%s: sci_controller_construct failed - status = %x\n",
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@ -200,6 +200,7 @@ struct isci_host {
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struct pci_dev *pdev;
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struct pci_dev *pdev;
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#define IHOST_START_PENDING 0
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#define IHOST_START_PENDING 0
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#define IHOST_STOP_PENDING 1
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#define IHOST_STOP_PENDING 1
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#define IHOST_IRQ_ENABLED 2
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unsigned long flags;
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unsigned long flags;
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wait_queue_head_t eventq;
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wait_queue_head_t eventq;
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struct Scsi_Host *shost;
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struct Scsi_Host *shost;
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