mirror of https://gitee.com/openkylin/linux.git
Merge tag 'drm-intel-next-fixes-2019-11-07' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
One RCU fix and fix for suspend GEM_BUG_ON (with dependencies). Signed-off-by: Dave Airlie <airlied@redhat.com> From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191107145058.GA17401@jlahtine-desk.ger.corp.intel.com
This commit is contained in:
commit
23aae183ff
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@ -11,50 +11,6 @@
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#include "i915_drv.h"
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static bool switch_to_kernel_context_sync(struct intel_gt *gt)
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{
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bool result = !intel_gt_is_wedged(gt);
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if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME) {
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/* XXX hide warning from gem_eio */
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if (i915_modparams.reset) {
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dev_err(gt->i915->drm.dev,
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"Failed to idle engines, declaring wedged!\n");
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GEM_TRACE_DUMP();
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}
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/*
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* Forcibly cancel outstanding work and leave
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* the gpu quiet.
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*/
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intel_gt_set_wedged(gt);
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result = false;
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}
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if (intel_gt_pm_wait_for_idle(gt))
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result = false;
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return result;
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}
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static void user_forcewake(struct intel_gt *gt, bool suspend)
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{
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int count = atomic_read(>->user_wakeref);
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/* Inside suspend/resume so single threaded, no races to worry about. */
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if (likely(!count))
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return;
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intel_gt_pm_get(gt);
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if (suspend) {
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GEM_BUG_ON(count > atomic_read(>->wakeref.count));
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atomic_sub(count, >->wakeref.count);
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} else {
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atomic_add(count, >->wakeref.count);
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}
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intel_gt_pm_put(gt);
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}
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void i915_gem_suspend(struct drm_i915_private *i915)
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{
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GEM_TRACE("\n");
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@ -62,8 +18,6 @@ void i915_gem_suspend(struct drm_i915_private *i915)
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intel_wakeref_auto(&i915->ggtt.userfault_wakeref, 0);
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flush_workqueue(i915->wq);
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user_forcewake(&i915->gt, true);
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/*
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* We have to flush all the executing contexts to main memory so
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* that they can saved in the hibernation image. To ensure the last
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@ -73,8 +27,7 @@ void i915_gem_suspend(struct drm_i915_private *i915)
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* state. Fortunately, the kernel_context is disposable and we do
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* not rely on its state.
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*/
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intel_gt_suspend(&i915->gt);
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intel_uc_suspend(&i915->gt.uc);
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intel_gt_suspend_prepare(&i915->gt);
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i915_gem_drain_freed_objects(i915);
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}
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@ -116,6 +69,8 @@ void i915_gem_suspend_late(struct drm_i915_private *i915)
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* machine in an unusable condition.
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*/
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intel_gt_suspend_late(&i915->gt);
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spin_lock_irqsave(&i915->mm.obj_lock, flags);
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for (phase = phases; *phase; phase++) {
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LIST_HEAD(keep);
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@ -140,8 +95,6 @@ void i915_gem_suspend_late(struct drm_i915_private *i915)
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list_splice_tail(&keep, *phase);
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}
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spin_unlock_irqrestore(&i915->mm.obj_lock, flags);
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i915_gem_sanitize(i915);
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}
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void i915_gem_resume(struct drm_i915_private *i915)
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@ -161,14 +114,6 @@ void i915_gem_resume(struct drm_i915_private *i915)
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if (intel_gt_resume(&i915->gt))
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goto err_wedged;
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intel_uc_resume(&i915->gt.uc);
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/* Always reload a context for powersaving. */
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if (!switch_to_kernel_context_sync(&i915->gt))
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goto err_wedged;
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user_forcewake(&i915->gt, false);
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out_unlock:
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intel_uncore_forcewake_put(&i915->uncore, FORCEWAKE_ALL);
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return;
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|
|
|
@ -31,9 +31,11 @@ void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
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intel_uc_init_early(>->uc);
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}
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void intel_gt_init_hw_early(struct drm_i915_private *i915)
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void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt)
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{
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i915->gt.ggtt = &i915->ggtt;
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gt->ggtt = ggtt;
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intel_gt_sanitize(gt, false);
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}
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static void init_unused_ring(struct intel_gt *gt, u32 base)
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|
|
|
@ -28,7 +28,7 @@ static inline struct intel_gt *huc_to_gt(struct intel_huc *huc)
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}
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void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915);
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void intel_gt_init_hw_early(struct drm_i915_private *i915);
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void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt);
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int __must_check intel_gt_init_hw(struct intel_gt *gt);
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int intel_gt_init(struct intel_gt *gt);
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void intel_gt_driver_register(struct intel_gt *gt);
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|
|
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@ -4,6 +4,8 @@
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* Copyright © 2019 Intel Corporation
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*/
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#include <linux/suspend.h>
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#include "i915_drv.h"
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#include "i915_globals.h"
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#include "i915_params.h"
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@ -18,6 +20,24 @@
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#include "intel_rps.h"
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#include "intel_wakeref.h"
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static void user_forcewake(struct intel_gt *gt, bool suspend)
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{
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int count = atomic_read(>->user_wakeref);
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/* Inside suspend/resume so single threaded, no races to worry about. */
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if (likely(!count))
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return;
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intel_gt_pm_get(gt);
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if (suspend) {
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GEM_BUG_ON(count > atomic_read(>->wakeref.count));
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atomic_sub(count, >->wakeref.count);
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} else {
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atomic_add(count, >->wakeref.count);
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}
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intel_gt_pm_put(gt);
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}
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static int __gt_unpark(struct intel_wakeref *wf)
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{
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struct intel_gt *gt = container_of(wf, typeof(*gt), wakeref);
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@ -118,8 +138,22 @@ void intel_gt_sanitize(struct intel_gt *gt, bool force)
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{
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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intel_wakeref_t wakeref;
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GEM_TRACE("\n");
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GEM_TRACE("force:%s\n", yesno(force));
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/* Use a raw wakeref to avoid calling intel_display_power_get early */
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wakeref = intel_runtime_pm_get(gt->uncore->rpm);
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intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
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/*
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* As we have just resumed the machine and woken the device up from
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* deep PCI sleep (presumably D3_cold), assume the HW has been reset
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* back to defaults, recovering from whatever wedged state we left it
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* in and so worth trying to use the device once more.
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*/
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if (intel_gt_is_wedged(gt))
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intel_gt_unset_wedged(gt);
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intel_uc_sanitize(>->uc);
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@ -127,6 +161,8 @@ void intel_gt_sanitize(struct intel_gt *gt, bool force)
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if (engine->reset.prepare)
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engine->reset.prepare(engine);
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intel_uc_reset_prepare(>->uc);
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if (reset_engines(gt) || force) {
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for_each_engine(engine, gt, id)
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__intel_engine_reset(engine, false);
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@ -135,6 +171,9 @@ void intel_gt_sanitize(struct intel_gt *gt, bool force)
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for_each_engine(engine, gt, id)
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if (engine->reset.finish)
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engine->reset.finish(engine);
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intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
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intel_runtime_pm_put(gt->uncore->rpm, wakeref);
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}
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void intel_gt_pm_fini(struct intel_gt *gt)
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@ -148,6 +187,8 @@ int intel_gt_resume(struct intel_gt *gt)
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enum intel_engine_id id;
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int err = 0;
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GEM_TRACE("\n");
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/*
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* After resume, we may need to poke into the pinned kernel
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* contexts to paper over any damage caused by the sudden suspend.
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@ -186,14 +227,22 @@ int intel_gt_resume(struct intel_gt *gt)
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}
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intel_rc6_enable(>->rc6);
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intel_uc_resume(>->uc);
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user_forcewake(gt, false);
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intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
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intel_gt_pm_put(gt);
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return err;
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}
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static void wait_for_idle(struct intel_gt *gt)
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static void wait_for_suspend(struct intel_gt *gt)
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{
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if (!intel_gt_pm_is_awake(gt))
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return;
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|
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if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME) {
|
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/*
|
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* Forcibly cancel outstanding work and leave
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|
@ -205,27 +254,65 @@ static void wait_for_idle(struct intel_gt *gt)
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intel_gt_pm_wait_for_idle(gt);
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}
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void intel_gt_suspend(struct intel_gt *gt)
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void intel_gt_suspend_prepare(struct intel_gt *gt)
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{
|
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user_forcewake(gt, true);
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wait_for_suspend(gt);
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|
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intel_uc_suspend(>->uc);
|
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}
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|
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static suspend_state_t pm_suspend_target(void)
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{
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#if IS_ENABLED(CONFIG_PM_SLEEP)
|
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return pm_suspend_target_state;
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#else
|
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return PM_SUSPEND_TO_IDLE;
|
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#endif
|
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}
|
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|
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void intel_gt_suspend_late(struct intel_gt *gt)
|
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{
|
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intel_wakeref_t wakeref;
|
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|
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/* We expect to be idle already; but also want to be independent */
|
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wait_for_idle(gt);
|
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wait_for_suspend(gt);
|
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|
||||
/*
|
||||
* On disabling the device, we want to turn off HW access to memory
|
||||
* that we no longer own.
|
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*
|
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* However, not all suspend-states disable the device. S0 (s2idle)
|
||||
* is effectively runtime-suspend, the device is left powered on
|
||||
* but needs to be put into a low power state. We need to keep
|
||||
* powermanagement enabled, but we also retain system state and so
|
||||
* it remains safe to keep on using our allocated memory.
|
||||
*/
|
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if (pm_suspend_target() == PM_SUSPEND_TO_IDLE)
|
||||
return;
|
||||
|
||||
with_intel_runtime_pm(gt->uncore->rpm, wakeref) {
|
||||
intel_rps_disable(>->rps);
|
||||
intel_rc6_disable(>->rc6);
|
||||
intel_llc_disable(>->llc);
|
||||
}
|
||||
|
||||
intel_gt_sanitize(gt, false);
|
||||
|
||||
GEM_TRACE("\n");
|
||||
}
|
||||
|
||||
void intel_gt_runtime_suspend(struct intel_gt *gt)
|
||||
{
|
||||
intel_uc_runtime_suspend(>->uc);
|
||||
|
||||
GEM_TRACE("\n");
|
||||
}
|
||||
|
||||
int intel_gt_runtime_resume(struct intel_gt *gt)
|
||||
{
|
||||
GEM_TRACE("\n");
|
||||
|
||||
intel_gt_init_swizzling(gt);
|
||||
|
||||
return intel_uc_runtime_resume(>->uc);
|
||||
|
|
|
@ -43,8 +43,9 @@ void intel_gt_pm_fini(struct intel_gt *gt);
|
|||
|
||||
void intel_gt_sanitize(struct intel_gt *gt, bool force);
|
||||
|
||||
void intel_gt_suspend_prepare(struct intel_gt *gt);
|
||||
void intel_gt_suspend_late(struct intel_gt *gt);
|
||||
int intel_gt_resume(struct intel_gt *gt);
|
||||
void intel_gt_suspend(struct intel_gt *gt);
|
||||
|
||||
void intel_gt_runtime_suspend(struct intel_gt *gt);
|
||||
int intel_gt_runtime_resume(struct intel_gt *gt);
|
||||
|
|
|
@ -525,6 +525,11 @@ void intel_rc6_init(struct intel_rc6 *rc6)
|
|||
|
||||
void intel_rc6_sanitize(struct intel_rc6 *rc6)
|
||||
{
|
||||
if (rc6->enabled) { /* unbalanced suspend/resume */
|
||||
rpm_get(rc6);
|
||||
rc6->enabled = false;
|
||||
}
|
||||
|
||||
if (rc6->supported)
|
||||
__intel_rc6_disable(rc6);
|
||||
}
|
||||
|
|
|
@ -15,7 +15,8 @@ static int live_gt_resume(void *arg)
|
|||
|
||||
/* Do several suspend/resume cycles to check we don't explode! */
|
||||
do {
|
||||
intel_gt_suspend(gt);
|
||||
intel_gt_suspend_prepare(gt);
|
||||
intel_gt_suspend_late(gt);
|
||||
|
||||
if (gt->rc6.enabled) {
|
||||
pr_err("rc6 still enabled after suspend!\n");
|
||||
|
|
|
@ -603,8 +603,6 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
|
|||
if (ret)
|
||||
goto err_uncore;
|
||||
|
||||
i915_gem_init_mmio(dev_priv);
|
||||
|
||||
return 0;
|
||||
|
||||
err_uncore:
|
||||
|
@ -1177,7 +1175,7 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
|
|||
if (ret)
|
||||
goto err_ggtt;
|
||||
|
||||
intel_gt_init_hw_early(dev_priv);
|
||||
intel_gt_init_hw_early(&dev_priv->gt, &dev_priv->ggtt);
|
||||
|
||||
ret = i915_ggtt_enable_hw(dev_priv);
|
||||
if (ret) {
|
||||
|
@ -1821,7 +1819,7 @@ static int i915_drm_resume(struct drm_device *dev)
|
|||
|
||||
disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
|
||||
|
||||
i915_gem_sanitize(dev_priv);
|
||||
intel_gt_sanitize(&dev_priv->gt, true);
|
||||
|
||||
ret = i915_ggtt_enable_hw(dev_priv);
|
||||
if (ret)
|
||||
|
@ -1952,8 +1950,6 @@ static int i915_drm_resume_early(struct drm_device *dev)
|
|||
|
||||
intel_power_domains_resume(dev_priv);
|
||||
|
||||
intel_gt_sanitize(&dev_priv->gt, true);
|
||||
|
||||
enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
|
||||
|
||||
return ret;
|
||||
|
|
|
@ -1779,7 +1779,6 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
|
|||
/* i915_gem.c */
|
||||
int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
|
||||
void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
|
||||
void i915_gem_sanitize(struct drm_i915_private *i915);
|
||||
void i915_gem_init_early(struct drm_i915_private *dev_priv);
|
||||
void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
|
||||
int i915_gem_freeze(struct drm_i915_private *dev_priv);
|
||||
|
@ -1863,7 +1862,6 @@ static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
|
|||
return atomic_read(&error->reset_engine_count[engine->uabi_class]);
|
||||
}
|
||||
|
||||
void i915_gem_init_mmio(struct drm_i915_private *i915);
|
||||
int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
|
||||
void i915_gem_driver_register(struct drm_i915_private *i915);
|
||||
void i915_gem_driver_unregister(struct drm_i915_private *i915);
|
||||
|
|
|
@ -1039,38 +1039,6 @@ i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
|
|||
return err;
|
||||
}
|
||||
|
||||
void i915_gem_sanitize(struct drm_i915_private *i915)
|
||||
{
|
||||
intel_wakeref_t wakeref;
|
||||
|
||||
GEM_TRACE("\n");
|
||||
|
||||
wakeref = intel_runtime_pm_get(&i915->runtime_pm);
|
||||
intel_uncore_forcewake_get(&i915->uncore, FORCEWAKE_ALL);
|
||||
|
||||
/*
|
||||
* As we have just resumed the machine and woken the device up from
|
||||
* deep PCI sleep (presumably D3_cold), assume the HW has been reset
|
||||
* back to defaults, recovering from whatever wedged state we left it
|
||||
* in and so worth trying to use the device once more.
|
||||
*/
|
||||
if (intel_gt_is_wedged(&i915->gt))
|
||||
intel_gt_unset_wedged(&i915->gt);
|
||||
|
||||
/*
|
||||
* If we inherit context state from the BIOS or earlier occupants
|
||||
* of the GPU, the GPU may be in an inconsistent state when we
|
||||
* try to take over. The only way to remove the earlier state
|
||||
* is by resetting. However, resetting on earlier gen is tricky as
|
||||
* it may impact the display and we are uncertain about the stability
|
||||
* of the reset, so this could be applied to even earlier gen.
|
||||
*/
|
||||
intel_gt_sanitize(&i915->gt, false);
|
||||
|
||||
intel_uncore_forcewake_put(&i915->uncore, FORCEWAKE_ALL);
|
||||
intel_runtime_pm_put(&i915->runtime_pm, wakeref);
|
||||
}
|
||||
|
||||
static int __intel_engines_record_defaults(struct intel_gt *gt)
|
||||
{
|
||||
struct i915_request *requests[I915_NUM_ENGINES] = {};
|
||||
|
@ -1413,11 +1381,6 @@ void i915_gem_driver_release(struct drm_i915_private *dev_priv)
|
|||
WARN_ON(!list_empty(&dev_priv->gem.contexts.list));
|
||||
}
|
||||
|
||||
void i915_gem_init_mmio(struct drm_i915_private *i915)
|
||||
{
|
||||
i915_gem_sanitize(i915);
|
||||
}
|
||||
|
||||
static void i915_gem_init__mm(struct drm_i915_private *i915)
|
||||
{
|
||||
spin_lock_init(&i915->mm.obj_lock);
|
||||
|
|
|
@ -202,21 +202,26 @@ static void kick_submission(struct intel_engine_cs *engine,
|
|||
if (prio <= engine->execlists.queue_priority_hint)
|
||||
return;
|
||||
|
||||
rcu_read_lock();
|
||||
|
||||
/* Nothing currently active? We're overdue for a submission! */
|
||||
inflight = execlists_active(&engine->execlists);
|
||||
if (!inflight)
|
||||
return;
|
||||
goto unlock;
|
||||
|
||||
/*
|
||||
* If we are already the currently executing context, don't
|
||||
* bother evaluating if we should preempt ourselves.
|
||||
*/
|
||||
if (inflight->hw_context == rq->hw_context)
|
||||
return;
|
||||
goto unlock;
|
||||
|
||||
engine->execlists.queue_priority_hint = prio;
|
||||
if (need_preempt(prio, rq_prio(inflight)))
|
||||
tasklet_hi_schedule(&engine->execlists.tasklet);
|
||||
|
||||
unlock:
|
||||
rcu_read_unlock();
|
||||
}
|
||||
|
||||
static void __i915_schedule(struct i915_sched_node *node,
|
||||
|
|
|
@ -124,7 +124,6 @@ static void pm_resume(struct drm_i915_private *i915)
|
|||
*/
|
||||
with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
|
||||
intel_gt_sanitize(&i915->gt, false);
|
||||
i915_gem_sanitize(i915);
|
||||
|
||||
i915_gem_restore_gtt_mappings(i915);
|
||||
i915_gem_restore_fences(&i915->ggtt);
|
||||
|
|
|
@ -183,7 +183,6 @@ struct drm_i915_private *mock_gem_device(void)
|
|||
intel_timelines_init(i915);
|
||||
|
||||
mock_init_ggtt(i915, &i915->ggtt);
|
||||
i915->gt.ggtt = &i915->ggtt;
|
||||
|
||||
mkwrite_device_info(i915)->engine_mask = BIT(0);
|
||||
|
||||
|
|
|
@ -118,8 +118,7 @@ void mock_init_ggtt(struct drm_i915_private *i915, struct i915_ggtt *ggtt)
|
|||
ggtt->vm.vma_ops.clear_pages = clear_pages;
|
||||
|
||||
i915_address_space_init(&ggtt->vm, VM_CLASS_GGTT);
|
||||
|
||||
intel_gt_init_hw_early(i915);
|
||||
i915->gt.ggtt = ggtt;
|
||||
}
|
||||
|
||||
void mock_fini_ggtt(struct i915_ggtt *ggtt)
|
||||
|
|
Loading…
Reference in New Issue