mirror of https://gitee.com/openkylin/linux.git
PCI: keystone: Cleanup ks_pcie_link_up()
ks_pcie_link_up() uses registers from the designware core to get the status of the link. Move the register defines to pcie-designware.h and cleanup ks_pcie_link_up(). Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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@ -38,8 +38,6 @@
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/* Application register defines */
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#define LTSSM_EN_VAL BIT(0)
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#define LTSSM_STATE_MASK 0x1f
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#define LTSSM_STATE_L0 0x11
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#define DBI_CS2 BIT(5)
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#define OB_XLAT_EN_VAL BIT(1)
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@ -87,11 +85,7 @@
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#define ERR_IRQ_ENABLE_SET 0x1c8
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#define ERR_IRQ_ENABLE_CLR 0x1cc
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/* Config space registers */
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#define DEBUG0 0x728
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#define MAX_MSI_HOST_IRQS 8
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/* PCIE controller device IDs */
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#define PCIE_RC_K2HK 0xb008
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#define PCIE_RC_K2E 0xb009
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@ -442,8 +436,9 @@ static int ks_pcie_link_up(struct dw_pcie *pci)
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{
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u32 val;
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val = dw_pcie_readl_dbi(pci, DEBUG0);
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return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0;
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val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0);
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val &= PORT_LOGIC_LTSSM_STATE_MASK;
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return (val == PORT_LOGIC_LTSSM_STATE_L0);
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}
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static void ks_pcie_initiate_link_train(struct keystone_pcie *ks_pcie)
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@ -37,6 +37,10 @@
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#define PORT_LINK_MODE_4_LANES (0x7 << 16)
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#define PORT_LINK_MODE_8_LANES (0xf << 16)
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#define PCIE_PORT_DEBUG0 0x728
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#define PORT_LOGIC_LTSSM_STATE_MASK 0x1f
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#define PORT_LOGIC_LTSSM_STATE_L0 0x11
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#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
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#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
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#define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8)
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