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ASoC: wm5110: Fix PGA clear when disabling DRE 

We don't want to use a bypassed write in wm5110_clear_pga_volume,
we might disable the DRE whilst the CODEC is powered down. A
normal regmap_write will always go to the hardware (when not on
cache_only) even if the written value matches the cache. As using
a normal write will still achieve the desired behaviour of bring
the cache and hardware in sync, this patch updates the function
to use a normal write, which avoids issues when the CODEC is
powered down.

Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Cc: stable@vger.kernel.org
This commit is contained in:
Charles Keepax 2016-01-06 15:15:37 +00:00 committed by Mark Brown
parent e73694d871
commit 24338722cf
1 changed files with 3 additions and 5 deletions
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8
sound/soc/codecs/wm5110.c
View File

@ -360,15 +360,13 @@ static int wm5110_hp_ev(struct snd_soc_dapm_widget *w,
static int wm5110_clear_pga_volume(struct arizona *arizona, int output)
{
struct reg_sequence clear_pga = {
ARIZONA_OUTPUT_PATH_CONFIG_1L + output * 4, 0x80
};
unsigned int reg = ARIZONA_OUTPUT_PATH_CONFIG_1L + output * 4;
int ret;
ret = regmap_multi_reg_write_bypassed(arizona->regmap, &clear_pga, 1);
ret = regmap_write(arizona->regmap, reg, 0x80);
if (ret)
dev_err(arizona->dev, "Failed to clear PGA (0x%x): %d\n",
clear_pga.reg, ret);
reg, ret);
return ret;
}