mirror of https://gitee.com/openkylin/linux.git
Merge branches 'acpi-soc' and 'acpi-tables'
* acpi-soc: ACPI: APD: Add AMD misc clock handler support clk: x86: Add ST oscout platform clock ACPI / LPSS: Only call pwm_add_table() for Bay Trail PWM if PMIC HRV is 2 * acpi-tables: ACPI / tables: improve comments regarding acpi_parse_entries_array()
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commit
2448d1399b
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@ -11,6 +11,7 @@
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*/
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#include <linux/clk-provider.h>
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#include <linux/platform_data/clk-st.h>
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#include <linux/platform_device.h>
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#include <linux/pm_domain.h>
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#include <linux/clkdev.h>
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@ -72,6 +73,47 @@ static int acpi_apd_setup(struct apd_private_data *pdata)
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}
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#ifdef CONFIG_X86_AMD_PLATFORM_DEVICE
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static int misc_check_res(struct acpi_resource *ares, void *data)
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{
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struct resource res;
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return !acpi_dev_resource_memory(ares, &res);
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}
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static int st_misc_setup(struct apd_private_data *pdata)
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{
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struct acpi_device *adev = pdata->adev;
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struct platform_device *clkdev;
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struct st_clk_data *clk_data;
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struct resource_entry *rentry;
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struct list_head resource_list;
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int ret;
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clk_data = devm_kzalloc(&adev->dev, sizeof(*clk_data), GFP_KERNEL);
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if (!clk_data)
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return -ENOMEM;
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INIT_LIST_HEAD(&resource_list);
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ret = acpi_dev_get_resources(adev, &resource_list, misc_check_res,
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NULL);
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if (ret < 0)
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return -ENOENT;
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list_for_each_entry(rentry, &resource_list, node) {
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clk_data->base = devm_ioremap(&adev->dev, rentry->res->start,
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resource_size(rentry->res));
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break;
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}
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acpi_dev_free_resource_list(&resource_list);
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clkdev = platform_device_register_data(&adev->dev, "clk-st",
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PLATFORM_DEVID_NONE, clk_data,
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sizeof(*clk_data));
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return PTR_ERR_OR_ZERO(clkdev);
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}
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static const struct apd_device_desc cz_i2c_desc = {
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.setup = acpi_apd_setup,
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.fixed_clk_rate = 133000000,
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@ -94,6 +136,10 @@ static const struct apd_device_desc cz_uart_desc = {
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.fixed_clk_rate = 48000000,
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.properties = uart_properties,
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};
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static const struct apd_device_desc st_misc_desc = {
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.setup = st_misc_setup,
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};
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#endif
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#ifdef CONFIG_ARM64
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@ -179,6 +225,7 @@ static const struct acpi_device_id acpi_apd_device_ids[] = {
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{ "AMD0020", APD_ADDR(cz_uart_desc) },
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{ "AMDI0020", APD_ADDR(cz_uart_desc) },
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{ "AMD0030", },
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{ "AMD0040", APD_ADDR(st_misc_desc)},
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#endif
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#ifdef CONFIG_ARM64
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{ "APMC0D0F", APD_ADDR(xgene_i2c_desc) },
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@ -69,6 +69,10 @@ ACPI_MODULE_NAME("acpi_lpss");
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#define LPSS_SAVE_CTX BIT(4)
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#define LPSS_NO_D3_DELAY BIT(5)
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/* Crystal Cove PMIC shares same ACPI ID between different platforms */
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#define BYT_CRC_HRV 2
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#define CHT_CRC_HRV 3
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struct lpss_private_data;
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struct lpss_device_desc {
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@ -162,7 +166,7 @@ static void byt_pwm_setup(struct lpss_private_data *pdata)
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if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1"))
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return;
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if (!acpi_dev_present("INT33FD", NULL, -1))
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if (!acpi_dev_present("INT33FD", NULL, BYT_CRC_HRV))
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pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup));
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}
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@ -222,7 +222,7 @@ void acpi_table_print_madt_entry(struct acpi_subtable_header *header)
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* acpi_parse_entries_array - for each proc_num find a suitable subtable
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*
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* @id: table id (for debugging purposes)
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* @table_size: single entry size
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* @table_size: size of the root table
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* @table_header: where does the table start?
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* @proc: array of acpi_subtable_proc struct containing entry id
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* and associated handler with it
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@ -233,6 +233,11 @@ void acpi_table_print_madt_entry(struct acpi_subtable_header *header)
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* on it. Assumption is that there's only single handler for particular
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* entry id.
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*
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* The table_size is not the size of the complete ACPI table (the length
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* field in the header struct), but only the size of the root table; i.e.,
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* the offset from the very first byte of the complete ACPI table, to the
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* first byte of the very first subtable.
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*
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* On success returns sum of all matching entries for all proc handlers.
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* Otherwise, -ENODEV or -EINVAL is returned.
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*/
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@ -400,7 +405,7 @@ int __init acpi_table_parse(char *id, acpi_tbl_table_handler handler)
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return -ENODEV;
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}
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/*
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/*
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* The BIOS is supposed to supply a single APIC/MADT,
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* but some report two. Provide a knob to use either.
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* (don't you wish instance 0 and 1 were not the same?)
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@ -1,3 +1,4 @@
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obj-$(CONFIG_PMC_ATOM) += clk-pmc-atom.o
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obj-$(CONFIG_X86_AMD_PLATFORM_DEVICE) += clk-st.o
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clk-x86-lpss-objs := clk-lpt.o
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obj-$(CONFIG_X86_INTEL_LPSS) += clk-x86-lpss.o
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obj-$(CONFIG_PMC_ATOM) += clk-pmc-atom.o
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@ -0,0 +1,77 @@
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// SPDX-License-Identifier: MIT
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/*
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* clock framework for AMD Stoney based clocks
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*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*/
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/platform_data/clk-st.h>
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#include <linux/platform_device.h>
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/* Clock Driving Strength 2 register */
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#define CLKDRVSTR2 0x28
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/* Clock Control 1 register */
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#define MISCCLKCNTL1 0x40
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/* Auxiliary clock1 enable bit */
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#define OSCCLKENB 2
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/* 25Mhz auxiliary output clock freq bit */
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#define OSCOUT1CLK25MHZ 16
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#define ST_CLK_48M 0
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#define ST_CLK_25M 1
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#define ST_CLK_MUX 2
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#define ST_CLK_GATE 3
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#define ST_MAX_CLKS 4
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static const char * const clk_oscout1_parents[] = { "clk48MHz", "clk25MHz" };
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static struct clk_hw *hws[ST_MAX_CLKS];
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static int st_clk_probe(struct platform_device *pdev)
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{
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struct st_clk_data *st_data;
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st_data = dev_get_platdata(&pdev->dev);
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if (!st_data || !st_data->base)
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return -EINVAL;
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hws[ST_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz", NULL, 0,
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48000000);
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hws[ST_CLK_25M] = clk_hw_register_fixed_rate(NULL, "clk25MHz", NULL, 0,
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25000000);
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hws[ST_CLK_MUX] = clk_hw_register_mux(NULL, "oscout1_mux",
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clk_oscout1_parents, ARRAY_SIZE(clk_oscout1_parents),
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0, st_data->base + CLKDRVSTR2, OSCOUT1CLK25MHZ, 3, 0, NULL);
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clk_set_parent(hws[ST_CLK_MUX]->clk, hws[ST_CLK_25M]->clk);
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hws[ST_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1", "oscout1_mux",
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0, st_data->base + MISCCLKCNTL1, OSCCLKENB,
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CLK_GATE_SET_TO_DISABLE, NULL);
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clk_hw_register_clkdev(hws[ST_CLK_GATE], "oscout1", NULL);
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return 0;
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}
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static int st_clk_remove(struct platform_device *pdev)
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{
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int i;
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for (i = 0; i < ST_MAX_CLKS; i++)
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clk_hw_unregister(hws[i]);
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return 0;
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}
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static struct platform_driver st_clk_driver = {
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.driver = {
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.name = "clk-st",
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.suppress_bind_attrs = true,
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},
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.probe = st_clk_probe,
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.remove = st_clk_remove,
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};
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builtin_platform_driver(st_clk_driver);
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@ -0,0 +1,17 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* clock framework for AMD Stoney based clock
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*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*/
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#ifndef __CLK_ST_H
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#define __CLK_ST_H
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#include <linux/compiler.h>
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struct st_clk_data {
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void __iomem *base;
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};
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#endif /* __CLK_ST_H */
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