mirror of https://gitee.com/openkylin/linux.git
blackfin: scb: Add system crossbar init code.
If SCB exists in select blackfin cpu, developer can change the SCB priority in kernel configuration. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Steven Miao <realmz6@gmail.com>
This commit is contained in:
Steven Miao
parent
6e4664525b
commit
24a70cf2b2
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@ -0,0 +1,21 @@
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/*
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* arch/blackfin/mach-common/scb-init.c - reprogram system cross bar priority
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*
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* Copyright 2012 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#define SCB_SLOT_OFFSET 24
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#define SCB_MI_MAX_SLOT 32
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struct scb_mi_prio {
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unsigned long scb_mi_arbr;
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unsigned long scb_mi_arbw;
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unsigned char scb_mi_slots;
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unsigned char scb_mi_prio[SCB_MI_MAX_SLOT];
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};
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extern struct scb_mi_prio scb_data[];
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extern void init_scb(void);
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@ -35,6 +35,9 @@
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#ifdef CONFIG_BF60x
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#include <mach/pm.h>
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#endif
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#ifdef CONFIG_SCB_PRIORITY
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#include <asm/scb.h>
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#endif
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u16 _bfin_swrst;
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EXPORT_SYMBOL(_bfin_swrst);
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@ -1101,6 +1104,9 @@ void __init setup_arch(char **cmdline_p)
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#endif
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init_exception_vectors();
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bfin_cache_init(); /* Initialize caches for the boot CPU */
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#ifdef CONFIG_SCB_PRIORITY
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init_scb();
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#endif
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}
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static int __init topology_init(void)
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File diff suppressed because it is too large
Load Diff
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@ -4,3 +4,4 @@
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obj-y := dma.o clock.o ints-priority.o
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obj-$(CONFIG_PM) += pm.o dpm.o
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obj-$(CONFIG_SCB_PRIORITY) += scb.o
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@ -0,0 +1,232 @@
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/*
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* arch/blackfin/mach-common/scb-init.c - reprogram system cross bar priority
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*
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* Copyright 2012 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <asm/blackfin.h>
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#include <asm/scb.h>
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struct scb_mi_prio scb_data[] = {
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#ifdef CONFIG_SCB0_MI0
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{ REG_SCB0_ARBR0, REG_SCB0_ARBW0, 32, {
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CONFIG_SCB0_MI0_SLOT0,
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CONFIG_SCB0_MI0_SLOT1,
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CONFIG_SCB0_MI0_SLOT2,
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CONFIG_SCB0_MI0_SLOT3,
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CONFIG_SCB0_MI0_SLOT4,
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CONFIG_SCB0_MI0_SLOT5,
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CONFIG_SCB0_MI0_SLOT6,
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CONFIG_SCB0_MI0_SLOT7,
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CONFIG_SCB0_MI0_SLOT8,
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CONFIG_SCB0_MI0_SLOT9,
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CONFIG_SCB0_MI0_SLOT10,
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CONFIG_SCB0_MI0_SLOT11,
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CONFIG_SCB0_MI0_SLOT12,
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CONFIG_SCB0_MI0_SLOT13,
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CONFIG_SCB0_MI0_SLOT14,
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CONFIG_SCB0_MI0_SLOT15,
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CONFIG_SCB0_MI0_SLOT16,
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CONFIG_SCB0_MI0_SLOT17,
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CONFIG_SCB0_MI0_SLOT18,
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CONFIG_SCB0_MI0_SLOT19,
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CONFIG_SCB0_MI0_SLOT20,
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CONFIG_SCB0_MI0_SLOT21,
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CONFIG_SCB0_MI0_SLOT22,
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CONFIG_SCB0_MI0_SLOT23,
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CONFIG_SCB0_MI0_SLOT24,
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CONFIG_SCB0_MI0_SLOT25,
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CONFIG_SCB0_MI0_SLOT26,
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CONFIG_SCB0_MI0_SLOT27,
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CONFIG_SCB0_MI0_SLOT28,
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CONFIG_SCB0_MI0_SLOT29,
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CONFIG_SCB0_MI0_SLOT30,
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CONFIG_SCB0_MI0_SLOT31
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},
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},
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#endif
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#ifdef CONFIG_SCB0_MI1
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{ REG_SCB0_ARBR1, REG_SCB0_ARBW1, 32, {
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CONFIG_SCB0_MI1_SLOT0,
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CONFIG_SCB0_MI1_SLOT1,
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CONFIG_SCB0_MI1_SLOT2,
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CONFIG_SCB0_MI1_SLOT3,
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CONFIG_SCB0_MI1_SLOT4,
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CONFIG_SCB0_MI1_SLOT5,
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CONFIG_SCB0_MI1_SLOT6,
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CONFIG_SCB0_MI1_SLOT7,
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CONFIG_SCB0_MI1_SLOT8,
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CONFIG_SCB0_MI1_SLOT9,
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CONFIG_SCB0_MI1_SLOT10,
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CONFIG_SCB0_MI1_SLOT11,
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CONFIG_SCB0_MI1_SLOT12,
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CONFIG_SCB0_MI1_SLOT13,
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CONFIG_SCB0_MI1_SLOT14,
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CONFIG_SCB0_MI1_SLOT15,
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CONFIG_SCB0_MI1_SLOT16,
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CONFIG_SCB0_MI1_SLOT17,
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CONFIG_SCB0_MI1_SLOT18,
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CONFIG_SCB0_MI1_SLOT19,
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CONFIG_SCB0_MI1_SLOT20,
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CONFIG_SCB0_MI1_SLOT21,
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CONFIG_SCB0_MI1_SLOT22,
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CONFIG_SCB0_MI1_SLOT23,
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CONFIG_SCB0_MI1_SLOT24,
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CONFIG_SCB0_MI1_SLOT25,
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CONFIG_SCB0_MI1_SLOT26,
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CONFIG_SCB0_MI1_SLOT27,
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CONFIG_SCB0_MI1_SLOT28,
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CONFIG_SCB0_MI1_SLOT29,
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CONFIG_SCB0_MI1_SLOT30,
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CONFIG_SCB0_MI1_SLOT31
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},
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},
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#endif
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#ifdef CONFIG_SCB0_MI2
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{ REG_SCB0_ARBR2, REG_SCB0_ARBW2, 32, {
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CONFIG_SCB0_MI2_SLOT0,
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CONFIG_SCB0_MI2_SLOT1,
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CONFIG_SCB0_MI2_SLOT2,
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CONFIG_SCB0_MI2_SLOT3,
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CONFIG_SCB0_MI2_SLOT4,
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CONFIG_SCB0_MI2_SLOT5,
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CONFIG_SCB0_MI2_SLOT6,
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CONFIG_SCB0_MI2_SLOT7,
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CONFIG_SCB0_MI2_SLOT8,
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CONFIG_SCB0_MI2_SLOT9,
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CONFIG_SCB0_MI2_SLOT10,
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CONFIG_SCB0_MI2_SLOT11,
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CONFIG_SCB0_MI2_SLOT12,
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CONFIG_SCB0_MI2_SLOT13,
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CONFIG_SCB0_MI2_SLOT14,
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CONFIG_SCB0_MI2_SLOT15,
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CONFIG_SCB0_MI2_SLOT16,
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CONFIG_SCB0_MI2_SLOT17,
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CONFIG_SCB0_MI2_SLOT18,
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CONFIG_SCB0_MI2_SLOT19,
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CONFIG_SCB0_MI2_SLOT20,
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CONFIG_SCB0_MI2_SLOT21,
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CONFIG_SCB0_MI2_SLOT22,
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CONFIG_SCB0_MI2_SLOT23,
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CONFIG_SCB0_MI2_SLOT24,
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CONFIG_SCB0_MI2_SLOT25,
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CONFIG_SCB0_MI2_SLOT26,
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CONFIG_SCB0_MI2_SLOT27,
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CONFIG_SCB0_MI2_SLOT28,
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CONFIG_SCB0_MI2_SLOT29,
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CONFIG_SCB0_MI2_SLOT30,
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CONFIG_SCB0_MI2_SLOT31
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},
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},
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#endif
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#ifdef CONFIG_SCB0_MI3
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{ REG_SCB0_ARBR3, REG_SCB0_ARBW3, 32, {
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CONFIG_SCB0_MI3_SLOT0,
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CONFIG_SCB0_MI3_SLOT1,
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CONFIG_SCB0_MI3_SLOT2,
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CONFIG_SCB0_MI3_SLOT3,
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CONFIG_SCB0_MI3_SLOT4,
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CONFIG_SCB0_MI3_SLOT5,
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CONFIG_SCB0_MI3_SLOT6,
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CONFIG_SCB0_MI3_SLOT7,
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CONFIG_SCB0_MI3_SLOT8,
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CONFIG_SCB0_MI3_SLOT9,
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CONFIG_SCB0_MI3_SLOT10,
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CONFIG_SCB0_MI3_SLOT11,
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CONFIG_SCB0_MI3_SLOT12,
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CONFIG_SCB0_MI3_SLOT13,
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CONFIG_SCB0_MI3_SLOT14,
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CONFIG_SCB0_MI3_SLOT15,
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CONFIG_SCB0_MI3_SLOT16,
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CONFIG_SCB0_MI3_SLOT17,
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CONFIG_SCB0_MI3_SLOT18,
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CONFIG_SCB0_MI3_SLOT19,
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CONFIG_SCB0_MI3_SLOT20,
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CONFIG_SCB0_MI3_SLOT21,
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CONFIG_SCB0_MI3_SLOT22,
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CONFIG_SCB0_MI3_SLOT23,
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CONFIG_SCB0_MI3_SLOT24,
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CONFIG_SCB0_MI3_SLOT25,
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CONFIG_SCB0_MI3_SLOT26,
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CONFIG_SCB0_MI3_SLOT27,
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CONFIG_SCB0_MI3_SLOT28,
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CONFIG_SCB0_MI3_SLOT29,
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CONFIG_SCB0_MI3_SLOT30,
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CONFIG_SCB0_MI3_SLOT31
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},
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},
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#endif
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#ifdef CONFIG_SCB0_MI4
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{ REG_SCB0_ARBR4, REG_SCB4_ARBW0, 32, {
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CONFIG_SCB0_MI4_SLOT0,
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CONFIG_SCB0_MI4_SLOT1,
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CONFIG_SCB0_MI4_SLOT2,
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CONFIG_SCB0_MI4_SLOT3,
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CONFIG_SCB0_MI4_SLOT4,
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CONFIG_SCB0_MI4_SLOT5,
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CONFIG_SCB0_MI4_SLOT6,
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CONFIG_SCB0_MI4_SLOT7,
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CONFIG_SCB0_MI4_SLOT8,
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CONFIG_SCB0_MI4_SLOT9,
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CONFIG_SCB0_MI4_SLOT10,
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CONFIG_SCB0_MI4_SLOT11,
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CONFIG_SCB0_MI4_SLOT12,
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CONFIG_SCB0_MI4_SLOT13,
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CONFIG_SCB0_MI4_SLOT14,
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CONFIG_SCB0_MI4_SLOT15,
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CONFIG_SCB0_MI4_SLOT16,
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CONFIG_SCB0_MI4_SLOT17,
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CONFIG_SCB0_MI4_SLOT18,
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CONFIG_SCB0_MI4_SLOT19,
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CONFIG_SCB0_MI4_SLOT20,
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CONFIG_SCB0_MI4_SLOT21,
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CONFIG_SCB0_MI4_SLOT22,
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CONFIG_SCB0_MI4_SLOT23,
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CONFIG_SCB0_MI4_SLOT24,
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CONFIG_SCB0_MI4_SLOT25,
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CONFIG_SCB0_MI4_SLOT26,
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CONFIG_SCB0_MI4_SLOT27,
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CONFIG_SCB0_MI4_SLOT28,
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CONFIG_SCB0_MI4_SLOT29,
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CONFIG_SCB0_MI4_SLOT30,
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CONFIG_SCB0_MI4_SLOT31
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},
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},
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#endif
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#ifdef CONFIG_SCB0_MI5
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{ REG_SCB0_ARBR5, REG_SCB0_ARBW5, 16, {
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CONFIG_SCB0_MI5_SLOT0,
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CONFIG_SCB0_MI5_SLOT1,
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CONFIG_SCB0_MI5_SLOT2,
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CONFIG_SCB0_MI5_SLOT3,
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CONFIG_SCB0_MI5_SLOT4,
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CONFIG_SCB0_MI5_SLOT5,
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CONFIG_SCB0_MI5_SLOT6,
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CONFIG_SCB0_MI5_SLOT7,
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CONFIG_SCB0_MI5_SLOT8,
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CONFIG_SCB0_MI5_SLOT9,
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CONFIG_SCB0_MI5_SLOT10,
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CONFIG_SCB0_MI5_SLOT11,
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CONFIG_SCB0_MI5_SLOT12,
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CONFIG_SCB0_MI5_SLOT13,
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CONFIG_SCB0_MI5_SLOT14,
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CONFIG_SCB0_MI5_SLOT15,
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},
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},
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#endif
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/*
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{ REG_SCB1_ARBR0, REG_SCB1_ARBW0, scb1_mi0, 20 },
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{ REG_SCB2_ARBR0, REG_SCB2_ARBW0, scb2_mi0, 10 },
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{ REG_SCB3_ARBR0, REG_SCB3_ARBW0, scb3_mi0, 16 },
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{ REG_SCB4_ARBR0, REG_SCB4_ARBW0, scb4_mi0, 16 },
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{ REG_SCB5_ARBR0, REG_SCB5_ARBW0, scb5_mi0, 8 },
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{ REG_SCB6_ARBR0, REG_SCB6_ARBW0, scb6_mi0, 4 },
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{ REG_SCB7_ARBR0, REG_SCB7_ARBW0, scb7_mi0, 6 },
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{ REG_SCB8_ARBR0, REG_SCB8_ARBW0, scb8_mi0, 8 },
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{ REG_SCB9_ARBR0, REG_SCB9_ARBW0, scb9_mi0, 10 },
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{ REG_SCB10_ARBR0, REG_SCB10_ARBW0, scb20_mi0, 16 },
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*/
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{ 0, }
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};
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@ -10,6 +10,7 @@ obj-$(CONFIG_PM) += pm.o
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ifneq ($(CONFIG_BF60x),y)
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obj-$(CONFIG_PM) += dpmc_modes.o
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endif
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obj-$(CONFIG_SCB_PRIORITY) += scb-init.o
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obj-$(CONFIG_CPU_VOLTAGE) += dpmc.o
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obj-$(CONFIG_SMP) += smp.o
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obj-$(CONFIG_BFIN_KERNEL_CLOCK) += clocks-init.o
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@ -0,0 +1,53 @@
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/*
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* arch/blackfin/mach-common/scb-init.c - reprogram system cross bar priority
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*
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* Copyright 2012 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <asm/scb.h>
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__attribute__((l1_text))
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inline void scb_mi_write(unsigned long scb_mi_arbw, unsigned int slots,
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unsigned char *scb_mi_prio)
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{
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unsigned int i;
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for (i = 0; i < slots; ++i)
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bfin_write32(scb_mi_arbw, (i << SCB_SLOT_OFFSET) | scb_mi_prio[i]);
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}
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__attribute__((l1_text))
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inline void scb_mi_read(unsigned long scb_mi_arbw, unsigned int slots,
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unsigned char *scb_mi_prio)
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{
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unsigned int i;
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for (i = 0; i < slots; ++i) {
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bfin_write32(scb_mi_arbw, (0xFF << SCB_SLOT_OFFSET) | i);
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scb_mi_prio[i] = bfin_read32(scb_mi_arbw);
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}
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}
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__attribute__((l1_text))
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void init_scb(void)
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{
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unsigned int i, j;
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unsigned char scb_tmp_prio[32];
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pr_info("Init System Crossbar\n");
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for (i = 0; scb_data[i].scb_mi_arbr > 0; ++i) {
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scb_mi_write(scb_data[i].scb_mi_arbw, scb_data[i].scb_mi_slots, scb_data[i].scb_mi_prio);
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pr_debug("scb priority at 0x%lx:\n", scb_data[i].scb_mi_arbr);
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scb_mi_read(scb_data[i].scb_mi_arbw, scb_data[i].scb_mi_slots, scb_tmp_prio);
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for (j = 0; j < scb_data[i].scb_mi_slots; ++j)
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pr_debug("slot %d = %d\n", j, scb_tmp_prio[j]);
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}
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}
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