mirror of https://gitee.com/openkylin/linux.git
drm/amdgpu: optimize gfx9 init_microcode function
Split each type of firmware into single function for easy to maintain. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Le Ma
Alex Deucher
parent
65e60f6e06
commit
24c44c8917
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@ -617,47 +617,14 @@ static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev)
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}
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}
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static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
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static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev,
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const char *chip_name)
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{
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const char *chip_name;
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char fw_name[30];
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int err;
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struct amdgpu_firmware_info *info = NULL;
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const struct common_firmware_header *header = NULL;
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const struct gfx_firmware_header_v1_0 *cp_hdr;
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const struct rlc_firmware_header_v2_0 *rlc_hdr;
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unsigned int *tmp = NULL;
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unsigned int i = 0;
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uint16_t version_major;
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uint16_t version_minor;
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uint32_t smu_version;
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DRM_DEBUG("\n");
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switch (adev->asic_type) {
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case CHIP_VEGA10:
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chip_name = "vega10";
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break;
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case CHIP_VEGA12:
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chip_name = "vega12";
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break;
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case CHIP_VEGA20:
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chip_name = "vega20";
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break;
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case CHIP_RAVEN:
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if (adev->rev_id >= 8)
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chip_name = "raven2";
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else if (adev->pdev->device == 0x15d8)
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chip_name = "picasso";
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else
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chip_name = "raven";
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break;
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case CHIP_ARCTURUS:
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chip_name = "arcturus";
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break;
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default:
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BUG();
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}
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snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
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err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
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@ -692,6 +659,58 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
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adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
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adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
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if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
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info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
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info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
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info->fw = adev->gfx.pfp_fw;
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header = (const struct common_firmware_header *)info->fw->data;
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adev->firmware.fw_size +=
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ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
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info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
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info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
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info->fw = adev->gfx.me_fw;
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header = (const struct common_firmware_header *)info->fw->data;
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adev->firmware.fw_size +=
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ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
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info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
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info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
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info->fw = adev->gfx.ce_fw;
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header = (const struct common_firmware_header *)info->fw->data;
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adev->firmware.fw_size +=
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ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
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}
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out:
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if (err) {
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dev_err(adev->dev,
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"gfx9: Failed to load firmware \"%s\"\n",
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fw_name);
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release_firmware(adev->gfx.pfp_fw);
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adev->gfx.pfp_fw = NULL;
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release_firmware(adev->gfx.me_fw);
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adev->gfx.me_fw = NULL;
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release_firmware(adev->gfx.ce_fw);
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adev->gfx.ce_fw = NULL;
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}
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return err;
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}
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static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev,
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const char *chip_name)
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{
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char fw_name[30];
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int err;
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struct amdgpu_firmware_info *info = NULL;
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const struct common_firmware_header *header = NULL;
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const struct rlc_firmware_header_v2_0 *rlc_hdr;
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unsigned int *tmp = NULL;
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unsigned int i = 0;
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uint16_t version_major;
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uint16_t version_minor;
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uint32_t smu_version;
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/*
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* For Picasso && AM4 SOCKET board, we use picasso_rlc_am4.bin
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* instead of picasso_rlc.bin.
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@ -766,6 +785,58 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
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if (adev->gfx.rlc.is_rlc_v2_1)
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gfx_v9_0_init_rlc_ext_microcode(adev);
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if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
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info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
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info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
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info->fw = adev->gfx.rlc_fw;
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header = (const struct common_firmware_header *)info->fw->data;
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adev->firmware.fw_size +=
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ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
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if (adev->gfx.rlc.is_rlc_v2_1 &&
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adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
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adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
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adev->gfx.rlc.save_restore_list_srm_size_bytes) {
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info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
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info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
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info->fw = adev->gfx.rlc_fw;
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adev->firmware.fw_size +=
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ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
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info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
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info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
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info->fw = adev->gfx.rlc_fw;
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adev->firmware.fw_size +=
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ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
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info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
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info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
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info->fw = adev->gfx.rlc_fw;
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adev->firmware.fw_size +=
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ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
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}
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}
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out:
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if (err) {
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dev_err(adev->dev,
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"gfx9: Failed to load firmware \"%s\"\n",
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fw_name);
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release_firmware(adev->gfx.rlc_fw);
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adev->gfx.rlc_fw = NULL;
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}
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return err;
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}
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static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev,
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const char *chip_name)
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{
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char fw_name[30];
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int err;
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struct amdgpu_firmware_info *info = NULL;
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const struct common_firmware_header *header = NULL;
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const struct gfx_firmware_header_v1_0 *cp_hdr;
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snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
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err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
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if (err)
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@ -796,57 +867,6 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
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}
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if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
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info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
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info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
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info->fw = adev->gfx.pfp_fw;
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header = (const struct common_firmware_header *)info->fw->data;
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adev->firmware.fw_size +=
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ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
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info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
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info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
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info->fw = adev->gfx.me_fw;
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header = (const struct common_firmware_header *)info->fw->data;
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adev->firmware.fw_size +=
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ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
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info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
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info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
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info->fw = adev->gfx.ce_fw;
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header = (const struct common_firmware_header *)info->fw->data;
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adev->firmware.fw_size +=
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ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
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info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
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info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
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info->fw = adev->gfx.rlc_fw;
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header = (const struct common_firmware_header *)info->fw->data;
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adev->firmware.fw_size +=
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ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
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if (adev->gfx.rlc.is_rlc_v2_1 &&
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adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
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adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
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adev->gfx.rlc.save_restore_list_srm_size_bytes) {
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info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
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info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
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info->fw = adev->gfx.rlc_fw;
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adev->firmware.fw_size +=
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ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
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info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
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info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
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info->fw = adev->gfx.rlc_fw;
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adev->firmware.fw_size +=
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ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
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info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
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info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
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info->fw = adev->gfx.rlc_fw;
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adev->firmware.fw_size +=
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ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
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}
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info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
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info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
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info->fw = adev->gfx.mec_fw;
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@ -875,7 +895,6 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
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adev->firmware.fw_size +=
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ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
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}
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}
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out:
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@ -885,14 +904,6 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
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dev_err(adev->dev,
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"gfx9: Failed to load firmware \"%s\"\n",
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fw_name);
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release_firmware(adev->gfx.pfp_fw);
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adev->gfx.pfp_fw = NULL;
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release_firmware(adev->gfx.me_fw);
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adev->gfx.me_fw = NULL;
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release_firmware(adev->gfx.ce_fw);
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adev->gfx.ce_fw = NULL;
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release_firmware(adev->gfx.rlc_fw);
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adev->gfx.rlc_fw = NULL;
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release_firmware(adev->gfx.mec_fw);
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adev->gfx.mec_fw = NULL;
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release_firmware(adev->gfx.mec2_fw);
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@ -901,6 +912,54 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
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return err;
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}
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static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
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{
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const char *chip_name;
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int r;
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DRM_DEBUG("\n");
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switch (adev->asic_type) {
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case CHIP_VEGA10:
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chip_name = "vega10";
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break;
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case CHIP_VEGA12:
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chip_name = "vega12";
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break;
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case CHIP_VEGA20:
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chip_name = "vega20";
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break;
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case CHIP_RAVEN:
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if (adev->rev_id >= 8)
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chip_name = "raven2";
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else if (adev->pdev->device == 0x15d8)
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chip_name = "picasso";
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else
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chip_name = "raven";
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break;
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break;
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case CHIP_ARCTURUS:
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chip_name = "arcturus";
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break;
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default:
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BUG();
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}
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r = gfx_v9_0_init_cp_gfx_microcode(adev, chip_name);
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if (r)
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return r;
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r = gfx_v9_0_init_rlc_microcode(adev, chip_name);
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if (r)
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return r;
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r = gfx_v9_0_init_cp_compute_microcode(adev, chip_name);
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if (r)
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return r;
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return r;
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}
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static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
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{
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u32 count = 0;
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