mirror of https://gitee.com/openkylin/linux.git
MT2701:
- add MUSB device to the SoC and the EVB MT7623: - add Mali-450 device node and bindings - add phy to gmac2 -----BEGIN PGP SIGNATURE----- iQJLBAABCAA1FiEEUdvKHhzqrUYPB/u8L21+TfbCqH4FAl7AO9gXHG1hdHRoaWFz LmJnZ0BnbWFpbC5jb20ACgkQL21+TfbCqH7hLg//aShrNUXpvEWR8HeLwzB5EkhR S+8PFfhF40VtjH5/pqyJsSa7M/airffqQbMwIyy1S/HsVHMggZDdTD26DhpH/x0E 14XnDxKWLmfrxMP/kq5A5X3DM1WQej2X1zpf/aKPkg52EazmYE47F1p2LtRdo+fq WAh01ZLHH/Z2J51RJdIwwGHGLNkQR1Ns9HJBKSPVdO28P/+FDO9iP33MmBKRi40A lX6k2vkxd+MV+cmNs573LUCzBkPGaAWmDfgDI3Vn3LJbxlWttfqhDttFKhysK4bn vaBRFgR4hSwjxhSLFNHBQ9DgCrx6mYezisd1ehCo3XZDB5stZjJJYvrxFdtXeVtX JxrvnDue69B+ZOy6hv1Z5+rRQCPMwvGRX3fiKEAjrRjcT9AnaEEbW2SjVZyN85o9 nAk/juENSVcUhCWt6CJdTXygDUsopLOs/lZH3fWg3xMWaMsC/ZZrl4uxd4PQNo2N x1YzcCVptnw2UxuF3asvgRqez6uHx4mUr3FN8MTmM5G9nlABKId6GUTu/Wuh8c50 YEcNOa/fMm7amAIkXlBTIiRbSf3b+dc7KsD8ld/cIcUMf5l0UWX2GXMW3colx4RE MatsAaOaSHHiVbS43O/Iw/rp29ZInmTnARqeijJCdWo4Vz0D9kR9HP7lleFZ+39a 3+HgZWsS2R7/LuXyG3g= =cK6A -----END PGP SIGNATURE----- Merge tag 'v5.7-next-dts32' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt MT2701: - add MUSB device to the SoC and the EVB MT7623: - add Mali-450 device node and bindings - add phy to gmac2 * tag 'v5.7-next-dts32' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: arm: dts: mt2701: Add usb2 device nodes dt-bindings: gpu: mali-utgard: add mediatek, mt7623-mali compatible arm: dts: mt7623: add Mali-450 device node arm: dts: mt7623: add phy-mode property for gmac2 Link: https://lore.kernel.org/r/ec17cf62-5463-9537-6618-2db9b2b5036e@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
25880899bf
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@ -41,6 +41,7 @@ properties:
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- amlogic,meson-gxbb-mali
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- amlogic,meson-gxl-mali
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- hisilicon,hi6220-mali
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- mediatek,mt7623-mali
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- rockchip,rk3328-mali
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- const: arm,mali-450
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@ -130,6 +131,7 @@ allOf:
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- amlogic,meson8-mali
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- amlogic,meson8b-mali
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- hisilicon,hi6220-mali
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- mediatek,mt7623-mali
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- rockchip,rk3036-mali
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- rockchip,rk3066-mali
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- rockchip,rk3188-mali
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@ -6,6 +6,7 @@
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include "mt2701.dtsi"
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/ {
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@ -61,6 +62,15 @@ backlight_lcd: backlight_lcd {
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>;
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default-brightness-level = <9>;
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};
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usb_vbus: regulator@0 {
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compatible = "regulator-fixed";
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regulator-name = "usb_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&pio 45 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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&auxadc {
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@ -230,3 +240,14 @@ pins1 {
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&uart0 {
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status = "okay";
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};
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&usb2 {
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status = "okay";
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usb-role-switch;
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connector{
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compatible = "gpio-usb-b-connector", "usb-b-connector";
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type = "micro";
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id-gpios = <&pio 44 GPIO_ACTIVE_HIGH>;
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vbus-supply = <&usb_vbus>;
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};
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};
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@ -671,6 +671,39 @@ u3port1: usb-phy@1a244900 {
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};
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};
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usb2: usb@11200000 {
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compatible = "mediatek,mt2701-musb",
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"mediatek,mtk-musb";
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reg = <0 0x11200000 0 0x1000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
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interrupt-names = "mc";
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phys = <&u2port2 PHY_TYPE_USB2>;
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dr_mode = "otg";
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clocks = <&pericfg CLK_PERI_USB0>,
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<&pericfg CLK_PERI_USB0_MCU>,
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<&pericfg CLK_PERI_USB_SLV>;
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clock-names = "main","mcu","univpll";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
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status = "disabled";
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};
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u2phy0: usb-phy@11210000 {
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compatible = "mediatek,generic-tphy-v1";
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reg = <0 0x11210000 0 0x0800>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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status = "okay";
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u2port2: usb-phy@1a1c4800 {
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reg = <0 0x11210800 0 0x0100>;
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clocks = <&topckgen CLK_TOP_USB_PHY48M>;
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clock-names = "ref";
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#phy-cells = <1>;
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status = "okay";
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};
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};
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ethsys: syscon@1b000000 {
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compatible = "mediatek,mt2701-ethsys", "syscon";
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reg = <0 0x1b000000 0 0x1000>;
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@ -3,6 +3,7 @@
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* Copyright (c) 2017-2018 MediaTek Inc.
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* Author: John Crispin <john@phrozen.org>
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* Sean Wang <sean.wang@mediatek.com>
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* Ryder Lee <ryder.lee@mediatek.com>
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*
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*/
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@ -733,6 +734,30 @@ g3dsys: syscon@13000000 {
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#reset-cells = <1>;
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};
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mali: gpu@13040000 {
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compatible = "mediatek,mt7623-mali", "arm,mali-450";
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reg = <0 0x13040000 0 0x30000>;
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interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 172 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 173 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 174 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 177 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 178 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 179 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
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interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
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"ppmmu1", "pp2", "ppmmu2", "pp3", "ppmmu3",
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"pp";
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clocks = <&topckgen CLK_TOP_MMPLL>,
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<&g3dsys CLK_G3DSYS_CORE>;
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clock-names = "bus", "core";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>;
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resets = <&g3dsys MT2701_G3DSYS_CORE_RST>;
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};
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mmsys: syscon@14000000 {
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compatible = "mediatek,mt7623-mmsys",
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"mediatek,mt2701-mmsys",
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@ -138,6 +138,7 @@ fixed-link {
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mac@1 {
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compatible = "mediatek,eth-mac";
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reg = <1>;
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phy-mode = "rgmii";
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phy-handle = <&phy5>;
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};
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