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drm/i915: Always program m2 fractional value on CHV 

When fractional m2 divider isn't used on CHV the fractional part
is ignore by the hardware. Despite that, program the fractional
value (0 in this case) to the hardware register just to keep
things a bit more consistent. Might at least make register dumps
a bit less confusing when there isn't some stale fractional part
hanging around.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Deepak S <deepak.s@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ville Syrjälä 2015-07-08 23:45:47 +03:00 committed by Daniel Vetter
parent 4eee4920f0
commit 25a25dfce4
1 changed files with 1 additions and 2 deletions
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3
drivers/gpu/drm/i915/intel_display.c
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@ -7374,8 +7374,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
1 << DPIO_CHV_N_DIV_SHIFT);
/* M2 fraction division */
if (bestm2_frac)
vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
/* M2 fraction division enable */
dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));