mirror of https://gitee.com/openkylin/linux.git
ath9k_hw: Add dump_eeprom support for AR9003
Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Rajkumar Manoharan
John W. Linville
parent
9d630c7796
commit
2652620201
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@ -3418,6 +3418,133 @@ static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)
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return true;
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}
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#if defined(CONFIG_ATH9K_DEBUGFS) || defined(CONFIG_ATH9K_HTC_DEBUGFS)
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static u32 ar9003_dump_modal_eeprom(char *buf, u32 len, u32 size,
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struct ar9300_modal_eep_header *modal_hdr)
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{
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PR_EEP("Chain0 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[0]));
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PR_EEP("Chain1 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[1]));
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PR_EEP("Chain2 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[2]));
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PR_EEP("Ant. Common Control", le32_to_cpu(modal_hdr->antCtrlCommon));
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PR_EEP("Ant. Common Control2", le32_to_cpu(modal_hdr->antCtrlCommon2));
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PR_EEP("Ant. Gain", modal_hdr->antennaGain);
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PR_EEP("Switch Settle", modal_hdr->switchSettling);
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PR_EEP("Chain0 xatten1DB", modal_hdr->xatten1DB[0]);
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PR_EEP("Chain1 xatten1DB", modal_hdr->xatten1DB[1]);
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PR_EEP("Chain2 xatten1DB", modal_hdr->xatten1DB[2]);
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PR_EEP("Chain0 xatten1Margin", modal_hdr->xatten1Margin[0]);
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PR_EEP("Chain1 xatten1Margin", modal_hdr->xatten1Margin[1]);
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PR_EEP("Chain2 xatten1Margin", modal_hdr->xatten1Margin[2]);
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PR_EEP("Temp Slope", modal_hdr->tempSlope);
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PR_EEP("Volt Slope", modal_hdr->voltSlope);
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PR_EEP("spur Channels0", modal_hdr->spurChans[0]);
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PR_EEP("spur Channels1", modal_hdr->spurChans[1]);
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PR_EEP("spur Channels2", modal_hdr->spurChans[2]);
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PR_EEP("spur Channels3", modal_hdr->spurChans[3]);
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PR_EEP("spur Channels4", modal_hdr->spurChans[4]);
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PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]);
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PR_EEP("Chain1 NF Threshold", modal_hdr->noiseFloorThreshCh[1]);
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PR_EEP("Chain2 NF Threshold", modal_hdr->noiseFloorThreshCh[2]);
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PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl);
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PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart);
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PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn);
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PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn);
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PR_EEP("txClip", modal_hdr->txClip);
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PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize);
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PR_EEP("Chain0 ob", modal_hdr->ob[0]);
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PR_EEP("Chain1 ob", modal_hdr->ob[1]);
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PR_EEP("Chain2 ob", modal_hdr->ob[2]);
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PR_EEP("Chain0 db_stage2", modal_hdr->db_stage2[0]);
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PR_EEP("Chain1 db_stage2", modal_hdr->db_stage2[1]);
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PR_EEP("Chain2 db_stage2", modal_hdr->db_stage2[2]);
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PR_EEP("Chain0 db_stage3", modal_hdr->db_stage3[0]);
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PR_EEP("Chain1 db_stage3", modal_hdr->db_stage3[1]);
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PR_EEP("Chain2 db_stage3", modal_hdr->db_stage3[2]);
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PR_EEP("Chain0 db_stage4", modal_hdr->db_stage4[0]);
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PR_EEP("Chain1 db_stage4", modal_hdr->db_stage4[1]);
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PR_EEP("Chain2 db_stage4", modal_hdr->db_stage4[2]);
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return len;
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}
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static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
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u8 *buf, u32 len, u32 size)
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{
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struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
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struct ar9300_base_eep_hdr *pBase;
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if (!dump_base_hdr) {
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len += snprintf(buf + len, size - len,
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"%20s :\n", "2GHz modal Header");
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len += ar9003_dump_modal_eeprom(buf, len, size,
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&eep->modalHeader2G);
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len += snprintf(buf + len, size - len,
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"%20s :\n", "5GHz modal Header");
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len += ar9003_dump_modal_eeprom(buf, len, size,
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&eep->modalHeader5G);
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goto out;
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}
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pBase = &eep->baseEepHeader;
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PR_EEP("EEPROM Version", ah->eeprom.ar9300_eep.eepromVersion);
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PR_EEP("RegDomain1", le16_to_cpu(pBase->regDmn[0]));
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PR_EEP("RegDomain2", le16_to_cpu(pBase->regDmn[1]));
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PR_EEP("TX Mask", (pBase->txrxMask >> 4));
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PR_EEP("RX Mask", (pBase->txrxMask & 0x0f));
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PR_EEP("Allow 5GHz", !!(pBase->opCapFlags.opFlags &
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AR5416_OPFLAGS_11A));
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PR_EEP("Allow 2GHz", !!(pBase->opCapFlags.opFlags &
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AR5416_OPFLAGS_11G));
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PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags.opFlags &
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AR5416_OPFLAGS_N_2G_HT20));
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PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags.opFlags &
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AR5416_OPFLAGS_N_2G_HT40));
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PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags.opFlags &
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AR5416_OPFLAGS_N_5G_HT20));
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PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags.opFlags &
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AR5416_OPFLAGS_N_5G_HT40));
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PR_EEP("Big Endian", !!(pBase->opCapFlags.eepMisc & 0x01));
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PR_EEP("RF Silent", pBase->rfSilent);
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PR_EEP("BT option", pBase->blueToothOptions);
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PR_EEP("Device Cap", pBase->deviceCap);
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PR_EEP("Device Type", pBase->deviceType);
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PR_EEP("Power Table Offset", pBase->pwrTableOffset);
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PR_EEP("Tuning Caps1", pBase->params_for_tuning_caps[0]);
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PR_EEP("Tuning Caps2", pBase->params_for_tuning_caps[1]);
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PR_EEP("Enable Tx Temp Comp", !!(pBase->featureEnable & BIT(0)));
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PR_EEP("Enable Tx Volt Comp", !!(pBase->featureEnable & BIT(1)));
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PR_EEP("Enable fast clock", !!(pBase->featureEnable & BIT(2)));
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PR_EEP("Enable doubling", !!(pBase->featureEnable & BIT(3)));
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PR_EEP("Internal regulator", !!(pBase->featureEnable & BIT(4)));
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PR_EEP("Enable Paprd", !!(pBase->featureEnable & BIT(5)));
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PR_EEP("Driver Strength", !!(pBase->miscConfiguration & BIT(0)));
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PR_EEP("Chain mask Reduce", (pBase->miscConfiguration >> 0x3) & 0x1);
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PR_EEP("Write enable Gpio", pBase->eepromWriteEnableGpio);
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PR_EEP("WLAN Disable Gpio", pBase->wlanDisableGpio);
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PR_EEP("WLAN LED Gpio", pBase->wlanLedGpio);
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PR_EEP("Rx Band Select Gpio", pBase->rxBandSelectGpio);
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PR_EEP("Tx Gain", pBase->txrxgain >> 4);
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PR_EEP("Rx Gain", pBase->txrxgain & 0xf);
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PR_EEP("SW Reg", le32_to_cpu(pBase->swreg));
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len += snprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress",
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ah->eeprom.ar9300_eep.macAddr);
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out:
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if (len > size)
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len = size;
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return len;
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}
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#else
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static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
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u8 *buf, u32 len, u32 size)
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{
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return 0;
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}
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#endif
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/* XXX: review hardware docs */
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static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah)
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{
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@ -4997,6 +5124,7 @@ const struct eeprom_ops eep_ar9300_ops = {
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.check_eeprom = ath9k_hw_ar9300_check_eeprom,
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.get_eeprom = ath9k_hw_ar9300_get_eeprom,
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.fill_eeprom = ath9k_hw_ar9300_fill_eeprom,
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.dump_eeprom = ath9k_hw_ar9003_dump_eeprom,
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.get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
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.get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
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.set_board_values = ath9k_hw_ar9300_set_board_values,
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@ -649,6 +649,8 @@ struct eeprom_ops {
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int (*check_eeprom)(struct ath_hw *hw);
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u32 (*get_eeprom)(struct ath_hw *hw, enum eeprom_param param);
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bool (*fill_eeprom)(struct ath_hw *hw);
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u32 (*dump_eeprom)(struct ath_hw *hw, bool dump_base_hdr, u8 *buf,
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u32 len, u32 size);
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int (*get_eeprom_ver)(struct ath_hw *hw);
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int (*get_eeprom_rev)(struct ath_hw *hw);
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void (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan);
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@ -93,6 +93,12 @@
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(_ah)->reg_ops.write_flush((_ah)); \
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} while (0)
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#define PR_EEP(_s, _val) \
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do { \
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len += snprintf(buf + len, size - len, "%20s : %10d\n", \
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_s, (_val)); \
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} while (0)
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#define SM(_v, _f) (((_v) << _f##_S) & _f)
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#define MS(_v, _f) (((_v) & _f) >> _f##_S)
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#define REG_RMW_FIELD(_a, _r, _f, _v) \
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