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MIPS: Unify perf counter register definitions
Unify definitions for MIPS performance counter register fields in mipsregs.h rather than duplicating them in perf_events and oprofile. This will allow future patches to use them to expose performance counters to KVM guests. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Arnaldo Carvalho de Melo <acme@kernel.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Robert Richter <rric@kernel.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: oprofile-list@lists.sf.net Patchwork: https://patchwork.linux-mips.org/patch/15212/ Signed-off-by: James Hogan <james.hogan@imgtec.com>
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James Hogan
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573deec094
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@ -685,6 +685,39 @@
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#define MIPS_WATCHHI_W (_ULCAST_(1) << 0)
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#define MIPS_WATCHHI_IRW (_ULCAST_(0x7) << 0)
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/* PerfCnt control register definitions */
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#define MIPS_PERFCTRL_EXL (_ULCAST_(1) << 0)
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#define MIPS_PERFCTRL_K (_ULCAST_(1) << 1)
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#define MIPS_PERFCTRL_S (_ULCAST_(1) << 2)
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#define MIPS_PERFCTRL_U (_ULCAST_(1) << 3)
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#define MIPS_PERFCTRL_IE (_ULCAST_(1) << 4)
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#define MIPS_PERFCTRL_EVENT_S 5
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#define MIPS_PERFCTRL_EVENT (_ULCAST_(0x3ff) << MIPS_PERFCTRL_EVENT_S)
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#define MIPS_PERFCTRL_PCTD (_ULCAST_(1) << 15)
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#define MIPS_PERFCTRL_EC (_ULCAST_(0x3) << 23)
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#define MIPS_PERFCTRL_EC_R (_ULCAST_(0) << 23)
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#define MIPS_PERFCTRL_EC_RI (_ULCAST_(1) << 23)
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#define MIPS_PERFCTRL_EC_G (_ULCAST_(2) << 23)
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#define MIPS_PERFCTRL_EC_GRI (_ULCAST_(3) << 23)
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#define MIPS_PERFCTRL_W (_ULCAST_(1) << 30)
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#define MIPS_PERFCTRL_M (_ULCAST_(1) << 31)
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/* PerfCnt control register MT extensions used by MIPS cores */
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#define MIPS_PERFCTRL_VPEID_S 16
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#define MIPS_PERFCTRL_VPEID (_ULCAST_(0xf) << MIPS_PERFCTRL_VPEID_S)
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#define MIPS_PERFCTRL_TCID_S 22
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#define MIPS_PERFCTRL_TCID (_ULCAST_(0xff) << MIPS_PERFCTRL_TCID_S)
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#define MIPS_PERFCTRL_MT_EN (_ULCAST_(0x3) << 20)
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#define MIPS_PERFCTRL_MT_EN_ALL (_ULCAST_(0) << 20)
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#define MIPS_PERFCTRL_MT_EN_VPE (_ULCAST_(1) << 20)
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#define MIPS_PERFCTRL_MT_EN_TC (_ULCAST_(2) << 20)
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/* PerfCnt control register MT extensions used by BMIPS5000 */
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#define BRCM_PERFCTRL_TC (_ULCAST_(1) << 30)
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/* PerfCnt control register MT extensions used by Netlogic XLR */
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#define XLR_PERFCTRL_ALLTHREADS (_ULCAST_(1) << 13)
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/* MAAR bit definitions */
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#define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
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#define MIPS_MAAR_ADDR_SHIFT 12
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@ -101,40 +101,31 @@ struct mips_pmu {
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static struct mips_pmu mipspmu;
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#define M_PERFCTL_EXL (1 << 0)
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#define M_PERFCTL_KERNEL (1 << 1)
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#define M_PERFCTL_SUPERVISOR (1 << 2)
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#define M_PERFCTL_USER (1 << 3)
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#define M_PERFCTL_INTERRUPT_ENABLE (1 << 4)
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#define M_PERFCTL_EVENT(event) (((event) & 0x3ff) << 5)
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#define M_PERFCTL_VPEID(vpe) ((vpe) << 16)
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#define M_PERFCTL_EVENT(event) (((event) << MIPS_PERFCTRL_EVENT_S) & \
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MIPS_PERFCTRL_EVENT)
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#define M_PERFCTL_VPEID(vpe) ((vpe) << MIPS_PERFCTRL_VPEID_S)
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#ifdef CONFIG_CPU_BMIPS5000
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#define M_PERFCTL_MT_EN(filter) 0
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#else /* !CONFIG_CPU_BMIPS5000 */
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#define M_PERFCTL_MT_EN(filter) ((filter) << 20)
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#define M_PERFCTL_MT_EN(filter) (filter)
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#endif /* CONFIG_CPU_BMIPS5000 */
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#define M_TC_EN_ALL M_PERFCTL_MT_EN(0)
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#define M_TC_EN_VPE M_PERFCTL_MT_EN(1)
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#define M_TC_EN_TC M_PERFCTL_MT_EN(2)
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#define M_PERFCTL_TCID(tcid) ((tcid) << 22)
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#define M_PERFCTL_WIDE (1 << 30)
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#define M_PERFCTL_MORE (1 << 31)
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#define M_PERFCTL_TC (1 << 30)
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#define M_TC_EN_ALL M_PERFCTL_MT_EN(MIPS_PERFCTRL_MT_EN_ALL)
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#define M_TC_EN_VPE M_PERFCTL_MT_EN(MIPS_PERFCTRL_MT_EN_VPE)
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#define M_TC_EN_TC M_PERFCTL_MT_EN(MIPS_PERFCTRL_MT_EN_TC)
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#define M_PERFCTL_COUNT_EVENT_WHENEVER (M_PERFCTL_EXL | \
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M_PERFCTL_KERNEL | \
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M_PERFCTL_USER | \
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M_PERFCTL_SUPERVISOR | \
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M_PERFCTL_INTERRUPT_ENABLE)
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#define M_PERFCTL_COUNT_EVENT_WHENEVER (MIPS_PERFCTRL_EXL | \
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MIPS_PERFCTRL_K | \
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MIPS_PERFCTRL_U | \
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MIPS_PERFCTRL_S | \
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MIPS_PERFCTRL_IE)
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#ifdef CONFIG_MIPS_MT_SMP
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#define M_PERFCTL_CONFIG_MASK 0x3fff801f
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#else
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#define M_PERFCTL_CONFIG_MASK 0x1f
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#endif
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#define M_PERFCTL_EVENT_MASK 0xfe0
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#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
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@ -345,11 +336,11 @@ static void mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx)
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cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0xff) |
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(evt->config_base & M_PERFCTL_CONFIG_MASK) |
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/* Make sure interrupt enabled. */
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M_PERFCTL_INTERRUPT_ENABLE;
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MIPS_PERFCTRL_IE;
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if (IS_ENABLED(CONFIG_CPU_BMIPS5000))
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/* enable the counter for the calling thread */
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cpuc->saved_ctrl[idx] |=
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(1 << (12 + vpe_id())) | M_PERFCTL_TC;
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(1 << (12 + vpe_id())) | BRCM_PERFCTRL_TC;
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/*
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* We do not actually let the counter run. Leave it until start().
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@ -754,11 +745,11 @@ static int __n_counters(void)
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{
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if (!cpu_has_perf)
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return 0;
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if (!(read_c0_perfctrl0() & M_PERFCTL_MORE))
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if (!(read_c0_perfctrl0() & MIPS_PERFCTRL_M))
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return 1;
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if (!(read_c0_perfctrl1() & M_PERFCTL_MORE))
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if (!(read_c0_perfctrl1() & MIPS_PERFCTRL_M))
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return 2;
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if (!(read_c0_perfctrl2() & M_PERFCTL_MORE))
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if (!(read_c0_perfctrl2() & MIPS_PERFCTRL_M))
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return 3;
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return 4;
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@ -1339,7 +1330,7 @@ static int __hw_perf_event_init(struct perf_event *event)
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* We allow max flexibility on how each individual counter shared
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* by the single CPU operates (the mode exclusion and the range).
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*/
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hwc->config_base = M_PERFCTL_INTERRUPT_ENABLE;
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hwc->config_base = MIPS_PERFCTRL_IE;
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/* Calculate range bits and validate it. */
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if (num_possible_cpus() > 1)
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@ -1350,14 +1341,14 @@ static int __hw_perf_event_init(struct perf_event *event)
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mutex_unlock(&raw_event_mutex);
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if (!attr->exclude_user)
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hwc->config_base |= M_PERFCTL_USER;
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hwc->config_base |= MIPS_PERFCTRL_U;
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if (!attr->exclude_kernel) {
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hwc->config_base |= M_PERFCTL_KERNEL;
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hwc->config_base |= MIPS_PERFCTRL_K;
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/* MIPS kernel mode: KSU == 00b || EXL == 1 || ERL == 1 */
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hwc->config_base |= M_PERFCTL_EXL;
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hwc->config_base |= MIPS_PERFCTRL_EXL;
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}
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if (!attr->exclude_hv)
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hwc->config_base |= M_PERFCTL_SUPERVISOR;
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hwc->config_base |= MIPS_PERFCTRL_S;
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hwc->config_base &= M_PERFCTL_CONFIG_MASK;
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/*
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@ -1830,7 +1821,7 @@ init_hw_perf_events(void)
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mipspmu.num_counters = counters;
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mipspmu.irq = irq;
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if (read_c0_perfctrl0() & M_PERFCTL_WIDE) {
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if (read_c0_perfctrl0() & MIPS_PERFCTRL_W) {
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mipspmu.max_period = (1ULL << 63) - 1;
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mipspmu.valid_count = (1ULL << 63) - 1;
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mipspmu.overflow = 1ULL << 63;
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@ -15,26 +15,12 @@
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#include "op_impl.h"
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#define M_PERFCTL_EXL (1UL << 0)
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#define M_PERFCTL_KERNEL (1UL << 1)
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#define M_PERFCTL_SUPERVISOR (1UL << 2)
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#define M_PERFCTL_USER (1UL << 3)
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#define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4)
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#define M_PERFCTL_EVENT(event) (((event) & 0x3ff) << 5)
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#define M_PERFCTL_VPEID(vpe) ((vpe) << 16)
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#define M_PERFCTL_MT_EN(filter) ((filter) << 20)
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#define M_TC_EN_ALL M_PERFCTL_MT_EN(0)
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#define M_TC_EN_VPE M_PERFCTL_MT_EN(1)
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#define M_TC_EN_TC M_PERFCTL_MT_EN(2)
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#define M_PERFCTL_TCID(tcid) ((tcid) << 22)
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#define M_PERFCTL_WIDE (1UL << 30)
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#define M_PERFCTL_MORE (1UL << 31)
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#define M_PERFCTL_EVENT(event) (((event) << MIPS_PERFCTRL_EVENT_S) & \
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MIPS_PERFCTRL_EVENT)
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#define M_PERFCTL_VPEID(vpe) ((vpe) << MIPS_PERFCTRL_VPEID_S)
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#define M_COUNTER_OVERFLOW (1UL << 31)
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/* Netlogic XLR specific, count events in all threads in a core */
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#define M_PERFCTL_COUNT_ALL_THREADS (1UL << 13)
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static int (*save_perf_irq)(void);
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static int perfcount_irq;
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@ -51,7 +37,7 @@ static int perfcount_irq;
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#ifdef CONFIG_MIPS_MT_SMP
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static int cpu_has_mipsmt_pertccounters;
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#define WHAT (M_TC_EN_VPE | \
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#define WHAT (MIPS_PERFCTRL_MT_EN_VPE | \
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M_PERFCTL_VPEID(cpu_data[smp_processor_id()].vpe_id))
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#define vpe_id() (cpu_has_mipsmt_pertccounters ? \
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0 : cpu_data[smp_processor_id()].vpe_id)
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@ -161,15 +147,15 @@ static void mipsxx_reg_setup(struct op_counter_config *ctr)
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continue;
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reg.control[i] = M_PERFCTL_EVENT(ctr[i].event) |
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M_PERFCTL_INTERRUPT_ENABLE;
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MIPS_PERFCTRL_IE;
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if (ctr[i].kernel)
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reg.control[i] |= M_PERFCTL_KERNEL;
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reg.control[i] |= MIPS_PERFCTRL_K;
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if (ctr[i].user)
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reg.control[i] |= M_PERFCTL_USER;
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reg.control[i] |= MIPS_PERFCTRL_U;
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if (ctr[i].exl)
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reg.control[i] |= M_PERFCTL_EXL;
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reg.control[i] |= MIPS_PERFCTRL_EXL;
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if (boot_cpu_type() == CPU_XLR)
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reg.control[i] |= M_PERFCTL_COUNT_ALL_THREADS;
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reg.control[i] |= XLR_PERFCTRL_ALLTHREADS;
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reg.counter[i] = 0x80000000 - ctr[i].count;
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}
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}
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@ -254,7 +240,7 @@ static int mipsxx_perfcount_handler(void)
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case n + 1: \
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control = r_c0_perfctrl ## n(); \
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counter = r_c0_perfcntr ## n(); \
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if ((control & M_PERFCTL_INTERRUPT_ENABLE) && \
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if ((control & MIPS_PERFCTRL_IE) && \
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(counter & M_COUNTER_OVERFLOW)) { \
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oprofile_add_sample(get_irq_regs(), n); \
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w_c0_perfcntr ## n(reg.counter[n]); \
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@ -273,11 +259,11 @@ static inline int __n_counters(void)
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{
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if (!cpu_has_perf)
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return 0;
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if (!(read_c0_perfctrl0() & M_PERFCTL_MORE))
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if (!(read_c0_perfctrl0() & MIPS_PERFCTRL_M))
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return 1;
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if (!(read_c0_perfctrl1() & M_PERFCTL_MORE))
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if (!(read_c0_perfctrl1() & MIPS_PERFCTRL_M))
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return 2;
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if (!(read_c0_perfctrl2() & M_PERFCTL_MORE))
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if (!(read_c0_perfctrl2() & MIPS_PERFCTRL_M))
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return 3;
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return 4;
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