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drm/meson: add AFBC decoder registers for GXM and G12A 

Add the registers used to program the ARM Framebuffer Compression decoders
used in the Amlogic GXM and G12A SoCs families.

This also adds the routing and pipeline configuration bits and registers
needed to enable AFBC support.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191021091509.3864-2-narmstrong@baylibre.com
This commit is contained in:
Neil Armstrong 2019-10-21 11:15:01 +02:00
parent b0077e521c
commit 26a7abd488
2 changed files with 77 additions and 0 deletions
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62
drivers/gpu/drm/meson/meson_registers.h
View File

@ -138,19 +138,25 @@
#define VIU_ADDR_START 0x1a00
#define VIU_ADDR_END 0x1aff
#define VIU_SW_RESET 0x1a01
#define VIU_SW_RESET_OSD1_AFBCD BIT(31)
#define VIU_SW_RESET_G12A_OSD1_AFBCD BIT(21)
#define VIU_SW_RESET_G12A_AFBC_ARB BIT(19)
#define VIU_SW_RESET_OSD1 BIT(0)
#define VIU_MISC_CTRL0 0x1a06
#define VIU_CTRL0_VD1_AFBC_MASK 0x170000
#define VIU_MISC_CTRL1 0x1a07
#define MALI_AFBC_MISC GENMASK(15, 8)
#define D2D3_INTF_LENGTH 0x1a08
#define D2D3_INTF_CTRL0 0x1a09
#define VIU_OSD1_CTRL_STAT 0x1a10
#define VIU_OSD1_OSD_BLK_ENABLE BIT(0)
#define VIU_OSD1_OSD_MEM_MODE_LINEAR BIT(2)
#define VIU_OSD1_POSTBLD_SRC_VD1 (1 << 8)
#define VIU_OSD1_POSTBLD_SRC_VD2 (2 << 8)
#define VIU_OSD1_POSTBLD_SRC_OSD1 (3 << 8)
#define VIU_OSD1_POSTBLD_SRC_OSD2 (4 << 8)
#define VIU_OSD1_OSD_ENABLE BIT(21)
#define VIU_OSD1_CFG_SYN_EN BIT(31)
#define VIU_OSD1_CTRL_STAT2 0x1a2d
#define VIU_OSD1_COLOR_ADDR 0x1a11
#define VIU_OSD1_COLOR 0x1a12
@ -181,6 +187,16 @@
#define VIU_OSD1_FIFO_CTRL_STAT 0x1a2b
#define VIU_OSD1_TEST_RDDATA 0x1a2c
#define VIU_OSD1_PROT_CTRL 0x1a2e
#define VIU_OSD1_MALI_UNPACK_CTRL 0x1a2f
#define VIU_OSD1_MALI_UNPACK_EN BIT(31)
#define VIU_OSD1_MALI_AFBCD_R_REORDER GENMASK(15, 12)
#define VIU_OSD1_MALI_AFBCD_G_REORDER GENMASK(11, 8)
#define VIU_OSD1_MALI_AFBCD_B_REORDER GENMASK(7, 4)
#define VIU_OSD1_MALI_AFBCD_A_REORDER GENMASK(3, 0)
#define VIU_OSD1_MALI_REORDER_R 1
#define VIU_OSD1_MALI_REORDER_G 2
#define VIU_OSD1_MALI_REORDER_B 3
#define VIU_OSD1_MALI_REORDER_A 4
#define VIU_OSD2_CTRL_STAT 0x1a30
#define VIU_OSD2_CTRL_STAT2 0x1a4d
#define VIU_OSD2_COLOR_ADDR 0x1a31
@ -1595,15 +1611,33 @@
/* osd afbcd on gxtvbb */
#define OSD1_AFBCD_ENABLE 0x31a0
#define OSD1_AFBCD_ID_FIFO_THRD GENMASK(15, 9)
#define OSD1_AFBCD_DEC_ENABLE BIT(8)
#define OSD1_AFBCD_FRM_START BIT(0)
#define OSD1_AFBCD_MODE 0x31a1
#define OSD1_AFBCD_SOFT_RESET BIT(31)
#define OSD1_AFBCD_AXI_REORDER_MODE BIT(28)
#define OSD1_AFBCD_MIF_URGENT GENMASK(25, 24)
#define OSD1_AFBCD_HOLD_LINE_NUM GENMASK(22, 16)
#define OSD1_AFBCD_RGBA_EXCHAN_CTRL GENMASK(15, 8)
#define OSD1_AFBCD_HREG_BLOCK_SPLIT BIT(6)
#define OSD1_AFBCD_HREG_HALF_BLOCK BIT(5)
#define OSD1_AFBCD_HREG_PIXEL_PACKING_FMT GENMASK(4, 0)
#define OSD1_AFBCD_SIZE_IN 0x31a2
#define OSD1_AFBCD_HREG_VSIZE_IN GENMASK(31, 16)
#define OSD1_AFBCD_HREG_HSIZE_IN GENMASK(15, 0)
#define OSD1_AFBCD_HDR_PTR 0x31a3
#define OSD1_AFBCD_FRAME_PTR 0x31a4
#define OSD1_AFBCD_CHROMA_PTR 0x31a5
#define OSD1_AFBCD_CONV_CTRL 0x31a6
#define OSD1_AFBCD_CONV_LBUF_LEN GENMASK(15, 0)
#define OSD1_AFBCD_STATUS 0x31a8
#define OSD1_AFBCD_PIXEL_HSCOPE 0x31a9
#define OSD1_AFBCD_DEC_PIXEL_BGN_H GENMASK(31, 16)
#define OSD1_AFBCD_DEC_PIXEL_END_H GENMASK(15, 0)
#define OSD1_AFBCD_PIXEL_VSCOPE 0x31aa
#define OSD1_AFBCD_DEC_PIXEL_BGN_V GENMASK(31, 16)
#define OSD1_AFBCD_DEC_PIXEL_END_V GENMASK(15, 0)
/* add for gxm and 962e dv core2 */
#define DOLBY_CORE2A_SWAP_CTRL1 0x3434
@ -1615,12 +1649,34 @@
#define VPU_MAFBC_IRQ_CLEAR 0x3a02
#define VPU_MAFBC_IRQ_MASK 0x3a03
#define VPU_MAFBC_IRQ_STATUS 0x3a04
#define VPU_MAFBC_IRQ_SECURE_ID_ERROR BIT(5)
#define VPU_MAFBC_IRQ_AXI_ERROR BIT(4)
#define VPU_MAFBC_IRQ_DETILING_ERROR BIT(3)
#define VPU_MAFBC_IRQ_DECODE_ERROR BIT(2)
#define VPU_MAFBC_IRQ_CONFIGURATION_SWAPPED BIT(1)
#define VPU_MAFBC_IRQ_SURFACES_COMPLETED BIT(0)
#define VPU_MAFBC_COMMAND 0x3a05
#define VPU_MAFBC_PENDING_SWAP BIT(1)
#define VPU_MAFBC_DIRECT_SWAP BIT(0)
#define VPU_MAFBC_STATUS 0x3a06
#define VPU_MAFBC_ERROR BIT(2)
#define VPU_MAFBC_SWAPPING BIT(1)
#define VPU_MAFBC_ACTIVE BIT(0)
#define VPU_MAFBC_SURFACE_CFG 0x3a07
#define VPU_MAFBC_CONTINUOUS_DECODING_ENABLE BIT(16)
#define VPU_MAFBC_S3_ENABLE BIT(3)
#define VPU_MAFBC_S2_ENABLE BIT(2)
#define VPU_MAFBC_S1_ENABLE BIT(1)
#define VPU_MAFBC_S0_ENABLE BIT(0)
#define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S0 0x3a10
#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S0 0x3a11
#define VPU_MAFBC_FORMAT_SPECIFIER_S0 0x3a12
#define VPU_MAFBC_PAYLOAD_LIMIT_EN BIT(19)
#define VPU_MAFBC_TILED_HEADER_EN BIT(18)
#define VPU_MAFBC_SUPER_BLOCK_ASPECT GENMASK(17, 16)
#define VPU_MAFBC_BLOCK_SPLIT BIT(9)
#define VPU_MAFBC_YUV_TRANSFORM BIT(8)
#define VPU_MAFBC_PIXEL_FORMAT GENMASK(3, 0)
#define VPU_MAFBC_BUFFER_WIDTH_S0 0x3a13
#define VPU_MAFBC_BUFFER_HEIGHT_S0 0x3a14
#define VPU_MAFBC_BOUNDING_BOX_X_START_S0 0x3a15
@ -1631,6 +1687,8 @@
#define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S0 0x3a1a
#define VPU_MAFBC_OUTPUT_BUF_STRIDE_S0 0x3a1b
#define VPU_MAFBC_PREFETCH_CFG_S0 0x3a1c
#define VPU_MAFBC_PREFETCH_READ_DIRECTION_Y BIT(1)
#define VPU_MAFBC_PREFETCH_READ_DIRECTION_X BIT(0)
#define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S1 0x3a30
#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S1 0x3a31
@ -1677,7 +1735,11 @@
#define DOLBY_PATH_CTRL 0x1a0c
#define DOLBY_BYPASS_EN(val) (val & 0xf)
#define OSD_PATH_MISC_CTRL 0x1a0e
#define OSD_PATH_OSD_AXI_SEL_OSD1_AFBCD BIT(4)
#define OSD_PATH_OSD_AXI_SEL_OSD2_AFBCD BIT(5)
#define OSD_PATH_OSD_AXI_SEL_OSD3_AFBCD BIT(6)
#define MALI_AFBCD_TOP_CTRL 0x1a0f
#define MALI_AFBCD_MANUAL_RESET BIT(23)
#define VIU_OSD_BLEND_CTRL 0x39b0
#define VIU_OSD_BLEND_REORDER(dest, src) ((src) << (dest * 4))

15
drivers/gpu/drm/meson/meson_viu.h
View File

@ -10,6 +10,8 @@
#define __MESON_VIU_H
/* OSDx_BLKx_CFG */
#define OSD_MALI_SRC_EN BIT(30)
#define OSD_CANVAS_SEL 16
#define OSD_ENDIANNESS_LE BIT(15)
@ -33,19 +35,32 @@
#define OSD_COLOR_MATRIX_16_RGB655 (0x00 << 2)
#define OSD_COLOR_MATRIX_16_RGB565 (0x04 << 2)
#define OSD_MALI_COLOR_MODE_R8 (0 << 8)
#define OSD_MALI_COLOR_MODE_YUV422 (1 << 8)
#define OSD_MALI_COLOR_MODE_RGB565 (2 << 8)
#define OSD_MALI_COLOR_MODE_RGBA5551 (3 << 8)
#define OSD_MALI_COLOR_MODE_RGBA4444 (4 << 8)
#define OSD_MALI_COLOR_MODE_RGBA8888 (5 << 8)
#define OSD_MALI_COLOR_MODE_RGB888 (7 << 8)
#define OSD_MALI_COLOR_MODE_YUV422_10B (8 << 8)
#define OSD_MALI_COLOR_MODE_RGBA1010102 (9 << 8)
#define OSD_INTERLACE_ENABLED BIT(1)
#define OSD_INTERLACE_ODD BIT(0)
#define OSD_INTERLACE_EVEN (0)
/* OSDx_CTRL_STAT */
#define OSD_ENABLE BIT(21)
#define OSD_MEM_LINEAR_ADDR BIT(2)
#define OSD_BLK0_ENABLE BIT(0)
#define OSD_GLOBAL_ALPHA_SHIFT 12
/* OSDx_CTRL_STAT2 */
#define OSD_DPATH_MALI_AFBCD BIT(15)
#define OSD_REPLACE_EN BIT(14)
#define OSD_REPLACE_SHIFT 6
#define OSD_PENDING_STAT_CLEAN BIT(1)
void meson_viu_osd1_reset(struct meson_drm *priv);
void meson_viu_init(struct meson_drm *priv);