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[ARM] 3443/1: [S3C2410] Improve IRQ entry code
Patch from Ben Dooks Remove the old debug from the IRQ entry code, update the comments on the handling of the IRQ registers. The message "bad interrupt offset" is removed as it is only helpful for debugging, and can cause printk() flooding when under load. Make the code to deal with GPIO interrupts faster, and use the same path to deal with unexplained results from the IRQ registers. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Ben Dooks
Russell King
parent
23759dc643
commit
26f91fd54d
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@ -6,116 +6,83 @@
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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/* We have a problem that the INTOFFSET register does not always
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* show one interrupt. Occasionally we get two interrupts through
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* the prioritiser, and this causes the INTOFFSET register to show
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* what looks like the logical-or of the two interrupt numbers.
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*
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* Thanks to Klaus, Shannon, et al for helping to debug this problem
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*/
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#define INTPND (0x10)
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#define INTOFFSET (0x14)
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#define EXTINTPEND (0xa8)
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#define EXTINTMASK (0xa4)
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* Modifications:
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* 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA
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*/
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#include <asm/hardware.h>
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#include <asm/arch/irqs.h>
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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mov \tmp, #S3C24XX_VA_IRQ
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ldr \irqnr, [ \tmp, #0x14 ] @ get irq no
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30000:
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teq \irqnr, #4
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teqne \irqnr, #5
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beq 1002f @ external irq reg
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mov \base, #S3C24XX_VA_IRQ
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@ debug check to see if interrupt reported is the same
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@ as the offset....
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ldr \irqstat, [ \base, #INTPND]
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bics \irqnr, \irqstat, #3<<4 @@ only an GPIO IRQ
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beq 2000f
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teq \irqnr, #0
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beq 20002f
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ldr \irqstat, [ \tmp, #0x10 ] @ INTPND
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mov \irqstat, \irqstat, lsr \irqnr
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tst \irqstat, #1
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bne 20002f
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@@ try the interrupt offset register, since it is there
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/* debug/warning if we get an invalud response from the
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* INTOFFSET register */
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#if 1
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stmfd r13!, { r0 - r4 , r8-r12, r14 }
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ldr r1, [ \tmp, #0x14 ] @ INTOFFSET
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ldr r2, [ \tmp, #0x10 ] @ INTPND
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ldr r3, [ \tmp, #0x00 ] @ SRCPND
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adr r0, 20003f
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bl printk
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b 20004f
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ldr \irqnr, [ \base, #INTOFFSET ]
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mov \tmp, #1
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tst \irqstat, \tmp, lsl \irqnr
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addne \irqnr, \irqnr, #IRQ_EINT0
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bne 1001f
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20003:
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.ascii "<7>irq: err - bad offset %d, intpnd=%08x, srcpnd=%08x\n"
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.byte 0
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.align 4
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20004:
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mov r1, #1
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mov \tmp, #S3C24XX_VA_IRQ
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ldmfd r13!, { r0 - r4 , r8-r12, r14 }
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#endif
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@@ the number specified is not a valid irq, so try
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@@ and work it out for ourselves
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@ try working out interrupt number for ourselves
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mov \irqnr, #0
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ldr \irqstat, [ \tmp, #0x10 ] @ INTPND
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10021:
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movs \irqstat, \irqstat, lsr#1
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bcs 30000b @ try and re-start the proccess
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add \irqnr, \irqnr, #1
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cmp \irqnr, #32
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ble 10021b
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mov \irqnr, #IRQ_EINT0 @@ start here
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b 3000f
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@ found no interrupt, set Z flag and leave
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movs \irqnr, #0
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b 1001f
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2000:
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@@ load the GPIO interrupt register, and check it
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20005:
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20002: @ exit
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@ we base the s3c2410x interrupts at 16 and above to allow
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@ isa peripherals to have their standard interrupts, also
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@ ensure that Z flag is un-set on exit
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add \tmp, \base, #S3C24XX_VA_GPIO - S3C24XX_VA_IRQ
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ldr \irqstat, [ \tmp, # EXTINTPEND ]
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ldr \irqnr, [ \tmp, # EXTINTMASK ]
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bics \irqstat, \irqstat, \irqnr
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beq 1001f
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@ note, we cannot be sure if we get IRQ_EINT0 (0) that
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@ there is simply no interrupt pending, so in all other
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@ cases we jump to say we have found something, otherwise
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@ we check to see if the interrupt really is assrted
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adds \irqnr, \irqnr, #IRQ_EINT0
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teq \irqnr, #IRQ_EINT0
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bne 1001f @ exit
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ldr \irqstat, [ \tmp, #0x10 ] @ INTPND
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teq \irqstat, #0
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moveq \irqnr, #0
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b 1001f
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mov \irqnr, #(IRQ_EINT4 - 4)
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@ we get here from no main or external interrupts pending
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1002:
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add \tmp, \tmp, #S3C24XX_VA_GPIO - S3C24XX_VA_IRQ
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ldr \irqstat, [ \tmp, # 0xa8 ] @ EXTINTPEND
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ldr \irqnr, [ \tmp, # 0xa4 ] @ EXTINTMASK
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@@ work out which irq (if any) we got
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3000:
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movs \tmp, \irqstat, lsl#16
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addeq \irqnr, \irqnr, #16
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moveq \irqstat, \irqstat, lsr#16
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tst \irqstat, #0xff
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addeq \irqnr, \irqnr, #8
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moveq \irqstat, \irqstat, lsr#8
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tst \irqstat, #0xf
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addeq \irqnr, \irqnr, #4
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moveq \irqstat, \irqstat, lsr#4
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tst \irqstat, #0x3
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addeq \irqnr, \irqnr, #2
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moveq \irqstat, \irqstat, lsr#2
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tst \irqstat, #0x1
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addeq \irqnr, \irqnr, #1
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bic \irqstat, \irqstat, \irqnr @ clear masked irqs
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@@ we have the value
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movs \irqnr, \irqnr
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mov \irqnr, #IRQ_EINT4 @ start extint nos
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mov \irqstat, \irqstat, lsr#4 @ ignore bottom 4 bits
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10021:
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movs \irqstat, \irqstat, lsr#1
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bcs 1004f
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add \irqnr, \irqnr, #1
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cmp \irqnr, #IRQ_EINT23
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ble 10021b
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@ found no interrupt, set Z flag and leave
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movs \irqnr, #0
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1004: @ ensure Z flag clear in case our MOVS shifted out the last bit
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teq \irqnr, #0
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1001:
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@ exit irq routine
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.endm
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@@ exit here, Z flag unset if IRQ
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.endm
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/* currently don't need an disable_fiq macro */
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.macro disable_fiq
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.endm
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