mirror of https://gitee.com/openkylin/linux.git
cxgb4: print ULD queue information managed by LLD
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Rahul Lakkireddy
David S. Miller
parent
1d4b016f02
commit
27defe9d8f
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@ -2474,16 +2474,64 @@ static inline struct port_info *ethqset2pinfo(struct adapter *adap, int qset)
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return NULL;
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}
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static int sge_qinfo_uld_txq_entries(const struct adapter *adap, int uld)
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{
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const struct sge_uld_txq_info *utxq_info = adap->sge.uld_txq_info[uld];
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if (!utxq_info)
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return 0;
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return DIV_ROUND_UP(utxq_info->ntxq, 4);
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}
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static int sge_qinfo_uld_rspq_entries(const struct adapter *adap, int uld,
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bool ciq)
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{
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const struct sge_uld_rxq_info *urxq_info = adap->sge.uld_rxq_info[uld];
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if (!urxq_info)
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return 0;
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return ciq ? DIV_ROUND_UP(urxq_info->nciq, 4) :
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DIV_ROUND_UP(urxq_info->nrxq, 4);
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}
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static int sge_qinfo_uld_rxq_entries(const struct adapter *adap, int uld)
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{
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return sge_qinfo_uld_rspq_entries(adap, uld, false);
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}
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static int sge_qinfo_uld_ciq_entries(const struct adapter *adap, int uld)
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{
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return sge_qinfo_uld_rspq_entries(adap, uld, true);
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}
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static int sge_qinfo_show(struct seq_file *seq, void *v)
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{
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int uld_rxq_entries[CXGB4_ULD_MAX] = { 0 };
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int uld_ciq_entries[CXGB4_ULD_MAX] = { 0 };
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int uld_txq_entries[CXGB4_TX_MAX] = { 0 };
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const struct sge_uld_txq_info *utxq_info;
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const struct sge_uld_rxq_info *urxq_info;
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struct adapter *adap = seq->private;
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int eth_entries = DIV_ROUND_UP(adap->sge.ethqsets, 4);
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int ofld_entries = DIV_ROUND_UP(adap->sge.ofldqsets, 4);
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int ctrl_entries = DIV_ROUND_UP(MAX_CTRL_QUEUES, 4);
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int i, r = (uintptr_t)v - 1;
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int ofld_idx = r - eth_entries;
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int ctrl_idx = ofld_idx - ofld_entries;
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int fq_idx = ctrl_idx - ctrl_entries;
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int i, n, r = (uintptr_t)v - 1;
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int eth_entries, ctrl_entries;
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struct sge *s = &adap->sge;
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eth_entries = DIV_ROUND_UP(adap->sge.ethqsets, 4);
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ctrl_entries = DIV_ROUND_UP(MAX_CTRL_QUEUES, 4);
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mutex_lock(&uld_mutex);
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if (s->uld_txq_info)
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for (i = 0; i < ARRAY_SIZE(uld_txq_entries); i++)
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uld_txq_entries[i] = sge_qinfo_uld_txq_entries(adap, i);
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if (s->uld_rxq_info) {
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for (i = 0; i < ARRAY_SIZE(uld_rxq_entries); i++) {
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uld_rxq_entries[i] = sge_qinfo_uld_rxq_entries(adap, i);
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uld_ciq_entries[i] = sge_qinfo_uld_ciq_entries(adap, i);
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}
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}
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if (r)
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seq_putc(seq, '\n');
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@ -2505,9 +2553,10 @@ do { \
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if (r < eth_entries) {
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int base_qset = r * 4;
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const struct sge_eth_rxq *rx = &adap->sge.ethrxq[base_qset];
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const struct sge_eth_txq *tx = &adap->sge.ethtxq[base_qset];
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int n = min(4, adap->sge.ethqsets - 4 * r);
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const struct sge_eth_rxq *rx = &s->ethrxq[base_qset];
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const struct sge_eth_txq *tx = &s->ethtxq[base_qset];
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n = min(4, s->ethqsets - 4 * r);
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S("QType:", "Ethernet");
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S("Interface:",
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@ -2532,8 +2581,7 @@ do { \
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R("RspQ CIDX:", rspq.cidx);
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R("RspQ Gen:", rspq.gen);
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S3("u", "Intr delay:", qtimer_val(adap, &rx[i].rspq));
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S3("u", "Intr pktcnt:",
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adap->sge.counter_val[rx[i].rspq.pktcnt_idx]);
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S3("u", "Intr pktcnt:", s->counter_val[rx[i].rspq.pktcnt_idx]);
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R("FL ID:", fl.cntxt_id);
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R("FL size:", fl.size - 8);
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R("FL pend:", fl.pend_cred);
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@ -2558,9 +2606,196 @@ do { \
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RL("FLLow:", fl.low);
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RL("FLStarving:", fl.starving);
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} else if (ctrl_idx < ctrl_entries) {
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const struct sge_ctrl_txq *tx = &adap->sge.ctrlq[ctrl_idx * 4];
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int n = min(4, adap->params.nports - 4 * ctrl_idx);
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goto unlock;
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}
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r -= eth_entries;
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if (r < uld_txq_entries[CXGB4_TX_OFLD]) {
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const struct sge_uld_txq *tx;
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utxq_info = s->uld_txq_info[CXGB4_TX_OFLD];
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tx = &utxq_info->uldtxq[r * 4];
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n = min(4, utxq_info->ntxq - 4 * r);
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S("QType:", "OFLD-TXQ");
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T("TxQ ID:", q.cntxt_id);
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T("TxQ size:", q.size);
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T("TxQ inuse:", q.in_use);
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T("TxQ CIDX:", q.cidx);
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T("TxQ PIDX:", q.pidx);
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goto unlock;
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}
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r -= uld_txq_entries[CXGB4_TX_OFLD];
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if (r < uld_rxq_entries[CXGB4_ULD_RDMA]) {
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const struct sge_ofld_rxq *rx;
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urxq_info = s->uld_rxq_info[CXGB4_ULD_RDMA];
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rx = &urxq_info->uldrxq[r * 4];
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n = min(4, urxq_info->nrxq - 4 * r);
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S("QType:", "RDMA-CPL");
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S("Interface:",
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rx[i].rspq.netdev ? rx[i].rspq.netdev->name : "N/A");
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R("RspQ ID:", rspq.abs_id);
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R("RspQ size:", rspq.size);
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R("RspQE size:", rspq.iqe_len);
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R("RspQ CIDX:", rspq.cidx);
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R("RspQ Gen:", rspq.gen);
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S3("u", "Intr delay:", qtimer_val(adap, &rx[i].rspq));
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S3("u", "Intr pktcnt:", s->counter_val[rx[i].rspq.pktcnt_idx]);
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R("FL ID:", fl.cntxt_id);
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R("FL size:", fl.size - 8);
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R("FL pend:", fl.pend_cred);
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R("FL avail:", fl.avail);
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R("FL PIDX:", fl.pidx);
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R("FL CIDX:", fl.cidx);
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goto unlock;
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}
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r -= uld_rxq_entries[CXGB4_ULD_RDMA];
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if (r < uld_ciq_entries[CXGB4_ULD_RDMA]) {
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const struct sge_ofld_rxq *rx;
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int ciq_idx = 0;
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urxq_info = s->uld_rxq_info[CXGB4_ULD_RDMA];
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ciq_idx = urxq_info->nrxq + (r * 4);
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rx = &urxq_info->uldrxq[ciq_idx];
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n = min(4, urxq_info->nciq - 4 * r);
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S("QType:", "RDMA-CIQ");
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S("Interface:",
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rx[i].rspq.netdev ? rx[i].rspq.netdev->name : "N/A");
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R("RspQ ID:", rspq.abs_id);
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R("RspQ size:", rspq.size);
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R("RspQE size:", rspq.iqe_len);
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R("RspQ CIDX:", rspq.cidx);
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R("RspQ Gen:", rspq.gen);
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S3("u", "Intr delay:", qtimer_val(adap, &rx[i].rspq));
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S3("u", "Intr pktcnt:", s->counter_val[rx[i].rspq.pktcnt_idx]);
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goto unlock;
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}
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r -= uld_ciq_entries[CXGB4_ULD_RDMA];
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if (r < uld_rxq_entries[CXGB4_ULD_ISCSI]) {
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const struct sge_ofld_rxq *rx;
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urxq_info = s->uld_rxq_info[CXGB4_ULD_ISCSI];
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rx = &urxq_info->uldrxq[r * 4];
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n = min(4, urxq_info->nrxq - 4 * r);
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S("QType:", "iSCSI");
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R("RspQ ID:", rspq.abs_id);
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R("RspQ size:", rspq.size);
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R("RspQE size:", rspq.iqe_len);
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R("RspQ CIDX:", rspq.cidx);
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R("RspQ Gen:", rspq.gen);
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S3("u", "Intr delay:", qtimer_val(adap, &rx[i].rspq));
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S3("u", "Intr pktcnt:", s->counter_val[rx[i].rspq.pktcnt_idx]);
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R("FL ID:", fl.cntxt_id);
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R("FL size:", fl.size - 8);
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R("FL pend:", fl.pend_cred);
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R("FL avail:", fl.avail);
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R("FL PIDX:", fl.pidx);
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R("FL CIDX:", fl.cidx);
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goto unlock;
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}
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r -= uld_rxq_entries[CXGB4_ULD_ISCSI];
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if (r < uld_rxq_entries[CXGB4_ULD_ISCSIT]) {
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const struct sge_ofld_rxq *rx;
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urxq_info = s->uld_rxq_info[CXGB4_ULD_ISCSIT];
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rx = &urxq_info->uldrxq[r * 4];
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n = min(4, urxq_info->nrxq - 4 * r);
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S("QType:", "iSCSIT");
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R("RspQ ID:", rspq.abs_id);
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R("RspQ size:", rspq.size);
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R("RspQE size:", rspq.iqe_len);
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R("RspQ CIDX:", rspq.cidx);
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R("RspQ Gen:", rspq.gen);
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S3("u", "Intr delay:", qtimer_val(adap, &rx[i].rspq));
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S3("u", "Intr pktcnt:", s->counter_val[rx[i].rspq.pktcnt_idx]);
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R("FL ID:", fl.cntxt_id);
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R("FL size:", fl.size - 8);
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R("FL pend:", fl.pend_cred);
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R("FL avail:", fl.avail);
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R("FL PIDX:", fl.pidx);
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R("FL CIDX:", fl.cidx);
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goto unlock;
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}
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r -= uld_rxq_entries[CXGB4_ULD_ISCSIT];
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if (r < uld_rxq_entries[CXGB4_ULD_TLS]) {
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const struct sge_ofld_rxq *rx;
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urxq_info = s->uld_rxq_info[CXGB4_ULD_TLS];
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rx = &urxq_info->uldrxq[r * 4];
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n = min(4, urxq_info->nrxq - 4 * r);
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S("QType:", "TLS");
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R("RspQ ID:", rspq.abs_id);
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R("RspQ size:", rspq.size);
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R("RspQE size:", rspq.iqe_len);
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R("RspQ CIDX:", rspq.cidx);
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R("RspQ Gen:", rspq.gen);
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S3("u", "Intr delay:", qtimer_val(adap, &rx[i].rspq));
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S3("u", "Intr pktcnt:", s->counter_val[rx[i].rspq.pktcnt_idx]);
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R("FL ID:", fl.cntxt_id);
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R("FL size:", fl.size - 8);
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R("FL pend:", fl.pend_cred);
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R("FL avail:", fl.avail);
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R("FL PIDX:", fl.pidx);
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R("FL CIDX:", fl.cidx);
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goto unlock;
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}
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r -= uld_rxq_entries[CXGB4_ULD_TLS];
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if (r < uld_txq_entries[CXGB4_TX_CRYPTO]) {
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const struct sge_ofld_rxq *rx;
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const struct sge_uld_txq *tx;
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utxq_info = s->uld_txq_info[CXGB4_TX_CRYPTO];
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urxq_info = s->uld_rxq_info[CXGB4_ULD_CRYPTO];
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tx = &utxq_info->uldtxq[r * 4];
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rx = &urxq_info->uldrxq[r * 4];
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n = min(4, utxq_info->ntxq - 4 * r);
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S("QType:", "Crypto");
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T("TxQ ID:", q.cntxt_id);
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T("TxQ size:", q.size);
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T("TxQ inuse:", q.in_use);
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T("TxQ CIDX:", q.cidx);
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T("TxQ PIDX:", q.pidx);
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R("RspQ ID:", rspq.abs_id);
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R("RspQ size:", rspq.size);
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R("RspQE size:", rspq.iqe_len);
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R("RspQ CIDX:", rspq.cidx);
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R("RspQ Gen:", rspq.gen);
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S3("u", "Intr delay:", qtimer_val(adap, &rx[i].rspq));
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S3("u", "Intr pktcnt:", s->counter_val[rx[i].rspq.pktcnt_idx]);
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R("FL ID:", fl.cntxt_id);
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R("FL size:", fl.size - 8);
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R("FL pend:", fl.pend_cred);
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R("FL avail:", fl.avail);
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R("FL PIDX:", fl.pidx);
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R("FL CIDX:", fl.cidx);
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goto unlock;
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}
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r -= uld_txq_entries[CXGB4_TX_CRYPTO];
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if (r < ctrl_entries) {
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const struct sge_ctrl_txq *tx = &s->ctrlq[r * 4];
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n = min(4, adap->params.nports - 4 * r);
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S("QType:", "Control");
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T("TxQ ID:", q.cntxt_id);
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@ -2570,8 +2805,13 @@ do { \
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T("TxQ PIDX:", q.pidx);
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TL("TxQFull:", q.stops);
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TL("TxQRestarts:", q.restarts);
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} else if (fq_idx == 0) {
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const struct sge_rspq *evtq = &adap->sge.fw_evtq;
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goto unlock;
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}
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r -= ctrl_entries;
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if (r < 1) {
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const struct sge_rspq *evtq = &s->fw_evtq;
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seq_printf(seq, "%-12s %16s\n", "QType:", "FW event queue");
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seq_printf(seq, "%-12s %16u\n", "RspQ ID:", evtq->abs_id);
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@ -2582,8 +2822,13 @@ do { \
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seq_printf(seq, "%-12s %16u\n", "Intr delay:",
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qtimer_val(adap, evtq));
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seq_printf(seq, "%-12s %16u\n", "Intr pktcnt:",
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adap->sge.counter_val[evtq->pktcnt_idx]);
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s->counter_val[evtq->pktcnt_idx]);
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goto unlock;
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}
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unlock:
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mutex_unlock(&uld_mutex);
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#undef R
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#undef RL
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#undef T
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@ -2597,8 +2842,21 @@ do { \
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static int sge_queue_entries(const struct adapter *adap)
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{
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int tot_uld_entries = 0;
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int i;
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mutex_lock(&uld_mutex);
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for (i = 0; i < CXGB4_TX_MAX; i++)
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tot_uld_entries += sge_qinfo_uld_txq_entries(adap, i);
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for (i = 0; i < CXGB4_ULD_MAX; i++) {
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tot_uld_entries += sge_qinfo_uld_rxq_entries(adap, i);
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tot_uld_entries += sge_qinfo_uld_ciq_entries(adap, i);
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}
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mutex_unlock(&uld_mutex);
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return DIV_ROUND_UP(adap->sge.ethqsets, 4) +
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DIV_ROUND_UP(adap->sge.ofldqsets, 4) +
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tot_uld_entries +
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DIV_ROUND_UP(MAX_CTRL_QUEUES, 4) + 1;
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}
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