mirror of https://gitee.com/openkylin/linux.git
[SCSI] hptiop: Support HighPoint RR4520/RR4522 HBA
Support IOP RR4520/RR4522 which are based on Marvell frey. Signed-off-by: HighPoint Linux Team <linux@highpoint-tech.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
This commit is contained in:
HighPoint Linux Team
James Bottomley
parent
b83908ce84
commit
286aa03166
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@ -37,7 +37,7 @@ For Intel IOP based adapters, the controller IOP is accessed via PCI BAR0:
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0x40 Inbound Queue Port
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0x44 Outbound Queue Port
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For Marvell IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1:
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For Marvell not Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1:
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BAR0 offset Register
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0x20400 Inbound Doorbell Register
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@ -55,9 +55,31 @@ For Marvell IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1:
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0x40-0x1040 Inbound Queue
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0x1040-0x2040 Outbound Queue
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For Marvell Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1:
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I/O Request Workflow
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----------------------
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BAR0 offset Register
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0x0 IOP configuration information.
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BAR1 offset Register
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0x4000 Inbound List Base Address Low
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0x4004 Inbound List Base Address High
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0x4018 Inbound List Write Pointer
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0x402C Inbound List Configuration and Control
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0x4050 Outbound List Base Address Low
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0x4054 Outbound List Base Address High
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0x4058 Outbound List Copy Pointer Shadow Base Address Low
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0x405C Outbound List Copy Pointer Shadow Base Address High
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0x4088 Outbound List Interrupt Cause
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0x408C Outbound List Interrupt Enable
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0x1020C PCIe Function 0 Interrupt Enable
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0x10400 PCIe Function 0 to CPU Message A
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0x10420 CPU to PCIe Function 0 Message A
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0x10480 CPU to PCIe Function 0 Doorbell
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0x10484 CPU to PCIe Function 0 Doorbell Enable
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I/O Request Workflow of Not Marvell Frey
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------------------------------------------
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All queued requests are handled via inbound/outbound queue port.
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A request packet can be allocated in either IOP or host memory.
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@ -101,6 +123,45 @@ register 0. An outbound message with the same value indicates the completion
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of an inbound message.
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I/O Request Workflow of Marvell Frey
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--------------------------------------
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All queued requests are handled via inbound/outbound list.
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To send a request to the controller:
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- Allocate a free request in host DMA coherent memory.
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Requests allocated in host memory must be aligned on 32-bytes boundary.
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- Fill the request with index of the request in the flag.
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Fill a free inbound list unit with the physical address and the size of
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the request.
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Set up the inbound list write pointer with the index of previous unit,
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round to 0 if the index reaches the supported count of requests.
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- Post the inbound list writer pointer to IOP.
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- The IOP process the request. When the request is completed, the flag of
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the request with or-ed IOPMU_QUEUE_MASK_HOST_BITS will be put into a
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free outbound list unit and the index of the outbound list unit will be
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put into the copy pointer shadow register. An outbound interrupt will be
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generated.
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- The host read the outbound list copy pointer shadow register and compare
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with previous saved read ponter N. If they are different, the host will
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read the (N+1)th outbound list unit.
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The host get the index of the request from the (N+1)th outbound list
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unit and complete the request.
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Non-queued requests (reset communication/reset/flush etc) can be sent via PCIe
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Function 0 to CPU Message A register. The CPU to PCIe Function 0 Message register
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with the same value indicates the completion of message.
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User-level Interface
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---------------------
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@ -112,7 +173,7 @@ The driver exposes following sysfs attributes:
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-----------------------------------------------------------------------------
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Copyright (C) 2006-2009 HighPoint Technologies, Inc. All Rights Reserved.
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Copyright (C) 2006-2012 HighPoint Technologies, Inc. All Rights Reserved.
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This file is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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@ -1,6 +1,6 @@
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/*
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* HighPoint RR3xxx/4xxx controller driver for Linux
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* Copyright (C) 2006-2009 HighPoint Technologies, Inc. All Rights Reserved.
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* Copyright (C) 2006-2012 HighPoint Technologies, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -42,7 +42,7 @@ MODULE_DESCRIPTION("HighPoint RocketRAID 3xxx/4xxx Controller Driver");
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static char driver_name[] = "hptiop";
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static const char driver_name_long[] = "RocketRAID 3xxx/4xxx Controller driver";
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static const char driver_ver[] = "v1.6 (091225)";
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static const char driver_ver[] = "v1.8";
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static int iop_send_sync_msg(struct hptiop_hba *hba, u32 msg, u32 millisec);
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static void hptiop_finish_scsi_req(struct hptiop_hba *hba, u32 tag,
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@ -77,6 +77,11 @@ static int iop_wait_ready_mv(struct hptiop_hba *hba, u32 millisec)
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return iop_send_sync_msg(hba, IOPMU_INBOUND_MSG0_NOP, millisec);
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}
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static int iop_wait_ready_mvfrey(struct hptiop_hba *hba, u32 millisec)
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{
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return iop_send_sync_msg(hba, IOPMU_INBOUND_MSG0_NOP, millisec);
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}
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static void hptiop_request_callback_itl(struct hptiop_hba *hba, u32 tag)
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{
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if (tag & IOPMU_QUEUE_ADDR_HOST_BIT)
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@ -230,6 +235,74 @@ static int iop_intr_mv(struct hptiop_hba *hba)
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return ret;
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}
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static void hptiop_request_callback_mvfrey(struct hptiop_hba *hba, u32 _tag)
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{
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u32 req_type = _tag & 0xf;
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struct hpt_iop_request_scsi_command *req;
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switch (req_type) {
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case IOP_REQUEST_TYPE_GET_CONFIG:
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case IOP_REQUEST_TYPE_SET_CONFIG:
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hba->msg_done = 1;
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break;
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case IOP_REQUEST_TYPE_SCSI_COMMAND:
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req = hba->reqs[(_tag >> 4) & 0xff].req_virt;
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if (likely(_tag & IOPMU_QUEUE_REQUEST_RESULT_BIT))
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req->header.result = IOP_RESULT_SUCCESS;
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hptiop_finish_scsi_req(hba, (_tag >> 4) & 0xff, req);
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break;
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default:
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break;
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}
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}
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static int iop_intr_mvfrey(struct hptiop_hba *hba)
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{
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u32 _tag, status, cptr, cur_rptr;
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int ret = 0;
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if (hba->initialized)
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writel(0, &(hba->u.mvfrey.mu->pcie_f0_int_enable));
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status = readl(&(hba->u.mvfrey.mu->f0_doorbell));
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if (status) {
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writel(status, &(hba->u.mvfrey.mu->f0_doorbell));
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if (status & CPU_TO_F0_DRBL_MSG_BIT) {
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u32 msg = readl(&(hba->u.mvfrey.mu->cpu_to_f0_msg_a));
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dprintk("received outbound msg %x\n", msg);
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hptiop_message_callback(hba, msg);
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}
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ret = 1;
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}
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status = readl(&(hba->u.mvfrey.mu->isr_cause));
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if (status) {
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writel(status, &(hba->u.mvfrey.mu->isr_cause));
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do {
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cptr = *hba->u.mvfrey.outlist_cptr & 0xff;
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cur_rptr = hba->u.mvfrey.outlist_rptr;
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while (cur_rptr != cptr) {
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cur_rptr++;
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if (cur_rptr == hba->u.mvfrey.list_count)
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cur_rptr = 0;
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_tag = hba->u.mvfrey.outlist[cur_rptr].val;
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BUG_ON(!(_tag & IOPMU_QUEUE_MASK_HOST_BITS));
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hptiop_request_callback_mvfrey(hba, _tag);
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ret = 1;
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}
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hba->u.mvfrey.outlist_rptr = cur_rptr;
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} while (cptr != (*hba->u.mvfrey.outlist_cptr & 0xff));
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}
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if (hba->initialized)
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writel(0x1010, &(hba->u.mvfrey.mu->pcie_f0_int_enable));
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return ret;
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}
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static int iop_send_sync_request_itl(struct hptiop_hba *hba,
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void __iomem *_req, u32 millisec)
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{
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@ -272,6 +345,26 @@ static int iop_send_sync_request_mv(struct hptiop_hba *hba,
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return -1;
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}
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static int iop_send_sync_request_mvfrey(struct hptiop_hba *hba,
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u32 size_bits, u32 millisec)
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{
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struct hpt_iop_request_header *reqhdr =
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hba->u.mvfrey.internal_req.req_virt;
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u32 i;
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hba->msg_done = 0;
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reqhdr->flags |= cpu_to_le32(IOP_REQUEST_FLAG_SYNC_REQUEST);
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hba->ops->post_req(hba, &(hba->u.mvfrey.internal_req));
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for (i = 0; i < millisec; i++) {
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iop_intr_mvfrey(hba);
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if (hba->msg_done)
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break;
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msleep(1);
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}
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return hba->msg_done ? 0 : -1;
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}
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static void hptiop_post_msg_itl(struct hptiop_hba *hba, u32 msg)
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{
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writel(msg, &hba->u.itl.iop->inbound_msgaddr0);
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@ -285,11 +378,18 @@ static void hptiop_post_msg_mv(struct hptiop_hba *hba, u32 msg)
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readl(&hba->u.mv.regs->inbound_doorbell);
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}
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static void hptiop_post_msg_mvfrey(struct hptiop_hba *hba, u32 msg)
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{
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writel(msg, &(hba->u.mvfrey.mu->f0_to_cpu_msg_a));
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readl(&(hba->u.mvfrey.mu->f0_to_cpu_msg_a));
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}
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static int iop_send_sync_msg(struct hptiop_hba *hba, u32 msg, u32 millisec)
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{
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u32 i;
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hba->msg_done = 0;
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hba->ops->disable_intr(hba);
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hba->ops->post_msg(hba, msg);
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for (i = 0; i < millisec; i++) {
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@ -301,6 +401,7 @@ static int iop_send_sync_msg(struct hptiop_hba *hba, u32 msg, u32 millisec)
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msleep(1);
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}
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hba->ops->enable_intr(hba);
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return hba->msg_done? 0 : -1;
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}
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@ -354,6 +455,28 @@ static int iop_get_config_mv(struct hptiop_hba *hba,
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return 0;
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}
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static int iop_get_config_mvfrey(struct hptiop_hba *hba,
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struct hpt_iop_request_get_config *config)
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{
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struct hpt_iop_request_get_config *info = hba->u.mvfrey.config;
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if (info->header.size != sizeof(struct hpt_iop_request_get_config) ||
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info->header.type != IOP_REQUEST_TYPE_GET_CONFIG)
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return -1;
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config->interface_version = info->interface_version;
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config->firmware_version = info->firmware_version;
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config->max_requests = info->max_requests;
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config->request_size = info->request_size;
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config->max_sg_count = info->max_sg_count;
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config->data_transfer_length = info->data_transfer_length;
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config->alignment_mask = info->alignment_mask;
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config->max_devices = info->max_devices;
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config->sdram_size = info->sdram_size;
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return 0;
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}
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static int iop_set_config_itl(struct hptiop_hba *hba,
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struct hpt_iop_request_set_config *config)
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{
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@ -408,6 +531,29 @@ static int iop_set_config_mv(struct hptiop_hba *hba,
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return 0;
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}
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static int iop_set_config_mvfrey(struct hptiop_hba *hba,
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struct hpt_iop_request_set_config *config)
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{
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struct hpt_iop_request_set_config *req =
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hba->u.mvfrey.internal_req.req_virt;
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memcpy(req, config, sizeof(struct hpt_iop_request_set_config));
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req->header.flags = cpu_to_le32(IOP_REQUEST_FLAG_OUTPUT_CONTEXT);
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req->header.type = cpu_to_le32(IOP_REQUEST_TYPE_SET_CONFIG);
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req->header.size =
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cpu_to_le32(sizeof(struct hpt_iop_request_set_config));
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req->header.result = cpu_to_le32(IOP_RESULT_PENDING);
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req->header.context = cpu_to_le32(IOP_REQUEST_TYPE_SET_CONFIG<<5);
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req->header.context_hi32 = 0;
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if (iop_send_sync_request_mvfrey(hba, 0, 20000)) {
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dprintk("Set config send cmd failed\n");
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return -1;
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}
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return 0;
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}
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static void hptiop_enable_intr_itl(struct hptiop_hba *hba)
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{
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writel(~(IOPMU_OUTBOUND_INT_POSTQUEUE | IOPMU_OUTBOUND_INT_MSG0),
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@ -420,6 +566,13 @@ static void hptiop_enable_intr_mv(struct hptiop_hba *hba)
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&hba->u.mv.regs->outbound_intmask);
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}
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static void hptiop_enable_intr_mvfrey(struct hptiop_hba *hba)
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{
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writel(CPU_TO_F0_DRBL_MSG_BIT, &(hba->u.mvfrey.mu->f0_doorbell_enable));
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writel(0x1, &(hba->u.mvfrey.mu->isr_enable));
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writel(0x1010, &(hba->u.mvfrey.mu->pcie_f0_int_enable));
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}
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static int hptiop_initialize_iop(struct hptiop_hba *hba)
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{
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/* enable interrupts */
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@ -502,17 +655,39 @@ static int hptiop_map_pci_bar_mv(struct hptiop_hba *hba)
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return 0;
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}
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static int hptiop_map_pci_bar_mvfrey(struct hptiop_hba *hba)
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{
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hba->u.mvfrey.config = hptiop_map_pci_bar(hba, 0);
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if (hba->u.mvfrey.config == NULL)
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return -1;
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hba->u.mvfrey.mu = hptiop_map_pci_bar(hba, 2);
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if (hba->u.mvfrey.mu == NULL) {
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iounmap(hba->u.mvfrey.config);
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return -1;
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}
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return 0;
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}
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static void hptiop_unmap_pci_bar_mv(struct hptiop_hba *hba)
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{
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iounmap(hba->u.mv.regs);
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iounmap(hba->u.mv.mu);
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}
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static void hptiop_unmap_pci_bar_mvfrey(struct hptiop_hba *hba)
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{
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iounmap(hba->u.mvfrey.config);
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iounmap(hba->u.mvfrey.mu);
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}
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static void hptiop_message_callback(struct hptiop_hba *hba, u32 msg)
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{
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dprintk("iop message 0x%x\n", msg);
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if (msg == IOPMU_INBOUND_MSG0_NOP)
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if (msg == IOPMU_INBOUND_MSG0_NOP ||
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msg == IOPMU_INBOUND_MSG0_RESET_COMM)
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hba->msg_done = 1;
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if (!hba->initialized)
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@ -592,6 +767,7 @@ static void hptiop_finish_scsi_req(struct hptiop_hba *hba, u32 tag,
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memcpy(scp->sense_buffer, &req->sg_list,
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min_t(size_t, SCSI_SENSE_BUFFERSIZE,
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le32_to_cpu(req->dataxfer_length)));
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goto skip_resid;
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break;
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default:
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@ -599,6 +775,10 @@ static void hptiop_finish_scsi_req(struct hptiop_hba *hba, u32 tag,
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break;
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}
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scsi_set_resid(scp,
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scsi_bufflen(scp) - le32_to_cpu(req->dataxfer_length));
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skip_resid:
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dprintk("scsi_done(%p)\n", scp);
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scp->scsi_done(scp);
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free_req(hba, &hba->reqs[tag]);
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@ -692,7 +872,8 @@ static int hptiop_buildsgl(struct scsi_cmnd *scp, struct hpt_iopsg *psg)
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BUG_ON(HPT_SCP(scp)->sgcnt > hba->max_sg_descriptors);
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scsi_for_each_sg(scp, sg, HPT_SCP(scp)->sgcnt, idx) {
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psg[idx].pci_address = cpu_to_le64(sg_dma_address(sg));
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psg[idx].pci_address = cpu_to_le64(sg_dma_address(sg)) |
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hba->ops->host_phy_flag;
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psg[idx].size = cpu_to_le32(sg_dma_len(sg));
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psg[idx].eot = (idx == HPT_SCP(scp)->sgcnt - 1) ?
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cpu_to_le32(1) : 0;
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@ -751,6 +932,78 @@ static void hptiop_post_req_mv(struct hptiop_hba *hba,
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MVIOP_MU_QUEUE_ADDR_HOST_BIT | size_bit, hba);
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}
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static void hptiop_post_req_mvfrey(struct hptiop_hba *hba,
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struct hptiop_request *_req)
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{
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struct hpt_iop_request_header *reqhdr = _req->req_virt;
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u32 index;
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|
||||
reqhdr->flags |= cpu_to_le32(IOP_REQUEST_FLAG_OUTPUT_CONTEXT |
|
||||
IOP_REQUEST_FLAG_ADDR_BITS |
|
||||
((_req->req_shifted_phy >> 11) & 0xffff0000));
|
||||
reqhdr->context = cpu_to_le32(IOPMU_QUEUE_ADDR_HOST_BIT |
|
||||
(_req->index << 4) | reqhdr->type);
|
||||
reqhdr->context_hi32 = cpu_to_le32((_req->req_shifted_phy << 5) &
|
||||
0xffffffff);
|
||||
|
||||
hba->u.mvfrey.inlist_wptr++;
|
||||
index = hba->u.mvfrey.inlist_wptr & 0x3fff;
|
||||
|
||||
if (index == hba->u.mvfrey.list_count) {
|
||||
index = 0;
|
||||
hba->u.mvfrey.inlist_wptr &= ~0x3fff;
|
||||
hba->u.mvfrey.inlist_wptr ^= CL_POINTER_TOGGLE;
|
||||
}
|
||||
|
||||
hba->u.mvfrey.inlist[index].addr =
|
||||
(dma_addr_t)_req->req_shifted_phy << 5;
|
||||
hba->u.mvfrey.inlist[index].intrfc_len = (reqhdr->size + 3) / 4;
|
||||
writel(hba->u.mvfrey.inlist_wptr,
|
||||
&(hba->u.mvfrey.mu->inbound_write_ptr));
|
||||
readl(&(hba->u.mvfrey.mu->inbound_write_ptr));
|
||||
}
|
||||
|
||||
static int hptiop_reset_comm_itl(struct hptiop_hba *hba)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int hptiop_reset_comm_mv(struct hptiop_hba *hba)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int hptiop_reset_comm_mvfrey(struct hptiop_hba *hba)
|
||||
{
|
||||
u32 list_count = hba->u.mvfrey.list_count;
|
||||
|
||||
if (iop_send_sync_msg(hba, IOPMU_INBOUND_MSG0_RESET_COMM, 3000))
|
||||
return -1;
|
||||
|
||||
/* wait 100ms for MCU ready */
|
||||
msleep(100);
|
||||
|
||||
writel(cpu_to_le32(hba->u.mvfrey.inlist_phy & 0xffffffff),
|
||||
&(hba->u.mvfrey.mu->inbound_base));
|
||||
writel(cpu_to_le32((hba->u.mvfrey.inlist_phy >> 16) >> 16),
|
||||
&(hba->u.mvfrey.mu->inbound_base_high));
|
||||
|
||||
writel(cpu_to_le32(hba->u.mvfrey.outlist_phy & 0xffffffff),
|
||||
&(hba->u.mvfrey.mu->outbound_base));
|
||||
writel(cpu_to_le32((hba->u.mvfrey.outlist_phy >> 16) >> 16),
|
||||
&(hba->u.mvfrey.mu->outbound_base_high));
|
||||
|
||||
writel(cpu_to_le32(hba->u.mvfrey.outlist_cptr_phy & 0xffffffff),
|
||||
&(hba->u.mvfrey.mu->outbound_shadow_base));
|
||||
writel(cpu_to_le32((hba->u.mvfrey.outlist_cptr_phy >> 16) >> 16),
|
||||
&(hba->u.mvfrey.mu->outbound_shadow_base_high));
|
||||
|
||||
hba->u.mvfrey.inlist_wptr = (list_count - 1) | CL_POINTER_TOGGLE;
|
||||
*hba->u.mvfrey.outlist_cptr = (list_count - 1) | CL_POINTER_TOGGLE;
|
||||
hba->u.mvfrey.outlist_rptr = list_count - 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int hptiop_queuecommand_lck(struct scsi_cmnd *scp,
|
||||
void (*done)(struct scsi_cmnd *))
|
||||
{
|
||||
|
|
@ -771,14 +1024,15 @@ static int hptiop_queuecommand_lck(struct scsi_cmnd *scp,
|
|||
|
||||
_req->scp = scp;
|
||||
|
||||
dprintk("hptiop_queuecmd(scp=%p) %d/%d/%d/%d cdb=(%x-%x-%x) "
|
||||
dprintk("hptiop_queuecmd(scp=%p) %d/%d/%d/%d cdb=(%08x-%08x-%08x-%08x) "
|
||||
"req_index=%d, req=%p\n",
|
||||
scp,
|
||||
host->host_no, scp->device->channel,
|
||||
scp->device->id, scp->device->lun,
|
||||
((u32 *)scp->cmnd)[0],
|
||||
((u32 *)scp->cmnd)[1],
|
||||
((u32 *)scp->cmnd)[2],
|
||||
cpu_to_be32(((u32 *)scp->cmnd)[0]),
|
||||
cpu_to_be32(((u32 *)scp->cmnd)[1]),
|
||||
cpu_to_be32(((u32 *)scp->cmnd)[2]),
|
||||
cpu_to_be32(((u32 *)scp->cmnd)[3]),
|
||||
_req->index, _req->req_virt);
|
||||
|
||||
scp->result = 0;
|
||||
|
|
@ -933,6 +1187,11 @@ static struct scsi_host_template driver_template = {
|
|||
.change_queue_depth = hptiop_adjust_disk_queue_depth,
|
||||
};
|
||||
|
||||
static int hptiop_internal_memalloc_itl(struct hptiop_hba *hba)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int hptiop_internal_memalloc_mv(struct hptiop_hba *hba)
|
||||
{
|
||||
hba->u.mv.internal_req = dma_alloc_coherent(&hba->pcidev->dev,
|
||||
|
|
@ -943,6 +1202,63 @@ static int hptiop_internal_memalloc_mv(struct hptiop_hba *hba)
|
|||
return -1;
|
||||
}
|
||||
|
||||
static int hptiop_internal_memalloc_mvfrey(struct hptiop_hba *hba)
|
||||
{
|
||||
u32 list_count = readl(&hba->u.mvfrey.mu->inbound_conf_ctl);
|
||||
char *p;
|
||||
dma_addr_t phy;
|
||||
|
||||
BUG_ON(hba->max_request_size == 0);
|
||||
|
||||
if (list_count == 0) {
|
||||
BUG_ON(1);
|
||||
return -1;
|
||||
}
|
||||
|
||||
list_count >>= 16;
|
||||
|
||||
hba->u.mvfrey.list_count = list_count;
|
||||
hba->u.mvfrey.internal_mem_size = 0x800 +
|
||||
list_count * sizeof(struct mvfrey_inlist_entry) +
|
||||
list_count * sizeof(struct mvfrey_outlist_entry) +
|
||||
sizeof(int);
|
||||
|
||||
p = dma_alloc_coherent(&hba->pcidev->dev,
|
||||
hba->u.mvfrey.internal_mem_size, &phy, GFP_KERNEL);
|
||||
if (!p)
|
||||
return -1;
|
||||
|
||||
hba->u.mvfrey.internal_req.req_virt = p;
|
||||
hba->u.mvfrey.internal_req.req_shifted_phy = phy >> 5;
|
||||
hba->u.mvfrey.internal_req.scp = NULL;
|
||||
hba->u.mvfrey.internal_req.next = NULL;
|
||||
|
||||
p += 0x800;
|
||||
phy += 0x800;
|
||||
|
||||
hba->u.mvfrey.inlist = (struct mvfrey_inlist_entry *)p;
|
||||
hba->u.mvfrey.inlist_phy = phy;
|
||||
|
||||
p += list_count * sizeof(struct mvfrey_inlist_entry);
|
||||
phy += list_count * sizeof(struct mvfrey_inlist_entry);
|
||||
|
||||
hba->u.mvfrey.outlist = (struct mvfrey_outlist_entry *)p;
|
||||
hba->u.mvfrey.outlist_phy = phy;
|
||||
|
||||
p += list_count * sizeof(struct mvfrey_outlist_entry);
|
||||
phy += list_count * sizeof(struct mvfrey_outlist_entry);
|
||||
|
||||
hba->u.mvfrey.outlist_cptr = (__le32 *)p;
|
||||
hba->u.mvfrey.outlist_cptr_phy = phy;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int hptiop_internal_memfree_itl(struct hptiop_hba *hba)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int hptiop_internal_memfree_mv(struct hptiop_hba *hba)
|
||||
{
|
||||
if (hba->u.mv.internal_req) {
|
||||
|
|
@ -953,6 +1269,19 @@ static int hptiop_internal_memfree_mv(struct hptiop_hba *hba)
|
|||
return -1;
|
||||
}
|
||||
|
||||
static int hptiop_internal_memfree_mvfrey(struct hptiop_hba *hba)
|
||||
{
|
||||
if (hba->u.mvfrey.internal_req.req_virt) {
|
||||
dma_free_coherent(&hba->pcidev->dev,
|
||||
hba->u.mvfrey.internal_mem_size,
|
||||
hba->u.mvfrey.internal_req.req_virt,
|
||||
(dma_addr_t)
|
||||
hba->u.mvfrey.internal_req.req_shifted_phy << 5);
|
||||
return 0;
|
||||
} else
|
||||
return -1;
|
||||
}
|
||||
|
||||
static int __devinit hptiop_probe(struct pci_dev *pcidev,
|
||||
const struct pci_device_id *id)
|
||||
{
|
||||
|
|
@ -1027,7 +1356,7 @@ static int __devinit hptiop_probe(struct pci_dev *pcidev,
|
|||
goto unmap_pci_bar;
|
||||
}
|
||||
|
||||
if (hba->ops->internal_memalloc) {
|
||||
if (hba->ops->family == MV_BASED_IOP) {
|
||||
if (hba->ops->internal_memalloc(hba)) {
|
||||
printk(KERN_ERR "scsi%d: internal_memalloc failed\n",
|
||||
hba->host->host_no);
|
||||
|
|
@ -1050,6 +1379,19 @@ static int __devinit hptiop_probe(struct pci_dev *pcidev,
|
|||
hba->interface_version = le32_to_cpu(iop_config.interface_version);
|
||||
hba->sdram_size = le32_to_cpu(iop_config.sdram_size);
|
||||
|
||||
if (hba->ops->family == MVFREY_BASED_IOP) {
|
||||
if (hba->ops->internal_memalloc(hba)) {
|
||||
printk(KERN_ERR "scsi%d: internal_memalloc failed\n",
|
||||
hba->host->host_no);
|
||||
goto unmap_pci_bar;
|
||||
}
|
||||
if (hba->ops->reset_comm(hba)) {
|
||||
printk(KERN_ERR "scsi%d: reset comm failed\n",
|
||||
hba->host->host_no);
|
||||
goto unmap_pci_bar;
|
||||
}
|
||||
}
|
||||
|
||||
if (hba->firmware_version > 0x01020000 ||
|
||||
hba->interface_version > 0x01020000)
|
||||
hba->iopintf_v2 = 1;
|
||||
|
|
@ -1104,14 +1446,13 @@ static int __devinit hptiop_probe(struct pci_dev *pcidev,
|
|||
hba->dma_coherent = start_virt;
|
||||
hba->dma_coherent_handle = start_phy;
|
||||
|
||||
if ((start_phy & 0x1f) != 0)
|
||||
{
|
||||
if ((start_phy & 0x1f) != 0) {
|
||||
offset = ((start_phy + 0x1f) & ~0x1f) - start_phy;
|
||||
start_phy += offset;
|
||||
start_virt += offset;
|
||||
}
|
||||
|
||||
hba->req_list = start_virt;
|
||||
hba->req_list = NULL;
|
||||
for (i = 0; i < hba->max_requests; i++) {
|
||||
hba->reqs[i].next = NULL;
|
||||
hba->reqs[i].req_virt = start_virt;
|
||||
|
|
@ -1132,7 +1473,6 @@ static int __devinit hptiop_probe(struct pci_dev *pcidev,
|
|||
goto free_request_mem;
|
||||
}
|
||||
|
||||
|
||||
scsi_scan_host(host);
|
||||
|
||||
dprintk("scsi%d: hptiop_probe successfully\n", hba->host->host_no);
|
||||
|
|
@ -1147,8 +1487,7 @@ static int __devinit hptiop_probe(struct pci_dev *pcidev,
|
|||
free_irq(hba->pcidev->irq, hba);
|
||||
|
||||
unmap_pci_bar:
|
||||
if (hba->ops->internal_memfree)
|
||||
hba->ops->internal_memfree(hba);
|
||||
hba->ops->internal_memfree(hba);
|
||||
|
||||
hba->ops->unmap_pci_bar(hba);
|
||||
|
||||
|
|
@ -1198,6 +1537,16 @@ static void hptiop_disable_intr_mv(struct hptiop_hba *hba)
|
|||
readl(&hba->u.mv.regs->outbound_intmask);
|
||||
}
|
||||
|
||||
static void hptiop_disable_intr_mvfrey(struct hptiop_hba *hba)
|
||||
{
|
||||
writel(0, &(hba->u.mvfrey.mu->f0_doorbell_enable));
|
||||
readl(&(hba->u.mvfrey.mu->f0_doorbell_enable));
|
||||
writel(0, &(hba->u.mvfrey.mu->isr_enable));
|
||||
readl(&(hba->u.mvfrey.mu->isr_enable));
|
||||
writel(0, &(hba->u.mvfrey.mu->pcie_f0_int_enable));
|
||||
readl(&(hba->u.mvfrey.mu->pcie_f0_int_enable));
|
||||
}
|
||||
|
||||
static void hptiop_remove(struct pci_dev *pcidev)
|
||||
{
|
||||
struct Scsi_Host *host = pci_get_drvdata(pcidev);
|
||||
|
|
@ -1216,8 +1565,7 @@ static void hptiop_remove(struct pci_dev *pcidev)
|
|||
hba->dma_coherent,
|
||||
hba->dma_coherent_handle);
|
||||
|
||||
if (hba->ops->internal_memfree)
|
||||
hba->ops->internal_memfree(hba);
|
||||
hba->ops->internal_memfree(hba);
|
||||
|
||||
hba->ops->unmap_pci_bar(hba);
|
||||
|
||||
|
|
@ -1229,9 +1577,10 @@ static void hptiop_remove(struct pci_dev *pcidev)
|
|||
}
|
||||
|
||||
static struct hptiop_adapter_ops hptiop_itl_ops = {
|
||||
.family = INTEL_BASED_IOP,
|
||||
.iop_wait_ready = iop_wait_ready_itl,
|
||||
.internal_memalloc = NULL,
|
||||
.internal_memfree = NULL,
|
||||
.internal_memalloc = hptiop_internal_memalloc_itl,
|
||||
.internal_memfree = hptiop_internal_memfree_itl,
|
||||
.map_pci_bar = hptiop_map_pci_bar_itl,
|
||||
.unmap_pci_bar = hptiop_unmap_pci_bar_itl,
|
||||
.enable_intr = hptiop_enable_intr_itl,
|
||||
|
|
@ -1242,9 +1591,12 @@ static struct hptiop_adapter_ops hptiop_itl_ops = {
|
|||
.post_msg = hptiop_post_msg_itl,
|
||||
.post_req = hptiop_post_req_itl,
|
||||
.hw_dma_bit_mask = 64,
|
||||
.reset_comm = hptiop_reset_comm_itl,
|
||||
.host_phy_flag = cpu_to_le64(0),
|
||||
};
|
||||
|
||||
static struct hptiop_adapter_ops hptiop_mv_ops = {
|
||||
.family = MV_BASED_IOP,
|
||||
.iop_wait_ready = iop_wait_ready_mv,
|
||||
.internal_memalloc = hptiop_internal_memalloc_mv,
|
||||
.internal_memfree = hptiop_internal_memfree_mv,
|
||||
|
|
@ -1258,6 +1610,27 @@ static struct hptiop_adapter_ops hptiop_mv_ops = {
|
|||
.post_msg = hptiop_post_msg_mv,
|
||||
.post_req = hptiop_post_req_mv,
|
||||
.hw_dma_bit_mask = 33,
|
||||
.reset_comm = hptiop_reset_comm_mv,
|
||||
.host_phy_flag = cpu_to_le64(0),
|
||||
};
|
||||
|
||||
static struct hptiop_adapter_ops hptiop_mvfrey_ops = {
|
||||
.family = MVFREY_BASED_IOP,
|
||||
.iop_wait_ready = iop_wait_ready_mvfrey,
|
||||
.internal_memalloc = hptiop_internal_memalloc_mvfrey,
|
||||
.internal_memfree = hptiop_internal_memfree_mvfrey,
|
||||
.map_pci_bar = hptiop_map_pci_bar_mvfrey,
|
||||
.unmap_pci_bar = hptiop_unmap_pci_bar_mvfrey,
|
||||
.enable_intr = hptiop_enable_intr_mvfrey,
|
||||
.disable_intr = hptiop_disable_intr_mvfrey,
|
||||
.get_config = iop_get_config_mvfrey,
|
||||
.set_config = iop_set_config_mvfrey,
|
||||
.iop_intr = iop_intr_mvfrey,
|
||||
.post_msg = hptiop_post_msg_mvfrey,
|
||||
.post_req = hptiop_post_req_mvfrey,
|
||||
.hw_dma_bit_mask = 64,
|
||||
.reset_comm = hptiop_reset_comm_mvfrey,
|
||||
.host_phy_flag = cpu_to_le64(1),
|
||||
};
|
||||
|
||||
static struct pci_device_id hptiop_id_table[] = {
|
||||
|
|
@ -1283,6 +1656,8 @@ static struct pci_device_id hptiop_id_table[] = {
|
|||
{ PCI_VDEVICE(TTI, 0x3120), (kernel_ulong_t)&hptiop_mv_ops },
|
||||
{ PCI_VDEVICE(TTI, 0x3122), (kernel_ulong_t)&hptiop_mv_ops },
|
||||
{ PCI_VDEVICE(TTI, 0x3020), (kernel_ulong_t)&hptiop_mv_ops },
|
||||
{ PCI_VDEVICE(TTI, 0x4520), (kernel_ulong_t)&hptiop_mvfrey_ops },
|
||||
{ PCI_VDEVICE(TTI, 0x4522), (kernel_ulong_t)&hptiop_mvfrey_ops },
|
||||
{},
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/*
|
||||
* HighPoint RR3xxx/4xxx controller driver for Linux
|
||||
* Copyright (C) 2006-2009 HighPoint Technologies, Inc. All Rights Reserved.
|
||||
* Copyright (C) 2006-2012 HighPoint Technologies, Inc. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
@ -75,6 +75,45 @@ struct hpt_iopmv_regs {
|
|||
__le32 outbound_intmask;
|
||||
};
|
||||
|
||||
#pragma pack(1)
|
||||
struct hpt_iopmu_mvfrey {
|
||||
__le32 reserved0[(0x4000 - 0) / 4];
|
||||
__le32 inbound_base;
|
||||
__le32 inbound_base_high;
|
||||
__le32 reserved1[(0x4018 - 0x4008) / 4];
|
||||
__le32 inbound_write_ptr;
|
||||
__le32 reserved2[(0x402c - 0x401c) / 4];
|
||||
__le32 inbound_conf_ctl;
|
||||
__le32 reserved3[(0x4050 - 0x4030) / 4];
|
||||
__le32 outbound_base;
|
||||
__le32 outbound_base_high;
|
||||
__le32 outbound_shadow_base;
|
||||
__le32 outbound_shadow_base_high;
|
||||
__le32 reserved4[(0x4088 - 0x4060) / 4];
|
||||
__le32 isr_cause;
|
||||
__le32 isr_enable;
|
||||
__le32 reserved5[(0x1020c - 0x4090) / 4];
|
||||
__le32 pcie_f0_int_enable;
|
||||
__le32 reserved6[(0x10400 - 0x10210) / 4];
|
||||
__le32 f0_to_cpu_msg_a;
|
||||
__le32 reserved7[(0x10420 - 0x10404) / 4];
|
||||
__le32 cpu_to_f0_msg_a;
|
||||
__le32 reserved8[(0x10480 - 0x10424) / 4];
|
||||
__le32 f0_doorbell;
|
||||
__le32 f0_doorbell_enable;
|
||||
};
|
||||
|
||||
struct mvfrey_inlist_entry {
|
||||
dma_addr_t addr;
|
||||
__le32 intrfc_len;
|
||||
__le32 reserved;
|
||||
};
|
||||
|
||||
struct mvfrey_outlist_entry {
|
||||
__le32 val;
|
||||
};
|
||||
#pragma pack()
|
||||
|
||||
#define MVIOP_MU_QUEUE_ADDR_HOST_MASK (~(0x1full))
|
||||
#define MVIOP_MU_QUEUE_ADDR_HOST_BIT 4
|
||||
|
||||
|
|
@ -87,6 +126,9 @@ struct hpt_iopmv_regs {
|
|||
#define MVIOP_MU_OUTBOUND_INT_MSG 1
|
||||
#define MVIOP_MU_OUTBOUND_INT_POSTQUEUE 2
|
||||
|
||||
#define CL_POINTER_TOGGLE 0x00004000
|
||||
#define CPU_TO_F0_DRBL_MSG_BIT 0x02000000
|
||||
|
||||
enum hpt_iopmu_message {
|
||||
/* host-to-iop messages */
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||||
IOPMU_INBOUND_MSG0_NOP = 0,
|
||||
|
|
@ -95,6 +137,7 @@ enum hpt_iopmu_message {
|
|||
IOPMU_INBOUND_MSG0_SHUTDOWN,
|
||||
IOPMU_INBOUND_MSG0_STOP_BACKGROUND_TASK,
|
||||
IOPMU_INBOUND_MSG0_START_BACKGROUND_TASK,
|
||||
IOPMU_INBOUND_MSG0_RESET_COMM,
|
||||
IOPMU_INBOUND_MSG0_MAX = 0xff,
|
||||
/* iop-to-host messages */
|
||||
IOPMU_OUTBOUND_MSG0_REGISTER_DEVICE_0 = 0x100,
|
||||
|
|
@ -118,6 +161,7 @@ struct hpt_iop_request_header {
|
|||
#define IOP_REQUEST_FLAG_BIST_REQUEST 2
|
||||
#define IOP_REQUEST_FLAG_REMAPPED 4
|
||||
#define IOP_REQUEST_FLAG_OUTPUT_CONTEXT 8
|
||||
#define IOP_REQUEST_FLAG_ADDR_BITS 0x40 /* flags[31:16] is phy_addr[47:32] */
|
||||
|
||||
enum hpt_iop_request_type {
|
||||
IOP_REQUEST_TYPE_GET_CONFIG = 0,
|
||||
|
|
@ -223,6 +267,13 @@ struct hpt_scsi_pointer {
|
|||
|
||||
#define HPT_SCP(scp) ((struct hpt_scsi_pointer *)&(scp)->SCp)
|
||||
|
||||
enum hptiop_family {
|
||||
UNKNOWN_BASED_IOP,
|
||||
INTEL_BASED_IOP,
|
||||
MV_BASED_IOP,
|
||||
MVFREY_BASED_IOP
|
||||
} ;
|
||||
|
||||
struct hptiop_hba {
|
||||
struct hptiop_adapter_ops *ops;
|
||||
union {
|
||||
|
|
@ -236,6 +287,22 @@ struct hptiop_hba {
|
|||
void *internal_req;
|
||||
dma_addr_t internal_req_phy;
|
||||
} mv;
|
||||
struct {
|
||||
struct hpt_iop_request_get_config __iomem *config;
|
||||
struct hpt_iopmu_mvfrey __iomem *mu;
|
||||
|
||||
int internal_mem_size;
|
||||
struct hptiop_request internal_req;
|
||||
int list_count;
|
||||
struct mvfrey_inlist_entry *inlist;
|
||||
dma_addr_t inlist_phy;
|
||||
__le32 inlist_wptr;
|
||||
struct mvfrey_outlist_entry *outlist;
|
||||
dma_addr_t outlist_phy;
|
||||
__le32 *outlist_cptr; /* copy pointer shadow */
|
||||
dma_addr_t outlist_cptr_phy;
|
||||
__le32 outlist_rptr;
|
||||
} mvfrey;
|
||||
} u;
|
||||
|
||||
struct Scsi_Host *host;
|
||||
|
|
@ -283,6 +350,7 @@ struct hpt_ioctl_k {
|
|||
};
|
||||
|
||||
struct hptiop_adapter_ops {
|
||||
enum hptiop_family family;
|
||||
int (*iop_wait_ready)(struct hptiop_hba *hba, u32 millisec);
|
||||
int (*internal_memalloc)(struct hptiop_hba *hba);
|
||||
int (*internal_memfree)(struct hptiop_hba *hba);
|
||||
|
|
@ -298,6 +366,8 @@ struct hptiop_adapter_ops {
|
|||
void (*post_msg)(struct hptiop_hba *hba, u32 msg);
|
||||
void (*post_req)(struct hptiop_hba *hba, struct hptiop_request *_req);
|
||||
int hw_dma_bit_mask;
|
||||
int (*reset_comm)(struct hptiop_hba *hba);
|
||||
__le64 host_phy_flag;
|
||||
};
|
||||
|
||||
#define HPT_IOCTL_RESULT_OK 0
|
||||
|
|
|
|||
Loading…
Reference in New Issue