mirror of https://gitee.com/openkylin/linux.git
dmaengine: dw: fix cyclic transfer callbacks
Cyclic transfer callbacks rely on block completion interrupts which were disabled in commitff7b05f29f
("dmaengine/dw_dmac: Don't handle block interrupts"). This re-enables block interrupts so the cyclic callbacks can work. Other transfer types are not affected as they set the INT_EN bit only on the last block. Fixes:ff7b05f29f
("dmaengine/dw_dmac: Don't handle block interrupts") Signed-off-by: Mans Rullgard <mans@mansr.com> Reviewed-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com> Cc: <stable@vger.kernel.org>
This commit is contained in:
parent
df3bb8a0e6
commit
2895b2cad6
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@ -156,6 +156,7 @@ static void dwc_initialize(struct dw_dma_chan *dwc)
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/* Enable interrupts */
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/* Enable interrupts */
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channel_set_bit(dw, MASK.XFER, dwc->mask);
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channel_set_bit(dw, MASK.XFER, dwc->mask);
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channel_set_bit(dw, MASK.BLOCK, dwc->mask);
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channel_set_bit(dw, MASK.ERROR, dwc->mask);
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channel_set_bit(dw, MASK.ERROR, dwc->mask);
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dwc->initialized = true;
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dwc->initialized = true;
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@ -536,16 +537,17 @@ EXPORT_SYMBOL(dw_dma_get_dst_addr);
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/* Called with dwc->lock held and all DMAC interrupts disabled */
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/* Called with dwc->lock held and all DMAC interrupts disabled */
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static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
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static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
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u32 status_err, u32 status_xfer)
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u32 status_block, u32 status_err, u32 status_xfer)
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{
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{
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unsigned long flags;
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unsigned long flags;
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if (dwc->mask) {
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if (status_block & dwc->mask) {
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void (*callback)(void *param);
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void (*callback)(void *param);
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void *callback_param;
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void *callback_param;
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dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
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dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
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channel_readl(dwc, LLP));
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channel_readl(dwc, LLP));
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dma_writel(dw, CLEAR.BLOCK, dwc->mask);
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callback = dwc->cdesc->period_callback;
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callback = dwc->cdesc->period_callback;
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callback_param = dwc->cdesc->period_callback_param;
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callback_param = dwc->cdesc->period_callback_param;
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@ -577,6 +579,7 @@ static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
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channel_writel(dwc, CTL_LO, 0);
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channel_writel(dwc, CTL_LO, 0);
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channel_writel(dwc, CTL_HI, 0);
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channel_writel(dwc, CTL_HI, 0);
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dma_writel(dw, CLEAR.BLOCK, dwc->mask);
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dma_writel(dw, CLEAR.ERROR, dwc->mask);
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dma_writel(dw, CLEAR.ERROR, dwc->mask);
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dma_writel(dw, CLEAR.XFER, dwc->mask);
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dma_writel(dw, CLEAR.XFER, dwc->mask);
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@ -593,10 +596,12 @@ static void dw_dma_tasklet(unsigned long data)
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{
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{
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struct dw_dma *dw = (struct dw_dma *)data;
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struct dw_dma *dw = (struct dw_dma *)data;
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struct dw_dma_chan *dwc;
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struct dw_dma_chan *dwc;
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u32 status_block;
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u32 status_xfer;
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u32 status_xfer;
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u32 status_err;
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u32 status_err;
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int i;
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int i;
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status_block = dma_readl(dw, RAW.BLOCK);
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status_xfer = dma_readl(dw, RAW.XFER);
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status_xfer = dma_readl(dw, RAW.XFER);
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status_err = dma_readl(dw, RAW.ERROR);
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status_err = dma_readl(dw, RAW.ERROR);
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@ -605,7 +610,8 @@ static void dw_dma_tasklet(unsigned long data)
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for (i = 0; i < dw->dma.chancnt; i++) {
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for (i = 0; i < dw->dma.chancnt; i++) {
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dwc = &dw->chan[i];
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dwc = &dw->chan[i];
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if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
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if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
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dwc_handle_cyclic(dw, dwc, status_err, status_xfer);
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dwc_handle_cyclic(dw, dwc, status_block, status_err,
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status_xfer);
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else if (status_err & (1 << i))
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else if (status_err & (1 << i))
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dwc_handle_error(dw, dwc);
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dwc_handle_error(dw, dwc);
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else if (status_xfer & (1 << i))
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else if (status_xfer & (1 << i))
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@ -616,6 +622,7 @@ static void dw_dma_tasklet(unsigned long data)
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* Re-enable interrupts.
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* Re-enable interrupts.
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*/
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*/
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channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
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channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
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channel_set_bit(dw, MASK.BLOCK, dw->all_chan_mask);
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channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
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channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
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}
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}
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@ -635,6 +642,7 @@ static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
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* softirq handler.
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* softirq handler.
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*/
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*/
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channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
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channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
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channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
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channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
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channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
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status = dma_readl(dw, STATUS_INT);
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status = dma_readl(dw, STATUS_INT);
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@ -645,6 +653,7 @@ static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
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/* Try to recover */
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/* Try to recover */
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channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
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channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
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channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1);
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channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
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channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
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channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
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channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
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channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
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channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
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@ -1111,6 +1120,7 @@ static void dw_dma_off(struct dw_dma *dw)
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dma_writel(dw, CFG, 0);
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dma_writel(dw, CFG, 0);
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channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
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channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
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channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
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channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
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channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
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channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
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channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
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channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
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channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
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@ -1216,6 +1226,7 @@ static void dwc_free_chan_resources(struct dma_chan *chan)
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/* Disable interrupts */
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/* Disable interrupts */
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channel_clear_bit(dw, MASK.XFER, dwc->mask);
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channel_clear_bit(dw, MASK.XFER, dwc->mask);
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channel_clear_bit(dw, MASK.BLOCK, dwc->mask);
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channel_clear_bit(dw, MASK.ERROR, dwc->mask);
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channel_clear_bit(dw, MASK.ERROR, dwc->mask);
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spin_unlock_irqrestore(&dwc->lock, flags);
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spin_unlock_irqrestore(&dwc->lock, flags);
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@ -1458,6 +1469,7 @@ void dw_dma_cyclic_free(struct dma_chan *chan)
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dwc_chan_disable(dw, dwc);
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dwc_chan_disable(dw, dwc);
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dma_writel(dw, CLEAR.BLOCK, dwc->mask);
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dma_writel(dw, CLEAR.ERROR, dwc->mask);
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dma_writel(dw, CLEAR.ERROR, dwc->mask);
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dma_writel(dw, CLEAR.XFER, dwc->mask);
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dma_writel(dw, CLEAR.XFER, dwc->mask);
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@ -1546,9 +1558,6 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
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/* Force dma off, just in case */
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/* Force dma off, just in case */
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dw_dma_off(dw);
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dw_dma_off(dw);
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/* Disable BLOCK interrupts as well */
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channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
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/* Create a pool of consistent memory blocks for hardware descriptors */
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/* Create a pool of consistent memory blocks for hardware descriptors */
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dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", chip->dev,
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dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", chip->dev,
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sizeof(struct dw_desc), 4, 0);
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sizeof(struct dw_desc), 4, 0);
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