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drm/amd/display: fix dcn1 dppclk when min dispclk patch applies 

Applying min dispclk patch would result in incorrect dppclk divider
without this change

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dmytro Laktyushkin 2018-02-21 15:10:02 -05:00 committed by Alex Deucher
parent 1296423bf2
commit 28d4175413
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
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@ -998,7 +998,7 @@ bool dcn_validate_bandwidth(
dc->debug.min_disp_clk_khz;
}
context->bw.dcn.calc_clk.max_dppclk_khz = (int)(v->dppclk * 1000);
context->bw.dcn.calc_clk.max_dppclk_khz = context->bw.dcn.calc_clk.dispclk_khz / v->dispclk_dppclk_ratio;
for (i = 0, input_idx = 0; i < pool->pipe_count; i++) {
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];