mirror of https://gitee.com/openkylin/linux.git
iio: mma8452: Basic support for transient events.
The event is triggered when the highpass filtered absolute acceleration exceeds the threshold. Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
This commit is contained in:
parent
4892688d70
commit
28e3427824
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@ -9,7 +9,7 @@
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*
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*
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* 7-bit I2C slave address 0x1c/0x1d (pin selectable)
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* 7-bit I2C slave address 0x1c/0x1d (pin selectable)
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*
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*
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* TODO: interrupt, thresholding, orientation / freefall events, autosleep
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* TODO: orientation / freefall events, autosleep
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*/
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*/
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#include <linux/module.h>
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#include <linux/module.h>
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@ -19,20 +19,33 @@
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#include <linux/iio/trigger_consumer.h>
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#include <linux/iio/trigger_consumer.h>
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#include <linux/iio/buffer.h>
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#include <linux/iio/buffer.h>
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#include <linux/iio/triggered_buffer.h>
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#include <linux/iio/triggered_buffer.h>
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#include <linux/iio/events.h>
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#include <linux/delay.h>
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#include <linux/delay.h>
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#define MMA8452_STATUS 0x00
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#define MMA8452_STATUS 0x00
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#define MMA8452_OUT_X 0x01 /* MSB first, 12-bit */
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#define MMA8452_OUT_X 0x01 /* MSB first, 12-bit */
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#define MMA8452_OUT_Y 0x03
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#define MMA8452_OUT_Y 0x03
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#define MMA8452_OUT_Z 0x05
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#define MMA8452_OUT_Z 0x05
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#define MMA8452_INT_SRC 0x0c
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#define MMA8452_WHO_AM_I 0x0d
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#define MMA8452_WHO_AM_I 0x0d
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#define MMA8452_DATA_CFG 0x0e
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#define MMA8452_DATA_CFG 0x0e
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#define MMA8452_TRANSIENT_CFG 0x1d
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#define MMA8452_TRANSIENT_CFG_ELE BIT(4)
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#define MMA8452_TRANSIENT_CFG_CHAN(chan) BIT(chan + 1)
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#define MMA8452_TRANSIENT_SRC 0x1e
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#define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1)
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#define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3)
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#define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5)
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#define MMA8452_TRANSIENT_THS 0x1f
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#define MMA8452_TRANSIENT_THS_MASK 0x7f
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#define MMA8452_OFF_X 0x2f
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#define MMA8452_OFF_X 0x2f
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#define MMA8452_OFF_Y 0x30
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#define MMA8452_OFF_Y 0x30
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#define MMA8452_OFF_Z 0x31
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#define MMA8452_OFF_Z 0x31
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#define MMA8452_CTRL_REG1 0x2a
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#define MMA8452_CTRL_REG1 0x2a
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#define MMA8452_CTRL_REG2 0x2b
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#define MMA8452_CTRL_REG2 0x2b
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#define MMA8452_CTRL_REG2_RST BIT(6)
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#define MMA8452_CTRL_REG2_RST BIT(6)
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#define MMA8452_CTRL_REG4 0x2d
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#define MMA8452_CTRL_REG5 0x2e
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#define MMA8452_MAX_REG 0x31
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#define MMA8452_MAX_REG 0x31
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@ -48,6 +61,8 @@
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#define MMA8452_DATA_CFG_FS_4G 1
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#define MMA8452_DATA_CFG_FS_4G 1
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#define MMA8452_DATA_CFG_FS_8G 2
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#define MMA8452_DATA_CFG_FS_8G 2
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#define MMA8452_INT_TRANS BIT(5)
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#define MMA8452_DEVICE_ID 0x2a
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#define MMA8452_DEVICE_ID 0x2a
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struct mma8452_data {
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struct mma8452_data {
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@ -274,6 +289,126 @@ static int mma8452_write_raw(struct iio_dev *indio_dev,
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}
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}
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}
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}
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static int mma8452_read_thresh(struct iio_dev *indio_dev,
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const struct iio_chan_spec *chan,
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enum iio_event_type type,
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enum iio_event_direction dir,
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enum iio_event_info info,
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int *val, int *val2)
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{
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struct mma8452_data *data = iio_priv(indio_dev);
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int ret;
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ret = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_THS);
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if (ret < 0)
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return ret;
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*val = ret & MMA8452_TRANSIENT_THS_MASK;
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return IIO_VAL_INT;
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}
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static int mma8452_write_thresh(struct iio_dev *indio_dev,
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const struct iio_chan_spec *chan,
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enum iio_event_type type,
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enum iio_event_direction dir,
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enum iio_event_info info,
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int val, int val2)
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{
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struct mma8452_data *data = iio_priv(indio_dev);
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return mma8452_change_config(data, MMA8452_TRANSIENT_THS,
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val & MMA8452_TRANSIENT_THS_MASK);
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}
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static int mma8452_read_event_config(struct iio_dev *indio_dev,
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const struct iio_chan_spec *chan,
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enum iio_event_type type,
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enum iio_event_direction dir)
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{
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struct mma8452_data *data = iio_priv(indio_dev);
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int ret;
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ret = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_CFG);
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if (ret < 0)
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return ret;
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return ret & MMA8452_TRANSIENT_CFG_CHAN(chan->scan_index) ? 1 : 0;
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}
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static int mma8452_write_event_config(struct iio_dev *indio_dev,
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const struct iio_chan_spec *chan,
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enum iio_event_type type,
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enum iio_event_direction dir,
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int state)
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{
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struct mma8452_data *data = iio_priv(indio_dev);
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int val;
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val = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_CFG);
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if (val < 0)
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return val;
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if (state)
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val |= MMA8452_TRANSIENT_CFG_CHAN(chan->scan_index);
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else
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val &= ~MMA8452_TRANSIENT_CFG_CHAN(chan->scan_index);
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val |= MMA8452_TRANSIENT_CFG_ELE;
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return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, val);
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}
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static void mma8452_transient_interrupt(struct iio_dev *indio_dev)
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{
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struct mma8452_data *data = iio_priv(indio_dev);
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s64 ts = iio_get_time_ns();
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int src;
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src = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_SRC);
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if (src < 0)
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return;
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if (src & MMA8452_TRANSIENT_SRC_XTRANSE)
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iio_push_event(indio_dev,
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IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,
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IIO_EV_TYPE_THRESH,
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IIO_EV_DIR_RISING),
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ts);
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if (src & MMA8452_TRANSIENT_SRC_YTRANSE)
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iio_push_event(indio_dev,
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IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y,
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IIO_EV_TYPE_THRESH,
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IIO_EV_DIR_RISING),
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ts);
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if (src & MMA8452_TRANSIENT_SRC_ZTRANSE)
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iio_push_event(indio_dev,
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IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z,
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IIO_EV_TYPE_THRESH,
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IIO_EV_DIR_RISING),
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ts);
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}
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static irqreturn_t mma8452_interrupt(int irq, void *p)
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{
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struct iio_dev *indio_dev = p;
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struct mma8452_data *data = iio_priv(indio_dev);
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int src;
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src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC);
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if (src < 0)
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return IRQ_NONE;
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if (src & MMA8452_INT_TRANS) {
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mma8452_transient_interrupt(indio_dev);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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static irqreturn_t mma8452_trigger_handler(int irq, void *p)
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static irqreturn_t mma8452_trigger_handler(int irq, void *p)
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{
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{
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struct iio_poll_func *pf = p;
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struct iio_poll_func *pf = p;
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return 0;
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return 0;
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}
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}
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static const struct iio_event_spec mma8452_transient_event[] = {
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{
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.type = IIO_EV_TYPE_THRESH,
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.dir = IIO_EV_DIR_RISING,
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.mask_separate = BIT(IIO_EV_INFO_ENABLE),
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.mask_shared_by_type = BIT(IIO_EV_INFO_VALUE)
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},
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};
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/*
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* Threshold is configured in fixed 8G/127 steps regardless of
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* currently selected scale for measurement.
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*/
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static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742");
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static struct attribute *mma8452_event_attributes[] = {
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&iio_const_attr_accel_transient_scale.dev_attr.attr,
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NULL,
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};
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static struct attribute_group mma8452_event_attribute_group = {
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.attrs = mma8452_event_attributes,
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.name = "events",
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};
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#define MMA8452_CHANNEL(axis, idx) { \
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#define MMA8452_CHANNEL(axis, idx) { \
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.type = IIO_ACCEL, \
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.type = IIO_ACCEL, \
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.modified = 1, \
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.modified = 1, \
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.shift = 4, \
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.shift = 4, \
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.endianness = IIO_BE, \
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.endianness = IIO_BE, \
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}, \
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}, \
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.event_spec = mma8452_transient_event, \
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.num_event_specs = ARRAY_SIZE(mma8452_transient_event), \
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}
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}
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static const struct iio_chan_spec mma8452_channels[] = {
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static const struct iio_chan_spec mma8452_channels[] = {
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@ -355,6 +517,11 @@ static const struct iio_info mma8452_info = {
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.attrs = &mma8452_group,
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.attrs = &mma8452_group,
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.read_raw = &mma8452_read_raw,
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.read_raw = &mma8452_read_raw,
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.write_raw = &mma8452_write_raw,
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.write_raw = &mma8452_write_raw,
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.event_attrs = &mma8452_event_attribute_group,
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.read_event_value = &mma8452_read_thresh,
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.write_event_value = &mma8452_write_thresh,
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.read_event_config = &mma8452_read_event_config,
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.write_event_config = &mma8452_write_event_config,
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.debugfs_reg_access = &mma8452_reg_access_dbg,
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.debugfs_reg_access = &mma8452_reg_access_dbg,
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.driver_module = THIS_MODULE,
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.driver_module = THIS_MODULE,
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};
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};
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if (ret < 0)
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if (ret < 0)
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return ret;
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return ret;
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/*
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* By default set transient threshold to max to avoid events if
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* enabling without configuring threshold.
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*/
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ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS,
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MMA8452_TRANSIENT_THS_MASK);
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if (ret < 0)
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return ret;
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if (client->irq) {
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/*
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* Although we enable the transient interrupt source once and
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* for all here the transient event detection itself is not
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* enabled until userspace asks for it by
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* mma8452_write_event_config()
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*/
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int supported_interrupts = MMA8452_INT_TRANS;
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/* Assume wired to INT1 pin */
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ret = i2c_smbus_write_byte_data(client,
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MMA8452_CTRL_REG5,
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supported_interrupts);
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if (ret < 0)
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return ret;
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ret = i2c_smbus_write_byte_data(client,
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MMA8452_CTRL_REG4,
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supported_interrupts);
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if (ret < 0)
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return ret;
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}
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data->ctrl_reg1 = MMA8452_CTRL_ACTIVE |
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data->ctrl_reg1 = MMA8452_CTRL_ACTIVE |
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(MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT);
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(MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT);
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ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1,
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ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1,
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if (ret < 0)
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if (ret < 0)
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return ret;
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return ret;
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if (client->irq) {
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ret = devm_request_threaded_irq(&client->dev,
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client->irq,
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NULL, mma8452_interrupt,
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IRQF_TRIGGER_LOW | IRQF_ONESHOT,
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client->name, indio_dev);
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if (ret)
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goto buffer_cleanup;
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}
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ret = iio_device_register(indio_dev);
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ret = iio_device_register(indio_dev);
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if (ret < 0)
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if (ret < 0)
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goto buffer_cleanup;
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goto buffer_cleanup;
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return 0;
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return 0;
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buffer_cleanup:
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buffer_cleanup:
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