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regmap-mmio: Use native endianness for read/write 

The regmap API has an endianness setting for formatting reads and writes.
This can be set by the usual DT "little-endian" and "big-endian" properties.
To work properly the associated regmap_bus needs to read/write in native
endian.

The "syscon" DT device binding creates an mmio-based regmap_bus which
performs all reads/writes as little-endian. These values are then converted
again by regmap, which means that all of the MIPS BCM boards (which are
big-endian) have been declared as "little-endian" to get regmap to convert
them back to big-endian.

Modify regmap-mmio to use the native-endian functions __raw_read*() and
__raw_write*() instead of the little-endian functions read*() and
write*().

Modify the big-endian MIPS BCM boards to use what will now be the correct
endianness instead of pretending that the devices are little-endian.

Signed-off-by: Simon Arlott <simon@fire.lp0.eu>
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Simon Arlott 2015-10-29 19:58:47 +00:00 committed by Mark Brown
parent 8005c49d9a
commit 29bb45f25f
10 changed files with 8 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/mips/boot/dts/brcm/bcm6328.dtsi
View File

@ -73,7 +73,6 @@ uart0: serial@10000100 {
timer: timer@10000040 {
compatible = "syscon";
reg = <0x10000040 0x2c>;
little-endian;
};
reboot {

1
arch/mips/boot/dts/brcm/bcm7125.dtsi
View File

@ -98,7 +98,6 @@ upg_irq0_intc: upg_irq0_intc@406780 {
sun_top_ctrl: syscon@404000 {
compatible = "brcm,bcm7125-sun-top-ctrl", "syscon";
reg = <0x404000 0x60c>;
little-endian;
};
reboot {

1
arch/mips/boot/dts/brcm/bcm7346.dtsi
View File

@ -118,7 +118,6 @@ upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 {
sun_top_ctrl: syscon@404000 {
compatible = "brcm,bcm7346-sun-top-ctrl", "syscon";
reg = <0x404000 0x51c>;
little-endian;
};
reboot {

1
arch/mips/boot/dts/brcm/bcm7358.dtsi
View File

@ -112,7 +112,6 @@ upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 {
sun_top_ctrl: syscon@404000 {
compatible = "brcm,bcm7358-sun-top-ctrl", "syscon";
reg = <0x404000 0x51c>;
little-endian;
};
reboot {

1
arch/mips/boot/dts/brcm/bcm7360.dtsi
View File

@ -112,7 +112,6 @@ upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 {
sun_top_ctrl: syscon@404000 {
compatible = "brcm,bcm7360-sun-top-ctrl", "syscon";
reg = <0x404000 0x51c>;
little-endian;
};
reboot {

1
arch/mips/boot/dts/brcm/bcm7362.dtsi
View File

@ -118,7 +118,6 @@ upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 {
sun_top_ctrl: syscon@404000 {
compatible = "brcm,bcm7362-sun-top-ctrl", "syscon";
reg = <0x404000 0x51c>;
little-endian;
};
reboot {

1
arch/mips/boot/dts/brcm/bcm7420.dtsi
View File

@ -99,7 +99,6 @@ upg_irq0_intc: upg_irq0_intc@406780 {
sun_top_ctrl: syscon@404000 {
compatible = "brcm,bcm7420-sun-top-ctrl", "syscon";
reg = <0x404000 0x60c>;
little-endian;
};
reboot {

1
arch/mips/boot/dts/brcm/bcm7425.dtsi
View File

@ -100,7 +100,6 @@ upg_irq0_intc: upg_irq0_intc@406780 {
sun_top_ctrl: syscon@404000 {
compatible = "brcm,bcm7425-sun-top-ctrl", "syscon";
reg = <0x404000 0x51c>;
little-endian;
};
reboot {

1
arch/mips/boot/dts/brcm/bcm7435.dtsi
View File

@ -114,7 +114,6 @@ upg_irq0_intc: upg_irq0_intc@406780 {
sun_top_ctrl: syscon@404000 {
compatible = "brcm,bcm7425-sun-top-ctrl", "syscon";
reg = <0x404000 0x51c>;
little-endian;
};
reboot {

16
drivers/base/regmap/regmap-mmio.c
View File

@ -106,17 +106,17 @@ static int regmap_mmio_gather_write(void *context,
while (val_size) {
switch (ctx->val_bytes) {
case 1:
writeb(*(u8 *)val, ctx->regs + offset);
__raw_writeb(*(u8 *)val, ctx->regs + offset);
break;
case 2:
writew(*(u16 *)val, ctx->regs + offset);
__raw_writew(*(u16 *)val, ctx->regs + offset);
break;
case 4:
writel(*(u32 *)val, ctx->regs + offset);
__raw_writel(*(u32 *)val, ctx->regs + offset);
break;
#ifdef CONFIG_64BIT
case 8:
writeq(*(u64 *)val, ctx->regs + offset);
__raw_writeq(*(u64 *)val, ctx->regs + offset);
break;
#endif
default:
@ -166,17 +166,17 @@ static int regmap_mmio_read(void *context,
while (val_size) {
switch (ctx->val_bytes) {
case 1:
*(u8 *)val = readb(ctx->regs + offset);
*(u8 *)val = __raw_readb(ctx->regs + offset);
break;
case 2:
*(u16 *)val = readw(ctx->regs + offset);
*(u16 *)val = __raw_readw(ctx->regs + offset);
break;
case 4:
*(u32 *)val = readl(ctx->regs + offset);
*(u32 *)val = __raw_readl(ctx->regs + offset);
break;
#ifdef CONFIG_64BIT
case 8:
*(u64 *)val = readq(ctx->regs + offset);
*(u64 *)val = __raw_readq(ctx->regs + offset);
break;
#endif
default: