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irqchip: sirf: move from legacy mode to linear irqdomain 

the series of patches for irqdomain core in 3.11 has broken sirf
irq which uses legacy mapping. all users fail in the new kernel
while setupping irq.

this patch moves to linear irqdomain and drop old legacy irqdomain
codes since we don't need it any more, and at the same time, it
also fixes the broken interrupts of sirfsoc in 3.11.

on the other hand, we actually only have 64 interrupt sources for
prima2 and atlas6, but there are 128 interrupt souces for marco
which uses GIC. in the legacy codes, sirf gpio also uses legacy
irqdomain, so to make gpio interrupt mapping not depend on the
prima2/atlas6/marco an use unified marco,we enlarge prima2/atlas6
interrupt number to 128. here we don't need this workaround any
more as sirf gpio also moved to linear mode before. so we move
SIRFSOC_NUM_IRQS back to 64 too.

Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Barry Song 2013-08-06 13:37:13 +08:00 committed by Olof Johansson
parent 30ca2226be
commit 29eb51a728
1 changed files with 10 additions and 8 deletions
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18
drivers/irqchip/irq-sirfsoc.c
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@ -23,7 +23,7 @@
#define SIRFSOC_INT_RISC_LEVEL1 0x0024 #define SIRFSOC_INT_RISC_LEVEL1 0x0024
#define SIRFSOC_INIT_IRQ_ID 0x0038 #define SIRFSOC_INIT_IRQ_ID 0x0038
#define SIRFSOC_NUM_IRQS 128 #define SIRFSOC_NUM_IRQS 64
static struct irq_domain *sirfsoc_irqdomain; static struct irq_domain *sirfsoc_irqdomain;
@ -32,15 +32,18 @@ sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
{ {
struct irq_chip_generic *gc; struct irq_chip_generic *gc;
struct irq_chip_type *ct; struct irq_chip_type *ct;
int ret;
unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
gc = irq_alloc_generic_chip("SIRFINTC", 1, irq_start, base, handle_level_irq); ret = irq_alloc_domain_generic_chips(sirfsoc_irqdomain, num, 1, "irq_sirfsoc",
handle_level_irq, clr, 0, IRQ_GC_INIT_MASK_CACHE);
gc = irq_get_domain_generic_chip(sirfsoc_irqdomain, irq_start);
gc->reg_base = base;
ct = gc->chip_types; ct = gc->chip_types;
ct->chip.irq_mask = irq_gc_mask_clr_bit; ct->chip.irq_mask = irq_gc_mask_clr_bit;
ct->chip.irq_unmask = irq_gc_mask_set_bit; ct->chip.irq_unmask = irq_gc_mask_set_bit;
ct->regs.mask = SIRFSOC_INT_RISC_MASK0; ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, 0);
} }
static asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs) static asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs)
@ -60,9 +63,8 @@ static int __init sirfsoc_irq_init(struct device_node *np, struct device_node *p
if (!base) if (!base)
panic("unable to map intc cpu registers\n"); panic("unable to map intc cpu registers\n");
/* using legacy because irqchip_generic does not work with linear */ sirfsoc_irqdomain = irq_domain_add_linear(np, SIRFSOC_NUM_IRQS,
sirfsoc_irqdomain = irq_domain_add_legacy(np, SIRFSOC_NUM_IRQS, 0, 0, &irq_generic_chip_ops, base);
&irq_domain_simple_ops, base);
sirfsoc_alloc_gc(base, 0, 32); sirfsoc_alloc_gc(base, 0, 32);
sirfsoc_alloc_gc(base + 4, 32, SIRFSOC_NUM_IRQS - 32); sirfsoc_alloc_gc(base + 4, 32, SIRFSOC_NUM_IRQS - 32);