mirror of https://gitee.com/openkylin/linux.git
clk: rockchip: drop CLK_SET_RATE_PARENT from rk3399 fractional dividers
Currently the fractional divider clock time can't handle the CLK_SET_RATE_PARENT flag. This is because, unlike normal dividers, there is no clk_divider_bestdiv() function to try speeding up the parent to see if it helps things. Eventually someone could try to figure out how to make fractional dividers able to use CLK_SET_RATE_PARENT, but until they do let's not confuse the common clock framework (and anyone using it) by setting the flag. Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Chris Zhong <zyw@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Douglas Anderson
Heiko Stuebner
parent
fd75b345bb
commit
29edeccb44
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@ -585,7 +585,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
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COMPOSITE(0, "clk_spdif_div", mux_pll_src_cpll_gpll_p, 0,
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RK3399_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 7, DFLAGS,
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RK3399_CLKGATE_CON(8), 13, GFLAGS),
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COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", CLK_SET_RATE_PARENT,
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COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", 0,
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RK3399_CLKSEL_CON(99), 0,
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RK3399_CLKGATE_CON(8), 14, GFLAGS,
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&rk3399_spdif_fracmux),
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@ -599,7 +599,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
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COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0,
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RK3399_CLKSEL_CON(28), 7, 1, MFLAGS, 0, 7, DFLAGS,
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RK3399_CLKGATE_CON(8), 3, GFLAGS),
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COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", CLK_SET_RATE_PARENT,
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COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", 0,
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RK3399_CLKSEL_CON(96), 0,
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RK3399_CLKGATE_CON(8), 4, GFLAGS,
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&rk3399_i2s0_fracmux),
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@ -609,7 +609,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
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COMPOSITE(0, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, 0,
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RK3399_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 7, DFLAGS,
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RK3399_CLKGATE_CON(8), 6, GFLAGS),
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COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", CLK_SET_RATE_PARENT,
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COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", 0,
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RK3399_CLKSEL_CON(97), 0,
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RK3399_CLKGATE_CON(8), 7, GFLAGS,
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&rk3399_i2s1_fracmux),
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@ -619,7 +619,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
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COMPOSITE(0, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, 0,
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RK3399_CLKSEL_CON(30), 7, 1, MFLAGS, 0, 7, DFLAGS,
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RK3399_CLKGATE_CON(8), 9, GFLAGS),
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COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", CLK_SET_RATE_PARENT,
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COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", 0,
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RK3399_CLKSEL_CON(98), 0,
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RK3399_CLKGATE_CON(8), 10, GFLAGS,
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&rk3399_i2s2_fracmux),
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@ -638,7 +638,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
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COMPOSITE_NOMUX(0, "clk_uart0_div", "clk_uart0_src", 0,
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RK3399_CLKSEL_CON(33), 0, 7, DFLAGS,
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RK3399_CLKGATE_CON(9), 0, GFLAGS),
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COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", CLK_SET_RATE_PARENT,
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COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", 0,
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RK3399_CLKSEL_CON(100), 0,
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RK3399_CLKGATE_CON(9), 1, GFLAGS,
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&rk3399_uart0_fracmux),
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@ -648,7 +648,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
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COMPOSITE_NOMUX(0, "clk_uart1_div", "clk_uart_src", 0,
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RK3399_CLKSEL_CON(34), 0, 7, DFLAGS,
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RK3399_CLKGATE_CON(9), 2, GFLAGS),
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COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", CLK_SET_RATE_PARENT,
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COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", 0,
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RK3399_CLKSEL_CON(101), 0,
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RK3399_CLKGATE_CON(9), 3, GFLAGS,
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&rk3399_uart1_fracmux),
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@ -656,7 +656,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
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COMPOSITE_NOMUX(0, "clk_uart2_div", "clk_uart_src", 0,
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RK3399_CLKSEL_CON(35), 0, 7, DFLAGS,
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RK3399_CLKGATE_CON(9), 4, GFLAGS),
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COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", CLK_SET_RATE_PARENT,
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COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", 0,
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RK3399_CLKSEL_CON(102), 0,
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RK3399_CLKGATE_CON(9), 5, GFLAGS,
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&rk3399_uart2_fracmux),
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@ -664,7 +664,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
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COMPOSITE_NOMUX(0, "clk_uart3_div", "clk_uart_src", 0,
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RK3399_CLKSEL_CON(36), 0, 7, DFLAGS,
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RK3399_CLKGATE_CON(9), 6, GFLAGS),
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COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_div", CLK_SET_RATE_PARENT,
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COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_div", 0,
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RK3399_CLKSEL_CON(103), 0,
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RK3399_CLKGATE_CON(9), 7, GFLAGS,
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&rk3399_uart3_fracmux),
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@ -1168,7 +1168,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
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RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS,
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RK3399_CLKGATE_CON(10), 12, GFLAGS),
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COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop0_frac", "dclk_vop0_div", CLK_SET_RATE_PARENT,
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COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop0_frac", "dclk_vop0_div", 0,
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RK3399_CLKSEL_CON(106), 0,
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&rk3399_dclk_vop0_fracmux),
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@ -1198,7 +1198,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
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RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS,
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RK3399_CLKGATE_CON(10), 13, GFLAGS),
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COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop1_frac", "dclk_vop1_div", CLK_SET_RATE_PARENT,
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COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop1_frac", "dclk_vop1_div", 0,
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RK3399_CLKSEL_CON(107), 0,
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&rk3399_dclk_vop1_fracmux),
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@ -1312,7 +1312,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
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/* testout */
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MUX(0, "clk_test_pre", mux_pll_src_cpll_gpll_p, CLK_SET_RATE_PARENT,
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RK3399_CLKSEL_CON(58), 7, 1, MFLAGS),
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COMPOSITE_FRAC(0, "clk_test_frac", "clk_test_pre", CLK_SET_RATE_PARENT,
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COMPOSITE_FRAC(0, "clk_test_frac", "clk_test_pre", 0,
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RK3399_CLKSEL_CON(105), 0,
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RK3399_CLKGATE_CON(13), 9, GFLAGS),
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@ -1417,7 +1417,7 @@ static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = {
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RK3399_PMU_CLKSEL_CON(1), 13, 1, MFLAGS, 8, 5, DFLAGS,
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RK3399_PMU_CLKGATE_CON(0), 8, GFLAGS),
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COMPOSITE_FRACMUX_NOGATE(0, "clk_wifi_frac", "clk_wifi_div", CLK_SET_RATE_PARENT,
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COMPOSITE_FRACMUX_NOGATE(0, "clk_wifi_frac", "clk_wifi_div", 0,
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RK3399_PMU_CLKSEL_CON(7), 0,
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&rk3399_pmuclk_wifi_fracmux),
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@ -1445,7 +1445,7 @@ static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = {
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RK3399_PMU_CLKSEL_CON(5), 10, 1, MFLAGS, 0, 7, DFLAGS,
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RK3399_PMU_CLKGATE_CON(0), 5, GFLAGS),
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COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_div", CLK_SET_RATE_PARENT,
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COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_div", 0,
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RK3399_PMU_CLKSEL_CON(6), 0,
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RK3399_PMU_CLKGATE_CON(0), 6, GFLAGS,
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&rk3399_uart4_pmu_fracmux),
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