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drm/i915: correct self-refresh calculation in "everything off" case 

If no planes are enabled, the self-refresh calculation may end up doing
a divide by zero.  This patch should prevent that by making sure at
least one of the CRTCs had a valid hdisplay value.

Reported-by: Eric Anholt <eric@anholt.net>
Tested-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Jesse Barnes 2009-07-16 13:01:02 -07:00 committed by Eric Anholt
parent 390c4dd448
commit 2a2430f454
1 changed files with 3 additions and 3 deletions
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6
drivers/gpu/drm/i915/intel_display.c
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@ -1906,7 +1906,7 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
cwm = 2;
/* Calc sr entries for one plane configs */
if (!planea_clock || !planeb_clock) {
if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
/* self-refresh has much higher latency */
const static int sr_latency_ns = 6000;
@ -1921,6 +1921,8 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
srwm = total_size - sr_entries;
if (srwm < 0)
srwm = 1;
if (IS_I9XX(dev))
I915_WRITE(FW_BLC_SELF, (srwm & 0x3f));
}
DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
@ -1935,8 +1937,6 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
I915_WRITE(FW_BLC, fwater_lo);
I915_WRITE(FW_BLC2, fwater_hi);
if (IS_I9XX(dev))
I915_WRITE(FW_BLC_SELF, (srwm & 0x3f));
}
static void i830_update_wm(struct drm_device *dev, int planea_clock,