mirror of https://gitee.com/openkylin/linux.git
drm/nouveau/disp: split user classes out from engine implementations
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
parent
0710cc3148
commit
2a7909c0ad
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@ -13,12 +13,6 @@ struct nvkm_disp {
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struct nvkm_event vblank;
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};
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static inline struct nvkm_disp *
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nvkm_disp(void *obj)
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{
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return (void *)nvkm_engine(obj, NVDEV_ENGINE_DISP);
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}
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extern struct nvkm_oclass *nv04_disp_oclass;
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extern struct nvkm_oclass *nv50_disp_oclass;
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extern struct nvkm_oclass *g84_disp_oclass;
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@ -5,7 +5,7 @@ nvkm-y += nvkm/engine/disp/g84.o
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nvkm-y += nvkm/engine/disp/g94.o
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nvkm-y += nvkm/engine/disp/gt200.o
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nvkm-y += nvkm/engine/disp/gt215.o
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nvkm-y += nvkm/engine/disp/gf110.o
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nvkm-y += nvkm/engine/disp/gf119.o
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nvkm-y += nvkm/engine/disp/gk104.o
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nvkm-y += nvkm/engine/disp/gk110.o
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nvkm-y += nvkm/engine/disp/gm107.o
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@ -17,18 +17,61 @@ nvkm-y += nvkm/engine/disp/dacnv50.o
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nvkm-y += nvkm/engine/disp/piornv50.o
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nvkm-y += nvkm/engine/disp/sornv50.o
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nvkm-y += nvkm/engine/disp/sorg94.o
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nvkm-y += nvkm/engine/disp/sorgf110.o
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nvkm-y += nvkm/engine/disp/sorgf119.o
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nvkm-y += nvkm/engine/disp/sorgm204.o
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nvkm-y += nvkm/engine/disp/dport.o
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nvkm-y += nvkm/engine/disp/conn.o
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nvkm-y += nvkm/engine/disp/hdagt215.o
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nvkm-y += nvkm/engine/disp/hdagf110.o
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nvkm-y += nvkm/engine/disp/hdagf119.o
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nvkm-y += nvkm/engine/disp/hdmig84.o
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nvkm-y += nvkm/engine/disp/hdmigt215.o
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nvkm-y += nvkm/engine/disp/hdmigf110.o
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nvkm-y += nvkm/engine/disp/hdmigf119.o
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nvkm-y += nvkm/engine/disp/hdmigk104.o
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nvkm-y += nvkm/engine/disp/vga.o
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nvkm-y += nvkm/engine/disp/rootnv04.o
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nvkm-y += nvkm/engine/disp/rootnv50.o
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nvkm-y += nvkm/engine/disp/rootg84.o
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nvkm-y += nvkm/engine/disp/rootg94.o
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nvkm-y += nvkm/engine/disp/rootgt200.o
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nvkm-y += nvkm/engine/disp/rootgt215.o
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nvkm-y += nvkm/engine/disp/rootgf119.o
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nvkm-y += nvkm/engine/disp/rootgk104.o
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nvkm-y += nvkm/engine/disp/rootgk110.o
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nvkm-y += nvkm/engine/disp/rootgm107.o
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nvkm-y += nvkm/engine/disp/rootgm204.o
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nvkm-y += nvkm/engine/disp/channv50.o
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nvkm-y += nvkm/engine/disp/changf119.o
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nvkm-y += nvkm/engine/disp/dmacnv50.o
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nvkm-y += nvkm/engine/disp/dmacgf119.o
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nvkm-y += nvkm/engine/disp/basenv50.o
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nvkm-y += nvkm/engine/disp/baseg84.o
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nvkm-y += nvkm/engine/disp/basegf119.o
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nvkm-y += nvkm/engine/disp/corenv50.o
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nvkm-y += nvkm/engine/disp/coreg84.o
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nvkm-y += nvkm/engine/disp/coreg94.o
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nvkm-y += nvkm/engine/disp/coregf119.o
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nvkm-y += nvkm/engine/disp/coregk104.o
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nvkm-y += nvkm/engine/disp/ovlynv50.o
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nvkm-y += nvkm/engine/disp/ovlyg84.o
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nvkm-y += nvkm/engine/disp/ovlygt200.o
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nvkm-y += nvkm/engine/disp/ovlygf119.o
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nvkm-y += nvkm/engine/disp/ovlygk104.o
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nvkm-y += nvkm/engine/disp/piocnv50.o
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nvkm-y += nvkm/engine/disp/piocgf119.o
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nvkm-y += nvkm/engine/disp/cursnv50.o
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nvkm-y += nvkm/engine/disp/cursgf119.o
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nvkm-y += nvkm/engine/disp/oimmnv50.o
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nvkm-y += nvkm/engine/disp/oimmgf119.o
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@ -0,0 +1,65 @@
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/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "dmacnv50.h"
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static const struct nv50_disp_mthd_list
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g84_disp_base_mthd_base = {
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.mthd = 0x0000,
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.addr = 0x000000,
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.data = {
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{ 0x0080, 0x000000 },
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{ 0x0084, 0x0008c4 },
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{ 0x0088, 0x0008d0 },
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{ 0x008c, 0x0008dc },
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{ 0x0090, 0x0008e4 },
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{ 0x0094, 0x610884 },
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{ 0x00a0, 0x6108a0 },
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{ 0x00a4, 0x610878 },
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{ 0x00c0, 0x61086c },
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{ 0x00c4, 0x610800 },
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{ 0x00c8, 0x61080c },
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{ 0x00cc, 0x610818 },
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{ 0x00e0, 0x610858 },
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{ 0x00e4, 0x610860 },
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{ 0x00e8, 0x6108ac },
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{ 0x00ec, 0x6108b4 },
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{ 0x00fc, 0x610824 },
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{ 0x0100, 0x610894 },
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{ 0x0104, 0x61082c },
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{ 0x0110, 0x6108bc },
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{ 0x0114, 0x61088c },
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{}
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}
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};
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const struct nv50_disp_mthd_chan
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g84_disp_base_mthd_chan = {
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.name = "Base",
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.addr = 0x000540,
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.data = {
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{ "Global", 1, &g84_disp_base_mthd_base },
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{ "Image", 2, &nv50_disp_base_mthd_image },
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{}
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}
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};
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@ -0,0 +1,114 @@
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/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "dmacnv50.h"
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static const struct nv50_disp_mthd_list
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gf119_disp_base_mthd_base = {
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.mthd = 0x0000,
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.addr = 0x000000,
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.data = {
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{ 0x0080, 0x661080 },
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{ 0x0084, 0x661084 },
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{ 0x0088, 0x661088 },
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{ 0x008c, 0x66108c },
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{ 0x0090, 0x661090 },
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{ 0x0094, 0x661094 },
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{ 0x00a0, 0x6610a0 },
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{ 0x00a4, 0x6610a4 },
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{ 0x00c0, 0x6610c0 },
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{ 0x00c4, 0x6610c4 },
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{ 0x00c8, 0x6610c8 },
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{ 0x00cc, 0x6610cc },
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{ 0x00e0, 0x6610e0 },
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{ 0x00e4, 0x6610e4 },
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{ 0x00e8, 0x6610e8 },
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{ 0x00ec, 0x6610ec },
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{ 0x00fc, 0x6610fc },
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{ 0x0100, 0x661100 },
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{ 0x0104, 0x661104 },
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{ 0x0108, 0x661108 },
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{ 0x010c, 0x66110c },
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{ 0x0110, 0x661110 },
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{ 0x0114, 0x661114 },
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{ 0x0118, 0x661118 },
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{ 0x011c, 0x66111c },
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{ 0x0130, 0x661130 },
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{ 0x0134, 0x661134 },
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{ 0x0138, 0x661138 },
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{ 0x013c, 0x66113c },
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{ 0x0140, 0x661140 },
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{ 0x0144, 0x661144 },
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{ 0x0148, 0x661148 },
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{ 0x014c, 0x66114c },
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{ 0x0150, 0x661150 },
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{ 0x0154, 0x661154 },
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{ 0x0158, 0x661158 },
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{ 0x015c, 0x66115c },
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{ 0x0160, 0x661160 },
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{ 0x0164, 0x661164 },
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{ 0x0168, 0x661168 },
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{ 0x016c, 0x66116c },
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{}
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}
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};
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static const struct nv50_disp_mthd_list
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gf119_disp_base_mthd_image = {
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.mthd = 0x0020,
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.addr = 0x000020,
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.data = {
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{ 0x0400, 0x661400 },
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{ 0x0404, 0x661404 },
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{ 0x0408, 0x661408 },
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{ 0x040c, 0x66140c },
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{ 0x0410, 0x661410 },
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{}
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}
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};
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const struct nv50_disp_mthd_chan
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gf119_disp_base_mthd_chan = {
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.name = "Base",
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.addr = 0x001000,
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.data = {
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{ "Global", 1, &gf119_disp_base_mthd_base },
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{ "Image", 2, &gf119_disp_base_mthd_image },
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{}
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}
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};
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struct nv50_disp_chan_impl
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gf119_disp_base_ofuncs = {
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.base.ctor = nv50_disp_base_ctor,
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.base.dtor = nv50_disp_dmac_dtor,
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.base.init = gf119_disp_dmac_init,
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.base.fini = gf119_disp_dmac_fini,
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.base.ntfy = nv50_disp_chan_ntfy,
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.base.map = nv50_disp_chan_map,
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.base.rd32 = nv50_disp_chan_rd32,
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.base.wr32 = nv50_disp_chan_wr32,
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.chid = 1,
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.attach = gf119_disp_dmac_object_attach,
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.detach = gf119_disp_dmac_object_detach,
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};
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@ -0,0 +1,127 @@
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/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
|
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* all copies or substantial portions of the Software.
|
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "dmacnv50.h"
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#include <core/client.h>
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#include <nvif/class.h>
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#include <nvif/unpack.h>
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static const struct nv50_disp_mthd_list
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nv50_disp_base_mthd_base = {
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.mthd = 0x0000,
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.addr = 0x000000,
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.data = {
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{ 0x0080, 0x000000 },
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{ 0x0084, 0x0008c4 },
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{ 0x0088, 0x0008d0 },
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{ 0x008c, 0x0008dc },
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{ 0x0090, 0x0008e4 },
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{ 0x0094, 0x610884 },
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{ 0x00a0, 0x6108a0 },
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{ 0x00a4, 0x610878 },
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{ 0x00c0, 0x61086c },
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{ 0x00e0, 0x610858 },
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{ 0x00e4, 0x610860 },
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{ 0x00e8, 0x6108ac },
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{ 0x00ec, 0x6108b4 },
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{ 0x0100, 0x610894 },
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{ 0x0110, 0x6108bc },
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{ 0x0114, 0x61088c },
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{}
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}
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};
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const struct nv50_disp_mthd_list
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nv50_disp_base_mthd_image = {
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.mthd = 0x0400,
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.addr = 0x000000,
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.data = {
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{ 0x0800, 0x6108f0 },
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{ 0x0804, 0x6108fc },
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{ 0x0808, 0x61090c },
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{ 0x080c, 0x610914 },
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{ 0x0810, 0x610904 },
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{}
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}
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};
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const struct nv50_disp_mthd_chan
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nv50_disp_base_mthd_chan = {
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.name = "Base",
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.addr = 0x000540,
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.data = {
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{ "Global", 1, &nv50_disp_base_mthd_base },
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{ "Image", 2, &nv50_disp_base_mthd_image },
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{}
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}
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};
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int
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nv50_disp_base_ctor(struct nvkm_object *parent,
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struct nvkm_object *engine,
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struct nvkm_oclass *oclass, void *data, u32 size,
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struct nvkm_object **pobject)
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{
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union {
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struct nv50_disp_base_channel_dma_v0 v0;
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} *args = data;
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struct nv50_disp *disp = (void *)engine;
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struct nv50_disp_dmac *dmac;
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int ret;
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nvif_ioctl(parent, "create disp base channel dma size %d\n", size);
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if (nvif_unpack(args->v0, 0, 0, false)) {
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nvif_ioctl(parent, "create disp base channel dma vers %d "
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"pushbuf %016llx head %d\n",
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args->v0.version, args->v0.pushbuf, args->v0.head);
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if (args->v0.head > disp->head.nr)
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return -EINVAL;
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} else
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return ret;
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ret = nv50_disp_dmac_create_(parent, engine, oclass, args->v0.pushbuf,
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args->v0.head, sizeof(*dmac),
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(void **)&dmac);
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*pobject = nv_object(dmac);
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if (ret)
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return ret;
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return 0;
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}
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struct nv50_disp_chan_impl
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nv50_disp_base_ofuncs = {
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.base.ctor = nv50_disp_base_ctor,
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.base.dtor = nv50_disp_dmac_dtor,
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.base.init = nv50_disp_dmac_init,
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.base.fini = nv50_disp_dmac_fini,
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.base.ntfy = nv50_disp_chan_ntfy,
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.base.map = nv50_disp_chan_map,
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.base.rd32 = nv50_disp_chan_rd32,
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.base.wr32 = nv50_disp_chan_wr32,
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.chid = 1,
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.attach = nv50_disp_dmac_object_attach,
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.detach = nv50_disp_dmac_object_detach,
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};
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@ -0,0 +1,49 @@
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/*
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* Copyright 2012 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "channv50.h"
|
||||
|
||||
static void
|
||||
gf119_disp_chan_uevent_fini(struct nvkm_event *event, int type, int index)
|
||||
{
|
||||
struct nv50_disp *disp = container_of(event, typeof(*disp), uevent);
|
||||
struct nvkm_device *device = disp->base.engine.subdev.device;
|
||||
nvkm_mask(device, 0x610090, 0x00000001 << index, 0x00000000 << index);
|
||||
nvkm_wr32(device, 0x61008c, 0x00000001 << index);
|
||||
}
|
||||
|
||||
static void
|
||||
gf119_disp_chan_uevent_init(struct nvkm_event *event, int types, int index)
|
||||
{
|
||||
struct nv50_disp *disp = container_of(event, typeof(*disp), uevent);
|
||||
struct nvkm_device *device = disp->base.engine.subdev.device;
|
||||
nvkm_wr32(device, 0x61008c, 0x00000001 << index);
|
||||
nvkm_mask(device, 0x610090, 0x00000001 << index, 0x00000001 << index);
|
||||
}
|
||||
|
||||
const struct nvkm_event_func
|
||||
gf119_disp_chan_uevent = {
|
||||
.ctor = nv50_disp_chan_uevent_ctor,
|
||||
.init = gf119_disp_chan_uevent_init,
|
||||
.fini = gf119_disp_chan_uevent_fini,
|
||||
};
|
|
@ -0,0 +1,229 @@
|
|||
/*
|
||||
* Copyright 2012 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "channv50.h"
|
||||
#include "rootnv50.h"
|
||||
|
||||
#include <nvif/class.h>
|
||||
#include <nvif/event.h>
|
||||
#include <nvif/unpack.h>
|
||||
|
||||
static void
|
||||
nv50_disp_mthd_list(struct nv50_disp *disp, int debug, u32 base, int c,
|
||||
const struct nv50_disp_mthd_list *list, int inst)
|
||||
{
|
||||
struct nvkm_subdev *subdev = &disp->base.engine.subdev;
|
||||
struct nvkm_device *device = subdev->device;
|
||||
int i;
|
||||
|
||||
for (i = 0; list->data[i].mthd; i++) {
|
||||
if (list->data[i].addr) {
|
||||
u32 next = nvkm_rd32(device, list->data[i].addr + base + 0);
|
||||
u32 prev = nvkm_rd32(device, list->data[i].addr + base + c);
|
||||
u32 mthd = list->data[i].mthd + (list->mthd * inst);
|
||||
const char *name = list->data[i].name;
|
||||
char mods[16];
|
||||
|
||||
if (prev != next)
|
||||
snprintf(mods, sizeof(mods), "-> %08x", next);
|
||||
else
|
||||
snprintf(mods, sizeof(mods), "%13c", ' ');
|
||||
|
||||
nvkm_printk_(subdev, debug, info,
|
||||
"\t%04x: %08x %s%s%s\n",
|
||||
mthd, prev, mods, name ? " // " : "",
|
||||
name ? name : "");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
nv50_disp_mthd_chan(struct nv50_disp *disp, int debug, int head,
|
||||
const struct nv50_disp_mthd_chan *chan)
|
||||
{
|
||||
struct nvkm_object *object = nv_object(disp);
|
||||
const struct nv50_disp_impl *impl = (void *)object->oclass;
|
||||
const struct nv50_disp_mthd_list *list;
|
||||
struct nvkm_subdev *subdev = &disp->base.engine.subdev;
|
||||
int i, j;
|
||||
|
||||
if (debug > nv_subdev(disp)->debug)
|
||||
return;
|
||||
|
||||
for (i = 0; (list = chan->data[i].mthd) != NULL; i++) {
|
||||
u32 base = head * chan->addr;
|
||||
for (j = 0; j < chan->data[i].nr; j++, base += list->addr) {
|
||||
const char *cname = chan->name;
|
||||
const char *sname = "";
|
||||
char cname_[16], sname_[16];
|
||||
|
||||
if (chan->addr) {
|
||||
snprintf(cname_, sizeof(cname_), "%s %d",
|
||||
chan->name, head);
|
||||
cname = cname_;
|
||||
}
|
||||
|
||||
if (chan->data[i].nr > 1) {
|
||||
snprintf(sname_, sizeof(sname_), " - %s %d",
|
||||
chan->data[i].name, j);
|
||||
sname = sname_;
|
||||
}
|
||||
|
||||
nvkm_printk_(subdev, debug, info, "%s%s:\n", cname, sname);
|
||||
nv50_disp_mthd_list(disp, debug, base, impl->mthd.prev,
|
||||
list, j);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
nv50_disp_chan_uevent_fini(struct nvkm_event *event, int type, int index)
|
||||
{
|
||||
struct nv50_disp *disp = container_of(event, typeof(*disp), uevent);
|
||||
struct nvkm_device *device = disp->base.engine.subdev.device;
|
||||
nvkm_mask(device, 0x610028, 0x00000001 << index, 0x00000000 << index);
|
||||
nvkm_wr32(device, 0x610020, 0x00000001 << index);
|
||||
}
|
||||
|
||||
static void
|
||||
nv50_disp_chan_uevent_init(struct nvkm_event *event, int types, int index)
|
||||
{
|
||||
struct nv50_disp *disp = container_of(event, typeof(*disp), uevent);
|
||||
struct nvkm_device *device = disp->base.engine.subdev.device;
|
||||
nvkm_wr32(device, 0x610020, 0x00000001 << index);
|
||||
nvkm_mask(device, 0x610028, 0x00000001 << index, 0x00000001 << index);
|
||||
}
|
||||
|
||||
void
|
||||
nv50_disp_chan_uevent_send(struct nv50_disp *disp, int chid)
|
||||
{
|
||||
struct nvif_notify_uevent_rep {
|
||||
} rep;
|
||||
|
||||
nvkm_event_send(&disp->uevent, 1, chid, &rep, sizeof(rep));
|
||||
}
|
||||
|
||||
int
|
||||
nv50_disp_chan_uevent_ctor(struct nvkm_object *object, void *data, u32 size,
|
||||
struct nvkm_notify *notify)
|
||||
{
|
||||
struct nv50_disp_dmac *dmac = (void *)object;
|
||||
union {
|
||||
struct nvif_notify_uevent_req none;
|
||||
} *args = data;
|
||||
int ret;
|
||||
|
||||
if (nvif_unvers(args->none)) {
|
||||
notify->size = sizeof(struct nvif_notify_uevent_rep);
|
||||
notify->types = 1;
|
||||
notify->index = dmac->base.chid;
|
||||
return 0;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
const struct nvkm_event_func
|
||||
nv50_disp_chan_uevent = {
|
||||
.ctor = nv50_disp_chan_uevent_ctor,
|
||||
.init = nv50_disp_chan_uevent_init,
|
||||
.fini = nv50_disp_chan_uevent_fini,
|
||||
};
|
||||
|
||||
int
|
||||
nv50_disp_chan_ntfy(struct nvkm_object *object, u32 type,
|
||||
struct nvkm_event **pevent)
|
||||
{
|
||||
struct nv50_disp *disp = (void *)object->engine;
|
||||
switch (type) {
|
||||
case NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT:
|
||||
*pevent = &disp->uevent;
|
||||
return 0;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
int
|
||||
nv50_disp_chan_map(struct nvkm_object *object, u64 *addr, u32 *size)
|
||||
{
|
||||
struct nv50_disp_chan *chan = (void *)object;
|
||||
*addr = nv_device_resource_start(nv_device(object), 0) +
|
||||
0x640000 + (chan->chid * 0x1000);
|
||||
*size = 0x001000;
|
||||
return 0;
|
||||
}
|
||||
|
||||
u32
|
||||
nv50_disp_chan_rd32(struct nvkm_object *object, u64 addr)
|
||||
{
|
||||
struct nv50_disp_chan *chan = (void *)object;
|
||||
struct nvkm_device *device = object->engine->subdev.device;
|
||||
return nvkm_rd32(device, 0x640000 + (chan->chid * 0x1000) + addr);
|
||||
}
|
||||
|
||||
void
|
||||
nv50_disp_chan_wr32(struct nvkm_object *object, u64 addr, u32 data)
|
||||
{
|
||||
struct nv50_disp_chan *chan = (void *)object;
|
||||
struct nvkm_device *device = object->engine->subdev.device;
|
||||
nvkm_wr32(device, 0x640000 + (chan->chid * 0x1000) + addr, data);
|
||||
}
|
||||
|
||||
void
|
||||
nv50_disp_chan_destroy(struct nv50_disp_chan *chan)
|
||||
{
|
||||
struct nv50_disp_root *root = (void *)nv_object(chan)->parent;
|
||||
root->chan &= ~(1 << chan->chid);
|
||||
nvkm_namedb_destroy(&chan->base);
|
||||
}
|
||||
|
||||
int
|
||||
nv50_disp_chan_create_(struct nvkm_object *parent,
|
||||
struct nvkm_object *engine,
|
||||
struct nvkm_oclass *oclass, int head,
|
||||
int length, void **pobject)
|
||||
{
|
||||
const struct nv50_disp_chan_impl *impl = (void *)oclass->ofuncs;
|
||||
struct nv50_disp_root *root = (void *)parent;
|
||||
struct nv50_disp_chan *chan;
|
||||
int chid = impl->chid + head;
|
||||
int ret;
|
||||
|
||||
if (root->chan & (1 << chid))
|
||||
return -EBUSY;
|
||||
root->chan |= (1 << chid);
|
||||
|
||||
ret = nvkm_namedb_create_(parent, engine, oclass, 0, NULL,
|
||||
(1ULL << NVDEV_ENGINE_DMAOBJ),
|
||||
length, pobject);
|
||||
chan = *pobject;
|
||||
if (ret)
|
||||
return ret;
|
||||
chan->chid = chid;
|
||||
|
||||
nv_parent(chan)->object_attach = impl->attach;
|
||||
nv_parent(chan)->object_detach = impl->detach;
|
||||
return 0;
|
||||
}
|
|
@ -0,0 +1,103 @@
|
|||
#ifndef __NV50_DISP_CHAN_H__
|
||||
#define __NV50_DISP_CHAN_H__
|
||||
#include "nv50.h"
|
||||
|
||||
struct nv50_disp_chan_impl {
|
||||
struct nvkm_ofuncs base;
|
||||
int chid;
|
||||
int (*attach)(struct nvkm_object *, struct nvkm_object *, u32);
|
||||
void (*detach)(struct nvkm_object *, int);
|
||||
};
|
||||
|
||||
#include <core/namedb.h>
|
||||
|
||||
struct nv50_disp_chan {
|
||||
struct nvkm_namedb base;
|
||||
int chid;
|
||||
};
|
||||
|
||||
int nv50_disp_chan_create_(struct nvkm_object *, struct nvkm_object *,
|
||||
struct nvkm_oclass *, int, int, void **);
|
||||
void nv50_disp_chan_destroy(struct nv50_disp_chan *);
|
||||
int nv50_disp_chan_ntfy(struct nvkm_object *, u32, struct nvkm_event **);
|
||||
int nv50_disp_chan_map(struct nvkm_object *, u64 *, u32 *);
|
||||
u32 nv50_disp_chan_rd32(struct nvkm_object *, u64);
|
||||
void nv50_disp_chan_wr32(struct nvkm_object *, u64, u32);
|
||||
extern const struct nvkm_event_func nv50_disp_chan_uevent;
|
||||
int nv50_disp_chan_uevent_ctor(struct nvkm_object *, void *, u32,
|
||||
struct nvkm_notify *);
|
||||
void nv50_disp_chan_uevent_send(struct nv50_disp *, int);
|
||||
|
||||
extern const struct nvkm_event_func gf119_disp_chan_uevent;
|
||||
|
||||
#define nv50_disp_chan_init(a) \
|
||||
nvkm_namedb_init(&(a)->base)
|
||||
#define nv50_disp_chan_fini(a,b) \
|
||||
nvkm_namedb_fini(&(a)->base, (b))
|
||||
|
||||
struct nv50_disp_pioc {
|
||||
struct nv50_disp_chan base;
|
||||
};
|
||||
|
||||
int nv50_disp_pioc_create_(struct nvkm_object *, struct nvkm_object *,
|
||||
struct nvkm_oclass *, int, int, void **);
|
||||
void nv50_disp_pioc_dtor(struct nvkm_object *);
|
||||
int nv50_disp_pioc_init(struct nvkm_object *);
|
||||
int nv50_disp_pioc_fini(struct nvkm_object *, bool);
|
||||
|
||||
int gf119_disp_pioc_init(struct nvkm_object *);
|
||||
int gf119_disp_pioc_fini(struct nvkm_object *, bool);
|
||||
|
||||
struct nv50_disp_mthd_list {
|
||||
u32 mthd;
|
||||
u32 addr;
|
||||
struct {
|
||||
u32 mthd;
|
||||
u32 addr;
|
||||
const char *name;
|
||||
} data[];
|
||||
};
|
||||
|
||||
struct nv50_disp_mthd_chan {
|
||||
const char *name;
|
||||
u32 addr;
|
||||
struct {
|
||||
const char *name;
|
||||
int nr;
|
||||
const struct nv50_disp_mthd_list *mthd;
|
||||
} data[];
|
||||
};
|
||||
|
||||
void nv50_disp_mthd_chan(struct nv50_disp *, int debug, int head,
|
||||
const struct nv50_disp_mthd_chan *);
|
||||
|
||||
extern const struct nv50_disp_mthd_chan nv50_disp_core_mthd_chan;
|
||||
extern const struct nv50_disp_mthd_list nv50_disp_core_mthd_base;
|
||||
extern const struct nv50_disp_mthd_list nv50_disp_core_mthd_sor;
|
||||
extern const struct nv50_disp_mthd_list nv50_disp_core_mthd_pior;
|
||||
extern const struct nv50_disp_mthd_chan nv50_disp_base_mthd_chan;
|
||||
extern const struct nv50_disp_mthd_list nv50_disp_base_mthd_image;
|
||||
extern const struct nv50_disp_mthd_chan nv50_disp_ovly_mthd_chan;
|
||||
extern const struct nv50_disp_mthd_list nv50_disp_ovly_mthd_base;
|
||||
|
||||
extern const struct nv50_disp_mthd_chan g84_disp_core_mthd_chan;
|
||||
extern const struct nv50_disp_mthd_list g84_disp_core_mthd_dac;
|
||||
extern const struct nv50_disp_mthd_list g84_disp_core_mthd_head;
|
||||
extern const struct nv50_disp_mthd_chan g84_disp_base_mthd_chan;
|
||||
extern const struct nv50_disp_mthd_chan g84_disp_ovly_mthd_chan;
|
||||
|
||||
extern const struct nv50_disp_mthd_chan g94_disp_core_mthd_chan;
|
||||
|
||||
extern const struct nv50_disp_mthd_chan gt200_disp_ovly_mthd_chan;
|
||||
|
||||
extern const struct nv50_disp_mthd_chan gf119_disp_core_mthd_chan;
|
||||
extern const struct nv50_disp_mthd_list gf119_disp_core_mthd_base;
|
||||
extern const struct nv50_disp_mthd_list gf119_disp_core_mthd_dac;
|
||||
extern const struct nv50_disp_mthd_list gf119_disp_core_mthd_sor;
|
||||
extern const struct nv50_disp_mthd_list gf119_disp_core_mthd_pior;
|
||||
extern const struct nv50_disp_mthd_chan gf119_disp_base_mthd_chan;
|
||||
extern const struct nv50_disp_mthd_chan gf119_disp_ovly_mthd_chan;
|
||||
|
||||
extern const struct nv50_disp_mthd_chan gk104_disp_core_mthd_chan;
|
||||
extern const struct nv50_disp_mthd_chan gk104_disp_ovly_mthd_chan;
|
||||
#endif
|
|
@ -0,0 +1,102 @@
|
|||
/*
|
||||
* Copyright 2012 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "dmacnv50.h"
|
||||
|
||||
const struct nv50_disp_mthd_list
|
||||
g84_disp_core_mthd_dac = {
|
||||
.mthd = 0x0080,
|
||||
.addr = 0x000008,
|
||||
.data = {
|
||||
{ 0x0400, 0x610b58 },
|
||||
{ 0x0404, 0x610bdc },
|
||||
{ 0x0420, 0x610bc4 },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
const struct nv50_disp_mthd_list
|
||||
g84_disp_core_mthd_head = {
|
||||
.mthd = 0x0400,
|
||||
.addr = 0x000540,
|
||||
.data = {
|
||||
{ 0x0800, 0x610ad8 },
|
||||
{ 0x0804, 0x610ad0 },
|
||||
{ 0x0808, 0x610a48 },
|
||||
{ 0x080c, 0x610a78 },
|
||||
{ 0x0810, 0x610ac0 },
|
||||
{ 0x0814, 0x610af8 },
|
||||
{ 0x0818, 0x610b00 },
|
||||
{ 0x081c, 0x610ae8 },
|
||||
{ 0x0820, 0x610af0 },
|
||||
{ 0x0824, 0x610b08 },
|
||||
{ 0x0828, 0x610b10 },
|
||||
{ 0x082c, 0x610a68 },
|
||||
{ 0x0830, 0x610a60 },
|
||||
{ 0x0834, 0x000000 },
|
||||
{ 0x0838, 0x610a40 },
|
||||
{ 0x0840, 0x610a24 },
|
||||
{ 0x0844, 0x610a2c },
|
||||
{ 0x0848, 0x610aa8 },
|
||||
{ 0x084c, 0x610ab0 },
|
||||
{ 0x085c, 0x610c5c },
|
||||
{ 0x0860, 0x610a84 },
|
||||
{ 0x0864, 0x610a90 },
|
||||
{ 0x0868, 0x610b18 },
|
||||
{ 0x086c, 0x610b20 },
|
||||
{ 0x0870, 0x610ac8 },
|
||||
{ 0x0874, 0x610a38 },
|
||||
{ 0x0878, 0x610c50 },
|
||||
{ 0x0880, 0x610a58 },
|
||||
{ 0x0884, 0x610a9c },
|
||||
{ 0x089c, 0x610c68 },
|
||||
{ 0x08a0, 0x610a70 },
|
||||
{ 0x08a4, 0x610a50 },
|
||||
{ 0x08a8, 0x610ae0 },
|
||||
{ 0x08c0, 0x610b28 },
|
||||
{ 0x08c4, 0x610b30 },
|
||||
{ 0x08c8, 0x610b40 },
|
||||
{ 0x08d4, 0x610b38 },
|
||||
{ 0x08d8, 0x610b48 },
|
||||
{ 0x08dc, 0x610b50 },
|
||||
{ 0x0900, 0x610a18 },
|
||||
{ 0x0904, 0x610ab8 },
|
||||
{ 0x0910, 0x610c70 },
|
||||
{ 0x0914, 0x610c78 },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
const struct nv50_disp_mthd_chan
|
||||
g84_disp_core_mthd_chan = {
|
||||
.name = "Core",
|
||||
.addr = 0x000000,
|
||||
.data = {
|
||||
{ "Global", 1, &nv50_disp_core_mthd_base },
|
||||
{ "DAC", 3, &g84_disp_core_mthd_dac },
|
||||
{ "SOR", 2, &nv50_disp_core_mthd_sor },
|
||||
{ "PIOR", 3, &nv50_disp_core_mthd_pior },
|
||||
{ "HEAD", 2, &g84_disp_core_mthd_head },
|
||||
{}
|
||||
}
|
||||
};
|
|
@ -0,0 +1,48 @@
|
|||
/*
|
||||
* Copyright 2012 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "dmacnv50.h"
|
||||
|
||||
const struct nv50_disp_mthd_list
|
||||
g94_disp_core_mthd_sor = {
|
||||
.mthd = 0x0040,
|
||||
.addr = 0x000008,
|
||||
.data = {
|
||||
{ 0x0600, 0x610794 },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
const struct nv50_disp_mthd_chan
|
||||
g94_disp_core_mthd_chan = {
|
||||
.name = "Core",
|
||||
.addr = 0x000000,
|
||||
.data = {
|
||||
{ "Global", 1, &nv50_disp_core_mthd_base },
|
||||
{ "DAC", 3, &g84_disp_core_mthd_dac },
|
||||
{ "SOR", 4, &g94_disp_core_mthd_sor },
|
||||
{ "PIOR", 3, &nv50_disp_core_mthd_pior },
|
||||
{ "HEAD", 2, &g84_disp_core_mthd_head },
|
||||
{}
|
||||
}
|
||||
};
|
|
@ -0,0 +1,246 @@
|
|||
/*
|
||||
* Copyright 2012 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "dmacnv50.h"
|
||||
|
||||
#include <subdev/timer.h>
|
||||
|
||||
const struct nv50_disp_mthd_list
|
||||
gf119_disp_core_mthd_base = {
|
||||
.mthd = 0x0000,
|
||||
.addr = 0x000000,
|
||||
.data = {
|
||||
{ 0x0080, 0x660080 },
|
||||
{ 0x0084, 0x660084 },
|
||||
{ 0x0088, 0x660088 },
|
||||
{ 0x008c, 0x000000 },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
const struct nv50_disp_mthd_list
|
||||
gf119_disp_core_mthd_dac = {
|
||||
.mthd = 0x0020,
|
||||
.addr = 0x000020,
|
||||
.data = {
|
||||
{ 0x0180, 0x660180 },
|
||||
{ 0x0184, 0x660184 },
|
||||
{ 0x0188, 0x660188 },
|
||||
{ 0x0190, 0x660190 },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
const struct nv50_disp_mthd_list
|
||||
gf119_disp_core_mthd_sor = {
|
||||
.mthd = 0x0020,
|
||||
.addr = 0x000020,
|
||||
.data = {
|
||||
{ 0x0200, 0x660200 },
|
||||
{ 0x0204, 0x660204 },
|
||||
{ 0x0208, 0x660208 },
|
||||
{ 0x0210, 0x660210 },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
const struct nv50_disp_mthd_list
|
||||
gf119_disp_core_mthd_pior = {
|
||||
.mthd = 0x0020,
|
||||
.addr = 0x000020,
|
||||
.data = {
|
||||
{ 0x0300, 0x660300 },
|
||||
{ 0x0304, 0x660304 },
|
||||
{ 0x0308, 0x660308 },
|
||||
{ 0x0310, 0x660310 },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
static const struct nv50_disp_mthd_list
|
||||
gf119_disp_core_mthd_head = {
|
||||
.mthd = 0x0300,
|
||||
.addr = 0x000300,
|
||||
.data = {
|
||||
{ 0x0400, 0x660400 },
|
||||
{ 0x0404, 0x660404 },
|
||||
{ 0x0408, 0x660408 },
|
||||
{ 0x040c, 0x66040c },
|
||||
{ 0x0410, 0x660410 },
|
||||
{ 0x0414, 0x660414 },
|
||||
{ 0x0418, 0x660418 },
|
||||
{ 0x041c, 0x66041c },
|
||||
{ 0x0420, 0x660420 },
|
||||
{ 0x0424, 0x660424 },
|
||||
{ 0x0428, 0x660428 },
|
||||
{ 0x042c, 0x66042c },
|
||||
{ 0x0430, 0x660430 },
|
||||
{ 0x0434, 0x660434 },
|
||||
{ 0x0438, 0x660438 },
|
||||
{ 0x0440, 0x660440 },
|
||||
{ 0x0444, 0x660444 },
|
||||
{ 0x0448, 0x660448 },
|
||||
{ 0x044c, 0x66044c },
|
||||
{ 0x0450, 0x660450 },
|
||||
{ 0x0454, 0x660454 },
|
||||
{ 0x0458, 0x660458 },
|
||||
{ 0x045c, 0x66045c },
|
||||
{ 0x0460, 0x660460 },
|
||||
{ 0x0468, 0x660468 },
|
||||
{ 0x046c, 0x66046c },
|
||||
{ 0x0470, 0x660470 },
|
||||
{ 0x0474, 0x660474 },
|
||||
{ 0x0480, 0x660480 },
|
||||
{ 0x0484, 0x660484 },
|
||||
{ 0x048c, 0x66048c },
|
||||
{ 0x0490, 0x660490 },
|
||||
{ 0x0494, 0x660494 },
|
||||
{ 0x0498, 0x660498 },
|
||||
{ 0x04b0, 0x6604b0 },
|
||||
{ 0x04b8, 0x6604b8 },
|
||||
{ 0x04bc, 0x6604bc },
|
||||
{ 0x04c0, 0x6604c0 },
|
||||
{ 0x04c4, 0x6604c4 },
|
||||
{ 0x04c8, 0x6604c8 },
|
||||
{ 0x04d0, 0x6604d0 },
|
||||
{ 0x04d4, 0x6604d4 },
|
||||
{ 0x04e0, 0x6604e0 },
|
||||
{ 0x04e4, 0x6604e4 },
|
||||
{ 0x04e8, 0x6604e8 },
|
||||
{ 0x04ec, 0x6604ec },
|
||||
{ 0x04f0, 0x6604f0 },
|
||||
{ 0x04f4, 0x6604f4 },
|
||||
{ 0x04f8, 0x6604f8 },
|
||||
{ 0x04fc, 0x6604fc },
|
||||
{ 0x0500, 0x660500 },
|
||||
{ 0x0504, 0x660504 },
|
||||
{ 0x0508, 0x660508 },
|
||||
{ 0x050c, 0x66050c },
|
||||
{ 0x0510, 0x660510 },
|
||||
{ 0x0514, 0x660514 },
|
||||
{ 0x0518, 0x660518 },
|
||||
{ 0x051c, 0x66051c },
|
||||
{ 0x052c, 0x66052c },
|
||||
{ 0x0530, 0x660530 },
|
||||
{ 0x054c, 0x66054c },
|
||||
{ 0x0550, 0x660550 },
|
||||
{ 0x0554, 0x660554 },
|
||||
{ 0x0558, 0x660558 },
|
||||
{ 0x055c, 0x66055c },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
const struct nv50_disp_mthd_chan
|
||||
gf119_disp_core_mthd_chan = {
|
||||
.name = "Core",
|
||||
.addr = 0x000000,
|
||||
.data = {
|
||||
{ "Global", 1, &gf119_disp_core_mthd_base },
|
||||
{ "DAC", 3, &gf119_disp_core_mthd_dac },
|
||||
{ "SOR", 8, &gf119_disp_core_mthd_sor },
|
||||
{ "PIOR", 4, &gf119_disp_core_mthd_pior },
|
||||
{ "HEAD", 4, &gf119_disp_core_mthd_head },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
static int
|
||||
gf119_disp_core_fini(struct nvkm_object *object, bool suspend)
|
||||
{
|
||||
struct nv50_disp *disp = (void *)object->engine;
|
||||
struct nv50_disp_dmac *mast = (void *)object;
|
||||
struct nvkm_subdev *subdev = &disp->base.engine.subdev;
|
||||
struct nvkm_device *device = subdev->device;
|
||||
|
||||
/* deactivate channel */
|
||||
nvkm_mask(device, 0x610490, 0x00000010, 0x00000000);
|
||||
nvkm_mask(device, 0x610490, 0x00000003, 0x00000000);
|
||||
if (nvkm_msec(device, 2000,
|
||||
if (!(nvkm_rd32(device, 0x610490) & 0x001e0000))
|
||||
break;
|
||||
) < 0) {
|
||||
nvkm_error(subdev, "core fini: %08x\n",
|
||||
nvkm_rd32(device, 0x610490));
|
||||
if (suspend)
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
/* disable error reporting and completion notification */
|
||||
nvkm_mask(device, 0x610090, 0x00000001, 0x00000000);
|
||||
nvkm_mask(device, 0x6100a0, 0x00000001, 0x00000000);
|
||||
|
||||
return nv50_disp_chan_fini(&mast->base, suspend);
|
||||
}
|
||||
|
||||
static int
|
||||
gf119_disp_core_init(struct nvkm_object *object)
|
||||
{
|
||||
struct nv50_disp *disp = (void *)object->engine;
|
||||
struct nv50_disp_dmac *mast = (void *)object;
|
||||
struct nvkm_subdev *subdev = &disp->base.engine.subdev;
|
||||
struct nvkm_device *device = subdev->device;
|
||||
int ret;
|
||||
|
||||
ret = nv50_disp_chan_init(&mast->base);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* enable error reporting */
|
||||
nvkm_mask(device, 0x6100a0, 0x00000001, 0x00000001);
|
||||
|
||||
/* initialise channel for dma command submission */
|
||||
nvkm_wr32(device, 0x610494, mast->push);
|
||||
nvkm_wr32(device, 0x610498, 0x00010000);
|
||||
nvkm_wr32(device, 0x61049c, 0x00000001);
|
||||
nvkm_mask(device, 0x610490, 0x00000010, 0x00000010);
|
||||
nvkm_wr32(device, 0x640000, 0x00000000);
|
||||
nvkm_wr32(device, 0x610490, 0x01000013);
|
||||
|
||||
/* wait for it to go inactive */
|
||||
if (nvkm_msec(device, 2000,
|
||||
if (!(nvkm_rd32(device, 0x610490) & 0x80000000))
|
||||
break;
|
||||
) < 0) {
|
||||
nvkm_error(subdev, "core init: %08x\n",
|
||||
nvkm_rd32(device, 0x610490));
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct nv50_disp_chan_impl
|
||||
gf119_disp_core_ofuncs = {
|
||||
.base.ctor = nv50_disp_core_ctor,
|
||||
.base.dtor = nv50_disp_dmac_dtor,
|
||||
.base.init = gf119_disp_core_init,
|
||||
.base.fini = gf119_disp_core_fini,
|
||||
.base.ntfy = nv50_disp_chan_ntfy,
|
||||
.base.map = nv50_disp_chan_map,
|
||||
.base.rd32 = nv50_disp_chan_rd32,
|
||||
.base.wr32 = nv50_disp_chan_wr32,
|
||||
.chid = 0,
|
||||
.attach = gf119_disp_dmac_object_attach,
|
||||
.detach = gf119_disp_dmac_object_detach,
|
||||
};
|
|
@ -0,0 +1,117 @@
|
|||
/*
|
||||
* Copyright 2012 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "dmacnv50.h"
|
||||
|
||||
static const struct nv50_disp_mthd_list
|
||||
gk104_disp_core_mthd_head = {
|
||||
.mthd = 0x0300,
|
||||
.addr = 0x000300,
|
||||
.data = {
|
||||
{ 0x0400, 0x660400 },
|
||||
{ 0x0404, 0x660404 },
|
||||
{ 0x0408, 0x660408 },
|
||||
{ 0x040c, 0x66040c },
|
||||
{ 0x0410, 0x660410 },
|
||||
{ 0x0414, 0x660414 },
|
||||
{ 0x0418, 0x660418 },
|
||||
{ 0x041c, 0x66041c },
|
||||
{ 0x0420, 0x660420 },
|
||||
{ 0x0424, 0x660424 },
|
||||
{ 0x0428, 0x660428 },
|
||||
{ 0x042c, 0x66042c },
|
||||
{ 0x0430, 0x660430 },
|
||||
{ 0x0434, 0x660434 },
|
||||
{ 0x0438, 0x660438 },
|
||||
{ 0x0440, 0x660440 },
|
||||
{ 0x0444, 0x660444 },
|
||||
{ 0x0448, 0x660448 },
|
||||
{ 0x044c, 0x66044c },
|
||||
{ 0x0450, 0x660450 },
|
||||
{ 0x0454, 0x660454 },
|
||||
{ 0x0458, 0x660458 },
|
||||
{ 0x045c, 0x66045c },
|
||||
{ 0x0460, 0x660460 },
|
||||
{ 0x0468, 0x660468 },
|
||||
{ 0x046c, 0x66046c },
|
||||
{ 0x0470, 0x660470 },
|
||||
{ 0x0474, 0x660474 },
|
||||
{ 0x047c, 0x66047c },
|
||||
{ 0x0480, 0x660480 },
|
||||
{ 0x0484, 0x660484 },
|
||||
{ 0x0488, 0x660488 },
|
||||
{ 0x048c, 0x66048c },
|
||||
{ 0x0490, 0x660490 },
|
||||
{ 0x0494, 0x660494 },
|
||||
{ 0x0498, 0x660498 },
|
||||
{ 0x04a0, 0x6604a0 },
|
||||
{ 0x04b0, 0x6604b0 },
|
||||
{ 0x04b8, 0x6604b8 },
|
||||
{ 0x04bc, 0x6604bc },
|
||||
{ 0x04c0, 0x6604c0 },
|
||||
{ 0x04c4, 0x6604c4 },
|
||||
{ 0x04c8, 0x6604c8 },
|
||||
{ 0x04d0, 0x6604d0 },
|
||||
{ 0x04d4, 0x6604d4 },
|
||||
{ 0x04e0, 0x6604e0 },
|
||||
{ 0x04e4, 0x6604e4 },
|
||||
{ 0x04e8, 0x6604e8 },
|
||||
{ 0x04ec, 0x6604ec },
|
||||
{ 0x04f0, 0x6604f0 },
|
||||
{ 0x04f4, 0x6604f4 },
|
||||
{ 0x04f8, 0x6604f8 },
|
||||
{ 0x04fc, 0x6604fc },
|
||||
{ 0x0500, 0x660500 },
|
||||
{ 0x0504, 0x660504 },
|
||||
{ 0x0508, 0x660508 },
|
||||
{ 0x050c, 0x66050c },
|
||||
{ 0x0510, 0x660510 },
|
||||
{ 0x0514, 0x660514 },
|
||||
{ 0x0518, 0x660518 },
|
||||
{ 0x051c, 0x66051c },
|
||||
{ 0x0520, 0x660520 },
|
||||
{ 0x0524, 0x660524 },
|
||||
{ 0x052c, 0x66052c },
|
||||
{ 0x0530, 0x660530 },
|
||||
{ 0x054c, 0x66054c },
|
||||
{ 0x0550, 0x660550 },
|
||||
{ 0x0554, 0x660554 },
|
||||
{ 0x0558, 0x660558 },
|
||||
{ 0x055c, 0x66055c },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
const struct nv50_disp_mthd_chan
|
||||
gk104_disp_core_mthd_chan = {
|
||||
.name = "Core",
|
||||
.addr = 0x000000,
|
||||
.data = {
|
||||
{ "Global", 1, &gf119_disp_core_mthd_base },
|
||||
{ "DAC", 3, &gf119_disp_core_mthd_dac },
|
||||
{ "SOR", 8, &gf119_disp_core_mthd_sor },
|
||||
{ "PIOR", 4, &gf119_disp_core_mthd_pior },
|
||||
{ "HEAD", 4, &gk104_disp_core_mthd_head },
|
||||
{}
|
||||
}
|
||||
};
|
|
@ -0,0 +1,250 @@
|
|||
/*
|
||||
* Copyright 2012 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "dmacnv50.h"
|
||||
|
||||
#include <core/client.h>
|
||||
#include <subdev/timer.h>
|
||||
|
||||
#include <nvif/class.h>
|
||||
#include <nvif/unpack.h>
|
||||
|
||||
const struct nv50_disp_mthd_list
|
||||
nv50_disp_core_mthd_base = {
|
||||
.mthd = 0x0000,
|
||||
.addr = 0x000000,
|
||||
.data = {
|
||||
{ 0x0080, 0x000000 },
|
||||
{ 0x0084, 0x610bb8 },
|
||||
{ 0x0088, 0x610b9c },
|
||||
{ 0x008c, 0x000000 },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
static const struct nv50_disp_mthd_list
|
||||
nv50_disp_core_mthd_dac = {
|
||||
.mthd = 0x0080,
|
||||
.addr = 0x000008,
|
||||
.data = {
|
||||
{ 0x0400, 0x610b58 },
|
||||
{ 0x0404, 0x610bdc },
|
||||
{ 0x0420, 0x610828 },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
const struct nv50_disp_mthd_list
|
||||
nv50_disp_core_mthd_sor = {
|
||||
.mthd = 0x0040,
|
||||
.addr = 0x000008,
|
||||
.data = {
|
||||
{ 0x0600, 0x610b70 },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
const struct nv50_disp_mthd_list
|
||||
nv50_disp_core_mthd_pior = {
|
||||
.mthd = 0x0040,
|
||||
.addr = 0x000008,
|
||||
.data = {
|
||||
{ 0x0700, 0x610b80 },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
static const struct nv50_disp_mthd_list
|
||||
nv50_disp_core_mthd_head = {
|
||||
.mthd = 0x0400,
|
||||
.addr = 0x000540,
|
||||
.data = {
|
||||
{ 0x0800, 0x610ad8 },
|
||||
{ 0x0804, 0x610ad0 },
|
||||
{ 0x0808, 0x610a48 },
|
||||
{ 0x080c, 0x610a78 },
|
||||
{ 0x0810, 0x610ac0 },
|
||||
{ 0x0814, 0x610af8 },
|
||||
{ 0x0818, 0x610b00 },
|
||||
{ 0x081c, 0x610ae8 },
|
||||
{ 0x0820, 0x610af0 },
|
||||
{ 0x0824, 0x610b08 },
|
||||
{ 0x0828, 0x610b10 },
|
||||
{ 0x082c, 0x610a68 },
|
||||
{ 0x0830, 0x610a60 },
|
||||
{ 0x0834, 0x000000 },
|
||||
{ 0x0838, 0x610a40 },
|
||||
{ 0x0840, 0x610a24 },
|
||||
{ 0x0844, 0x610a2c },
|
||||
{ 0x0848, 0x610aa8 },
|
||||
{ 0x084c, 0x610ab0 },
|
||||
{ 0x0860, 0x610a84 },
|
||||
{ 0x0864, 0x610a90 },
|
||||
{ 0x0868, 0x610b18 },
|
||||
{ 0x086c, 0x610b20 },
|
||||
{ 0x0870, 0x610ac8 },
|
||||
{ 0x0874, 0x610a38 },
|
||||
{ 0x0880, 0x610a58 },
|
||||
{ 0x0884, 0x610a9c },
|
||||
{ 0x08a0, 0x610a70 },
|
||||
{ 0x08a4, 0x610a50 },
|
||||
{ 0x08a8, 0x610ae0 },
|
||||
{ 0x08c0, 0x610b28 },
|
||||
{ 0x08c4, 0x610b30 },
|
||||
{ 0x08c8, 0x610b40 },
|
||||
{ 0x08d4, 0x610b38 },
|
||||
{ 0x08d8, 0x610b48 },
|
||||
{ 0x08dc, 0x610b50 },
|
||||
{ 0x0900, 0x610a18 },
|
||||
{ 0x0904, 0x610ab8 },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
const struct nv50_disp_mthd_chan
|
||||
nv50_disp_core_mthd_chan = {
|
||||
.name = "Core",
|
||||
.addr = 0x000000,
|
||||
.data = {
|
||||
{ "Global", 1, &nv50_disp_core_mthd_base },
|
||||
{ "DAC", 3, &nv50_disp_core_mthd_dac },
|
||||
{ "SOR", 2, &nv50_disp_core_mthd_sor },
|
||||
{ "PIOR", 3, &nv50_disp_core_mthd_pior },
|
||||
{ "HEAD", 2, &nv50_disp_core_mthd_head },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
static int
|
||||
nv50_disp_core_fini(struct nvkm_object *object, bool suspend)
|
||||
{
|
||||
struct nv50_disp *disp = (void *)object->engine;
|
||||
struct nv50_disp_dmac *mast = (void *)object;
|
||||
struct nvkm_subdev *subdev = &disp->base.engine.subdev;
|
||||
struct nvkm_device *device = subdev->device;
|
||||
|
||||
/* deactivate channel */
|
||||
nvkm_mask(device, 0x610200, 0x00000010, 0x00000000);
|
||||
nvkm_mask(device, 0x610200, 0x00000003, 0x00000000);
|
||||
if (nvkm_msec(device, 2000,
|
||||
if (!(nvkm_rd32(device, 0x610200) & 0x001e0000))
|
||||
break;
|
||||
) < 0) {
|
||||
nvkm_error(subdev, "core fini: %08x\n",
|
||||
nvkm_rd32(device, 0x610200));
|
||||
if (suspend)
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
/* disable error reporting and completion notifications */
|
||||
nvkm_mask(device, 0x610028, 0x00010001, 0x00000000);
|
||||
|
||||
return nv50_disp_chan_fini(&mast->base, suspend);
|
||||
}
|
||||
|
||||
static int
|
||||
nv50_disp_core_init(struct nvkm_object *object)
|
||||
{
|
||||
struct nv50_disp *disp = (void *)object->engine;
|
||||
struct nv50_disp_dmac *mast = (void *)object;
|
||||
struct nvkm_subdev *subdev = &disp->base.engine.subdev;
|
||||
struct nvkm_device *device = subdev->device;
|
||||
int ret;
|
||||
|
||||
ret = nv50_disp_chan_init(&mast->base);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* enable error reporting */
|
||||
nvkm_mask(device, 0x610028, 0x00010000, 0x00010000);
|
||||
|
||||
/* attempt to unstick channel from some unknown state */
|
||||
if ((nvkm_rd32(device, 0x610200) & 0x009f0000) == 0x00020000)
|
||||
nvkm_mask(device, 0x610200, 0x00800000, 0x00800000);
|
||||
if ((nvkm_rd32(device, 0x610200) & 0x003f0000) == 0x00030000)
|
||||
nvkm_mask(device, 0x610200, 0x00600000, 0x00600000);
|
||||
|
||||
/* initialise channel for dma command submission */
|
||||
nvkm_wr32(device, 0x610204, mast->push);
|
||||
nvkm_wr32(device, 0x610208, 0x00010000);
|
||||
nvkm_wr32(device, 0x61020c, 0x00000000);
|
||||
nvkm_mask(device, 0x610200, 0x00000010, 0x00000010);
|
||||
nvkm_wr32(device, 0x640000, 0x00000000);
|
||||
nvkm_wr32(device, 0x610200, 0x01000013);
|
||||
|
||||
/* wait for it to go inactive */
|
||||
if (nvkm_msec(device, 2000,
|
||||
if (!(nvkm_rd32(device, 0x610200) & 0x80000000))
|
||||
break;
|
||||
) < 0) {
|
||||
nvkm_error(subdev, "core init: %08x\n",
|
||||
nvkm_rd32(device, 0x610200));
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
nv50_disp_core_ctor(struct nvkm_object *parent,
|
||||
struct nvkm_object *engine,
|
||||
struct nvkm_oclass *oclass, void *data, u32 size,
|
||||
struct nvkm_object **pobject)
|
||||
{
|
||||
union {
|
||||
struct nv50_disp_core_channel_dma_v0 v0;
|
||||
} *args = data;
|
||||
struct nv50_disp_dmac *mast;
|
||||
int ret;
|
||||
|
||||
nvif_ioctl(parent, "create disp core channel dma size %d\n", size);
|
||||
if (nvif_unpack(args->v0, 0, 0, false)) {
|
||||
nvif_ioctl(parent, "create disp core channel dma vers %d "
|
||||
"pushbuf %016llx\n",
|
||||
args->v0.version, args->v0.pushbuf);
|
||||
} else
|
||||
return ret;
|
||||
|
||||
ret = nv50_disp_dmac_create_(parent, engine, oclass, args->v0.pushbuf,
|
||||
0, sizeof(*mast), (void **)&mast);
|
||||
*pobject = nv_object(mast);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct nv50_disp_chan_impl
|
||||
nv50_disp_core_ofuncs = {
|
||||
.base.ctor = nv50_disp_core_ctor,
|
||||
.base.dtor = nv50_disp_dmac_dtor,
|
||||
.base.init = nv50_disp_core_init,
|
||||
.base.fini = nv50_disp_core_fini,
|
||||
.base.map = nv50_disp_chan_map,
|
||||
.base.ntfy = nv50_disp_chan_ntfy,
|
||||
.base.rd32 = nv50_disp_chan_rd32,
|
||||
.base.wr32 = nv50_disp_chan_wr32,
|
||||
.chid = 0,
|
||||
.attach = nv50_disp_dmac_object_attach,
|
||||
.detach = nv50_disp_dmac_object_detach,
|
||||
};
|
|
@ -0,0 +1,37 @@
|
|||
/*
|
||||
* Copyright 2012 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "channv50.h"
|
||||
|
||||
struct nv50_disp_chan_impl
|
||||
gf119_disp_curs_ofuncs = {
|
||||
.base.ctor = nv50_disp_curs_ctor,
|
||||
.base.dtor = nv50_disp_pioc_dtor,
|
||||
.base.init = gf119_disp_pioc_init,
|
||||
.base.fini = gf119_disp_pioc_fini,
|
||||
.base.ntfy = nv50_disp_chan_ntfy,
|
||||
.base.map = nv50_disp_chan_map,
|
||||
.base.rd32 = nv50_disp_chan_rd32,
|
||||
.base.wr32 = nv50_disp_chan_wr32,
|
||||
.chid = 13,
|
||||
};
|
|
@ -0,0 +1,73 @@
|
|||
/*
|
||||
* Copyright 2012 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "channv50.h"
|
||||
|
||||
#include <core/client.h>
|
||||
|
||||
#include <nvif/class.h>
|
||||
#include <nvif/unpack.h>
|
||||
|
||||
int
|
||||
nv50_disp_curs_ctor(struct nvkm_object *parent,
|
||||
struct nvkm_object *engine,
|
||||
struct nvkm_oclass *oclass, void *data, u32 size,
|
||||
struct nvkm_object **pobject)
|
||||
{
|
||||
union {
|
||||
struct nv50_disp_cursor_v0 v0;
|
||||
} *args = data;
|
||||
struct nv50_disp *disp = (void *)engine;
|
||||
struct nv50_disp_pioc *pioc;
|
||||
int ret;
|
||||
|
||||
nvif_ioctl(parent, "create disp cursor size %d\n", size);
|
||||
if (nvif_unpack(args->v0, 0, 0, false)) {
|
||||
nvif_ioctl(parent, "create disp cursor vers %d head %d\n",
|
||||
args->v0.version, args->v0.head);
|
||||
if (args->v0.head > disp->head.nr)
|
||||
return -EINVAL;
|
||||
} else
|
||||
return ret;
|
||||
|
||||
ret = nv50_disp_pioc_create_(parent, engine, oclass, args->v0.head,
|
||||
sizeof(*pioc), (void **)&pioc);
|
||||
*pobject = nv_object(pioc);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct nv50_disp_chan_impl
|
||||
nv50_disp_curs_ofuncs = {
|
||||
.base.ctor = nv50_disp_curs_ctor,
|
||||
.base.dtor = nv50_disp_pioc_dtor,
|
||||
.base.init = nv50_disp_pioc_init,
|
||||
.base.fini = nv50_disp_pioc_fini,
|
||||
.base.ntfy = nv50_disp_chan_ntfy,
|
||||
.base.map = nv50_disp_chan_map,
|
||||
.base.rd32 = nv50_disp_chan_rd32,
|
||||
.base.wr32 = nv50_disp_chan_wr32,
|
||||
.chid = 7,
|
||||
};
|
|
@ -0,0 +1,113 @@
|
|||
/*
|
||||
* Copyright 2012 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "dmacnv50.h"
|
||||
#include "rootnv50.h"
|
||||
|
||||
#include <core/ramht.h>
|
||||
#include <subdev/timer.h>
|
||||
|
||||
void
|
||||
gf119_disp_dmac_object_detach(struct nvkm_object *parent, int cookie)
|
||||
{
|
||||
struct nv50_disp_root *root = (void *)parent->parent;
|
||||
nvkm_ramht_remove(root->ramht, cookie);
|
||||
}
|
||||
|
||||
int
|
||||
gf119_disp_dmac_object_attach(struct nvkm_object *parent,
|
||||
struct nvkm_object *object, u32 name)
|
||||
{
|
||||
struct nv50_disp_root *root = (void *)parent->parent;
|
||||
struct nv50_disp_chan *chan = (void *)parent;
|
||||
u32 addr = nv_gpuobj(object)->node->offset;
|
||||
u32 data = (chan->chid << 27) | (addr << 9) | 0x00000001;
|
||||
return nvkm_ramht_insert(root->ramht, NULL, chan->chid, 0, name, data);
|
||||
}
|
||||
|
||||
int
|
||||
gf119_disp_dmac_fini(struct nvkm_object *object, bool suspend)
|
||||
{
|
||||
struct nv50_disp *disp = (void *)object->engine;
|
||||
struct nv50_disp_dmac *dmac = (void *)object;
|
||||
struct nvkm_subdev *subdev = &disp->base.engine.subdev;
|
||||
struct nvkm_device *device = subdev->device;
|
||||
int chid = dmac->base.chid;
|
||||
|
||||
/* deactivate channel */
|
||||
nvkm_mask(device, 0x610490 + (chid * 0x0010), 0x00001010, 0x00001000);
|
||||
nvkm_mask(device, 0x610490 + (chid * 0x0010), 0x00000003, 0x00000000);
|
||||
if (nvkm_msec(device, 2000,
|
||||
if (!(nvkm_rd32(device, 0x610490 + (chid * 0x10)) & 0x001e0000))
|
||||
break;
|
||||
) < 0) {
|
||||
nvkm_error(subdev, "ch %d fini: %08x\n", chid,
|
||||
nvkm_rd32(device, 0x610490 + (chid * 0x10)));
|
||||
if (suspend)
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
/* disable error reporting and completion notification */
|
||||
nvkm_mask(device, 0x610090, 0x00000001 << chid, 0x00000000);
|
||||
nvkm_mask(device, 0x6100a0, 0x00000001 << chid, 0x00000000);
|
||||
|
||||
return nv50_disp_chan_fini(&dmac->base, suspend);
|
||||
}
|
||||
|
||||
int
|
||||
gf119_disp_dmac_init(struct nvkm_object *object)
|
||||
{
|
||||
struct nv50_disp *disp = (void *)object->engine;
|
||||
struct nv50_disp_dmac *dmac = (void *)object;
|
||||
struct nvkm_subdev *subdev = &disp->base.engine.subdev;
|
||||
struct nvkm_device *device = subdev->device;
|
||||
int chid = dmac->base.chid;
|
||||
int ret;
|
||||
|
||||
ret = nv50_disp_chan_init(&dmac->base);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* enable error reporting */
|
||||
nvkm_mask(device, 0x6100a0, 0x00000001 << chid, 0x00000001 << chid);
|
||||
|
||||
/* initialise channel for dma command submission */
|
||||
nvkm_wr32(device, 0x610494 + (chid * 0x0010), dmac->push);
|
||||
nvkm_wr32(device, 0x610498 + (chid * 0x0010), 0x00010000);
|
||||
nvkm_wr32(device, 0x61049c + (chid * 0x0010), 0x00000001);
|
||||
nvkm_mask(device, 0x610490 + (chid * 0x0010), 0x00000010, 0x00000010);
|
||||
nvkm_wr32(device, 0x640000 + (chid * 0x1000), 0x00000000);
|
||||
nvkm_wr32(device, 0x610490 + (chid * 0x0010), 0x00000013);
|
||||
|
||||
/* wait for it to go inactive */
|
||||
if (nvkm_msec(device, 2000,
|
||||
if (!(nvkm_rd32(device, 0x610490 + (chid * 0x10)) & 0x80000000))
|
||||
break;
|
||||
) < 0) {
|
||||
nvkm_error(subdev, "ch %d init: %08x\n", chid,
|
||||
nvkm_rd32(device, 0x610490 + (chid * 0x10)));
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
|
@ -0,0 +1,163 @@
|
|||
/*
|
||||
* Copyright 2012 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "dmacnv50.h"
|
||||
#include "rootnv50.h"
|
||||
|
||||
#include <core/client.h>
|
||||
#include <core/handle.h>
|
||||
#include <core/ramht.h>
|
||||
#include <subdev/fb.h>
|
||||
#include <subdev/timer.h>
|
||||
#include <engine/dma.h>
|
||||
|
||||
void
|
||||
nv50_disp_dmac_object_detach(struct nvkm_object *parent, int cookie)
|
||||
{
|
||||
struct nv50_disp_root *root = (void *)parent->parent;
|
||||
nvkm_ramht_remove(root->ramht, cookie);
|
||||
}
|
||||
|
||||
int
|
||||
nv50_disp_dmac_object_attach(struct nvkm_object *parent,
|
||||
struct nvkm_object *object, u32 name)
|
||||
{
|
||||
struct nv50_disp_root *root = (void *)parent->parent;
|
||||
struct nv50_disp_chan *chan = (void *)parent;
|
||||
u32 addr = nv_gpuobj(object)->node->offset;
|
||||
u32 chid = chan->chid;
|
||||
u32 data = (chid << 28) | (addr << 10) | chid;
|
||||
return nvkm_ramht_insert(root->ramht, NULL, chid, 0, name, data);
|
||||
}
|
||||
|
||||
int
|
||||
nv50_disp_dmac_fini(struct nvkm_object *object, bool suspend)
|
||||
{
|
||||
struct nv50_disp *disp = (void *)object->engine;
|
||||
struct nv50_disp_dmac *dmac = (void *)object;
|
||||
struct nvkm_subdev *subdev = &disp->base.engine.subdev;
|
||||
struct nvkm_device *device = subdev->device;
|
||||
int chid = dmac->base.chid;
|
||||
|
||||
/* deactivate channel */
|
||||
nvkm_mask(device, 0x610200 + (chid * 0x0010), 0x00001010, 0x00001000);
|
||||
nvkm_mask(device, 0x610200 + (chid * 0x0010), 0x00000003, 0x00000000);
|
||||
if (nvkm_msec(device, 2000,
|
||||
if (!(nvkm_rd32(device, 0x610200 + (chid * 0x10)) & 0x001e0000))
|
||||
break;
|
||||
) < 0) {
|
||||
nvkm_error(subdev, "ch %d fini timeout, %08x\n", chid,
|
||||
nvkm_rd32(device, 0x610200 + (chid * 0x10)));
|
||||
if (suspend)
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
/* disable error reporting and completion notifications */
|
||||
nvkm_mask(device, 0x610028, 0x00010001 << chid, 0x00000000 << chid);
|
||||
|
||||
return nv50_disp_chan_fini(&dmac->base, suspend);
|
||||
}
|
||||
|
||||
int
|
||||
nv50_disp_dmac_init(struct nvkm_object *object)
|
||||
{
|
||||
struct nv50_disp *disp = (void *)object->engine;
|
||||
struct nv50_disp_dmac *dmac = (void *)object;
|
||||
struct nvkm_subdev *subdev = &disp->base.engine.subdev;
|
||||
struct nvkm_device *device = subdev->device;
|
||||
int chid = dmac->base.chid;
|
||||
int ret;
|
||||
|
||||
ret = nv50_disp_chan_init(&dmac->base);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* enable error reporting */
|
||||
nvkm_mask(device, 0x610028, 0x00010000 << chid, 0x00010000 << chid);
|
||||
|
||||
/* initialise channel for dma command submission */
|
||||
nvkm_wr32(device, 0x610204 + (chid * 0x0010), dmac->push);
|
||||
nvkm_wr32(device, 0x610208 + (chid * 0x0010), 0x00010000);
|
||||
nvkm_wr32(device, 0x61020c + (chid * 0x0010), chid);
|
||||
nvkm_mask(device, 0x610200 + (chid * 0x0010), 0x00000010, 0x00000010);
|
||||
nvkm_wr32(device, 0x640000 + (chid * 0x1000), 0x00000000);
|
||||
nvkm_wr32(device, 0x610200 + (chid * 0x0010), 0x00000013);
|
||||
|
||||
/* wait for it to go inactive */
|
||||
if (nvkm_msec(device, 2000,
|
||||
if (!(nvkm_rd32(device, 0x610200 + (chid * 0x10)) & 0x80000000))
|
||||
break;
|
||||
) < 0) {
|
||||
nvkm_error(subdev, "ch %d init timeout, %08x\n", chid,
|
||||
nvkm_rd32(device, 0x610200 + (chid * 0x10)));
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void
|
||||
nv50_disp_dmac_dtor(struct nvkm_object *object)
|
||||
{
|
||||
struct nv50_disp_dmac *dmac = (void *)object;
|
||||
nv50_disp_chan_destroy(&dmac->base);
|
||||
}
|
||||
|
||||
int
|
||||
nv50_disp_dmac_create_(struct nvkm_object *parent,
|
||||
struct nvkm_object *engine,
|
||||
struct nvkm_oclass *oclass, u64 pushbuf, int head,
|
||||
int length, void **pobject)
|
||||
{
|
||||
struct nvkm_device *device = parent->engine->subdev.device;
|
||||
struct nvkm_client *client = nvkm_client(parent);
|
||||
struct nvkm_dmaobj *dmaobj;
|
||||
struct nv50_disp_dmac *dmac;
|
||||
int ret;
|
||||
|
||||
ret = nv50_disp_chan_create_(parent, engine, oclass, head,
|
||||
length, pobject);
|
||||
dmac = *pobject;
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
dmaobj = nvkm_dma_search(device->dma, client, pushbuf);
|
||||
if (!dmaobj)
|
||||
return -ENOENT;
|
||||
|
||||
if (dmaobj->limit - dmaobj->start != 0xfff)
|
||||
return -EINVAL;
|
||||
|
||||
switch (dmaobj->target) {
|
||||
case NV_MEM_TARGET_VRAM:
|
||||
dmac->push = 0x00000001 | dmaobj->start >> 8;
|
||||
break;
|
||||
case NV_MEM_TARGET_PCI_NOSNOOP:
|
||||
dmac->push = 0x00000003 | dmaobj->start >> 8;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
|
@ -0,0 +1,24 @@
|
|||
#ifndef __NV50_DISP_DMAC_H__
|
||||
#define __NV50_DISP_DMAC_H__
|
||||
#include "channv50.h"
|
||||
|
||||
struct nv50_disp_dmac {
|
||||
struct nv50_disp_chan base;
|
||||
u32 push;
|
||||
};
|
||||
|
||||
void nv50_disp_dmac_dtor(struct nvkm_object *);
|
||||
int nv50_disp_dmac_object_attach(struct nvkm_object *,
|
||||
struct nvkm_object *, u32);
|
||||
void nv50_disp_dmac_object_detach(struct nvkm_object *, int);
|
||||
int nv50_disp_dmac_create_(struct nvkm_object *, struct nvkm_object *,
|
||||
struct nvkm_oclass *, u64, int, int, void **);
|
||||
int nv50_disp_dmac_init(struct nvkm_object *);
|
||||
int nv50_disp_dmac_fini(struct nvkm_object *, bool);
|
||||
|
||||
int gf119_disp_dmac_object_attach(struct nvkm_object *,
|
||||
struct nvkm_object *, u32);
|
||||
void gf119_disp_dmac_object_detach(struct nvkm_object *, int);
|
||||
int gf119_disp_dmac_init(struct nvkm_object *);
|
||||
int gf119_disp_dmac_fini(struct nvkm_object *, bool);
|
||||
#endif
|
|
@ -22,201 +22,7 @@
|
|||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "nv50.h"
|
||||
|
||||
#include <nvif/class.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* EVO master channel object
|
||||
******************************************************************************/
|
||||
|
||||
const struct nv50_disp_mthd_list
|
||||
g84_disp_core_mthd_dac = {
|
||||
.mthd = 0x0080,
|
||||
.addr = 0x000008,
|
||||
.data = {
|
||||
{ 0x0400, 0x610b58 },
|
||||
{ 0x0404, 0x610bdc },
|
||||
{ 0x0420, 0x610bc4 },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
const struct nv50_disp_mthd_list
|
||||
g84_disp_core_mthd_head = {
|
||||
.mthd = 0x0400,
|
||||
.addr = 0x000540,
|
||||
.data = {
|
||||
{ 0x0800, 0x610ad8 },
|
||||
{ 0x0804, 0x610ad0 },
|
||||
{ 0x0808, 0x610a48 },
|
||||
{ 0x080c, 0x610a78 },
|
||||
{ 0x0810, 0x610ac0 },
|
||||
{ 0x0814, 0x610af8 },
|
||||
{ 0x0818, 0x610b00 },
|
||||
{ 0x081c, 0x610ae8 },
|
||||
{ 0x0820, 0x610af0 },
|
||||
{ 0x0824, 0x610b08 },
|
||||
{ 0x0828, 0x610b10 },
|
||||
{ 0x082c, 0x610a68 },
|
||||
{ 0x0830, 0x610a60 },
|
||||
{ 0x0834, 0x000000 },
|
||||
{ 0x0838, 0x610a40 },
|
||||
{ 0x0840, 0x610a24 },
|
||||
{ 0x0844, 0x610a2c },
|
||||
{ 0x0848, 0x610aa8 },
|
||||
{ 0x084c, 0x610ab0 },
|
||||
{ 0x085c, 0x610c5c },
|
||||
{ 0x0860, 0x610a84 },
|
||||
{ 0x0864, 0x610a90 },
|
||||
{ 0x0868, 0x610b18 },
|
||||
{ 0x086c, 0x610b20 },
|
||||
{ 0x0870, 0x610ac8 },
|
||||
{ 0x0874, 0x610a38 },
|
||||
{ 0x0878, 0x610c50 },
|
||||
{ 0x0880, 0x610a58 },
|
||||
{ 0x0884, 0x610a9c },
|
||||
{ 0x089c, 0x610c68 },
|
||||
{ 0x08a0, 0x610a70 },
|
||||
{ 0x08a4, 0x610a50 },
|
||||
{ 0x08a8, 0x610ae0 },
|
||||
{ 0x08c0, 0x610b28 },
|
||||
{ 0x08c4, 0x610b30 },
|
||||
{ 0x08c8, 0x610b40 },
|
||||
{ 0x08d4, 0x610b38 },
|
||||
{ 0x08d8, 0x610b48 },
|
||||
{ 0x08dc, 0x610b50 },
|
||||
{ 0x0900, 0x610a18 },
|
||||
{ 0x0904, 0x610ab8 },
|
||||
{ 0x0910, 0x610c70 },
|
||||
{ 0x0914, 0x610c78 },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
const struct nv50_disp_mthd_chan
|
||||
g84_disp_core_mthd_chan = {
|
||||
.name = "Core",
|
||||
.addr = 0x000000,
|
||||
.data = {
|
||||
{ "Global", 1, &nv50_disp_core_mthd_base },
|
||||
{ "DAC", 3, &g84_disp_core_mthd_dac },
|
||||
{ "SOR", 2, &nv50_disp_core_mthd_sor },
|
||||
{ "PIOR", 3, &nv50_disp_core_mthd_pior },
|
||||
{ "HEAD", 2, &g84_disp_core_mthd_head },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* EVO sync channel objects
|
||||
******************************************************************************/
|
||||
|
||||
static const struct nv50_disp_mthd_list
|
||||
g84_disp_base_mthd_base = {
|
||||
.mthd = 0x0000,
|
||||
.addr = 0x000000,
|
||||
.data = {
|
||||
{ 0x0080, 0x000000 },
|
||||
{ 0x0084, 0x0008c4 },
|
||||
{ 0x0088, 0x0008d0 },
|
||||
{ 0x008c, 0x0008dc },
|
||||
{ 0x0090, 0x0008e4 },
|
||||
{ 0x0094, 0x610884 },
|
||||
{ 0x00a0, 0x6108a0 },
|
||||
{ 0x00a4, 0x610878 },
|
||||
{ 0x00c0, 0x61086c },
|
||||
{ 0x00c4, 0x610800 },
|
||||
{ 0x00c8, 0x61080c },
|
||||
{ 0x00cc, 0x610818 },
|
||||
{ 0x00e0, 0x610858 },
|
||||
{ 0x00e4, 0x610860 },
|
||||
{ 0x00e8, 0x6108ac },
|
||||
{ 0x00ec, 0x6108b4 },
|
||||
{ 0x00fc, 0x610824 },
|
||||
{ 0x0100, 0x610894 },
|
||||
{ 0x0104, 0x61082c },
|
||||
{ 0x0110, 0x6108bc },
|
||||
{ 0x0114, 0x61088c },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
const struct nv50_disp_mthd_chan
|
||||
g84_disp_base_mthd_chan = {
|
||||
.name = "Base",
|
||||
.addr = 0x000540,
|
||||
.data = {
|
||||
{ "Global", 1, &g84_disp_base_mthd_base },
|
||||
{ "Image", 2, &nv50_disp_base_mthd_image },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* EVO overlay channel objects
|
||||
******************************************************************************/
|
||||
|
||||
static const struct nv50_disp_mthd_list
|
||||
g84_disp_ovly_mthd_base = {
|
||||
.mthd = 0x0000,
|
||||
.addr = 0x000000,
|
||||
.data = {
|
||||
{ 0x0080, 0x000000 },
|
||||
{ 0x0084, 0x6109a0 },
|
||||
{ 0x0088, 0x6109c0 },
|
||||
{ 0x008c, 0x6109c8 },
|
||||
{ 0x0090, 0x6109b4 },
|
||||
{ 0x0094, 0x610970 },
|
||||
{ 0x00a0, 0x610998 },
|
||||
{ 0x00a4, 0x610964 },
|
||||
{ 0x00c0, 0x610958 },
|
||||
{ 0x00e0, 0x6109a8 },
|
||||
{ 0x00e4, 0x6109d0 },
|
||||
{ 0x00e8, 0x6109d8 },
|
||||
{ 0x0100, 0x61094c },
|
||||
{ 0x0104, 0x610984 },
|
||||
{ 0x0108, 0x61098c },
|
||||
{ 0x0800, 0x6109f8 },
|
||||
{ 0x0808, 0x610a08 },
|
||||
{ 0x080c, 0x610a10 },
|
||||
{ 0x0810, 0x610a00 },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
const struct nv50_disp_mthd_chan
|
||||
g84_disp_ovly_mthd_chan = {
|
||||
.name = "Overlay",
|
||||
.addr = 0x000540,
|
||||
.data = {
|
||||
{ "Global", 1, &g84_disp_ovly_mthd_base },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Base display object
|
||||
******************************************************************************/
|
||||
|
||||
static struct nvkm_oclass
|
||||
g84_disp_sclass[] = {
|
||||
{ G82_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
|
||||
{ G82_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
|
||||
{ G82_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
|
||||
{ G82_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
|
||||
{ G82_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct nvkm_oclass
|
||||
g84_disp_main_oclass[] = {
|
||||
{ G82_DISP, &nv50_disp_main_ofuncs },
|
||||
{}
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Display engine implementation
|
||||
******************************************************************************/
|
||||
#include "rootnv50.h"
|
||||
|
||||
static int
|
||||
g84_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
||||
|
@ -236,7 +42,7 @@ g84_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
nv_engine(disp)->sclass = g84_disp_main_oclass;
|
||||
nv_engine(disp)->sclass = g84_disp_root_oclass;
|
||||
nv_engine(disp)->cclass = &nv50_disp_cclass;
|
||||
nv_subdev(disp)->intr = nv50_disp_intr;
|
||||
INIT_WORK(&disp->supervisor, nv50_disp_intr_supervisor);
|
||||
|
@ -272,5 +78,5 @@ g84_disp_oclass = &(struct nv50_disp_impl) {
|
|||
.mthd.base = &g84_disp_base_mthd_chan,
|
||||
.mthd.ovly = &g84_disp_ovly_mthd_chan,
|
||||
.mthd.prev = 0x000004,
|
||||
.head.scanoutpos = nv50_disp_main_scanoutpos,
|
||||
.head.scanoutpos = nv50_disp_root_scanoutpos,
|
||||
}.base.base;
|
||||
|
|
|
@ -22,61 +22,7 @@
|
|||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "nv50.h"
|
||||
#include "outpdp.h"
|
||||
|
||||
#include <nvif/class.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* EVO master channel object
|
||||
******************************************************************************/
|
||||
|
||||
const struct nv50_disp_mthd_list
|
||||
g94_disp_core_mthd_sor = {
|
||||
.mthd = 0x0040,
|
||||
.addr = 0x000008,
|
||||
.data = {
|
||||
{ 0x0600, 0x610794 },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
const struct nv50_disp_mthd_chan
|
||||
g94_disp_core_mthd_chan = {
|
||||
.name = "Core",
|
||||
.addr = 0x000000,
|
||||
.data = {
|
||||
{ "Global", 1, &nv50_disp_core_mthd_base },
|
||||
{ "DAC", 3, &g84_disp_core_mthd_dac },
|
||||
{ "SOR", 4, &g94_disp_core_mthd_sor },
|
||||
{ "PIOR", 3, &nv50_disp_core_mthd_pior },
|
||||
{ "HEAD", 2, &g84_disp_core_mthd_head },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Base display object
|
||||
******************************************************************************/
|
||||
|
||||
static struct nvkm_oclass
|
||||
g94_disp_sclass[] = {
|
||||
{ GT206_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
|
||||
{ GT200_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
|
||||
{ GT200_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
|
||||
{ G82_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
|
||||
{ G82_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct nvkm_oclass
|
||||
g94_disp_main_oclass[] = {
|
||||
{ GT206_DISP, &nv50_disp_main_ofuncs },
|
||||
{}
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Display engine implementation
|
||||
******************************************************************************/
|
||||
#include "rootnv50.h"
|
||||
|
||||
static int
|
||||
g94_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
||||
|
@ -96,7 +42,7 @@ g94_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
nv_engine(disp)->sclass = g94_disp_main_oclass;
|
||||
nv_engine(disp)->sclass = g94_disp_root_oclass;
|
||||
nv_engine(disp)->cclass = &nv50_disp_cclass;
|
||||
nv_subdev(disp)->intr = nv50_disp_intr;
|
||||
INIT_WORK(&disp->supervisor, nv50_disp_intr_supervisor);
|
||||
|
@ -133,5 +79,5 @@ g94_disp_oclass = &(struct nv50_disp_impl) {
|
|||
.mthd.base = &g84_disp_base_mthd_chan,
|
||||
.mthd.ovly = &g84_disp_ovly_mthd_chan,
|
||||
.mthd.prev = 0x000004,
|
||||
.head.scanoutpos = nv50_disp_main_scanoutpos,
|
||||
.head.scanoutpos = nv50_disp_root_scanoutpos,
|
||||
}.base.base;
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,586 @@
|
|||
/*
|
||||
* Copyright 2012 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "nv50.h"
|
||||
#include "rootnv50.h"
|
||||
|
||||
#include <subdev/bios.h>
|
||||
#include <subdev/bios/disp.h>
|
||||
#include <subdev/bios/init.h>
|
||||
#include <subdev/bios/pll.h>
|
||||
#include <subdev/devinit.h>
|
||||
|
||||
static void
|
||||
gf119_disp_vblank_init(struct nvkm_event *event, int type, int head)
|
||||
{
|
||||
struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank);
|
||||
struct nvkm_device *device = disp->engine.subdev.device;
|
||||
nvkm_mask(device, 0x6100c0 + (head * 0x800), 0x00000001, 0x00000001);
|
||||
}
|
||||
|
||||
static void
|
||||
gf119_disp_vblank_fini(struct nvkm_event *event, int type, int head)
|
||||
{
|
||||
struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank);
|
||||
struct nvkm_device *device = disp->engine.subdev.device;
|
||||
nvkm_mask(device, 0x6100c0 + (head * 0x800), 0x00000001, 0x00000000);
|
||||
}
|
||||
|
||||
const struct nvkm_event_func
|
||||
gf119_disp_vblank_func = {
|
||||
.ctor = nvkm_disp_vblank_ctor,
|
||||
.init = gf119_disp_vblank_init,
|
||||
.fini = gf119_disp_vblank_fini,
|
||||
};
|
||||
|
||||
static struct nvkm_output *
|
||||
exec_lookup(struct nv50_disp *disp, int head, int or, u32 ctrl,
|
||||
u32 *data, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
|
||||
struct nvbios_outp *info)
|
||||
{
|
||||
struct nvkm_subdev *subdev = &disp->base.engine.subdev;
|
||||
struct nvkm_bios *bios = subdev->device->bios;
|
||||
struct nvkm_output *outp;
|
||||
u16 mask, type;
|
||||
|
||||
if (or < 4) {
|
||||
type = DCB_OUTPUT_ANALOG;
|
||||
mask = 0;
|
||||
} else {
|
||||
or -= 4;
|
||||
switch (ctrl & 0x00000f00) {
|
||||
case 0x00000000: type = DCB_OUTPUT_LVDS; mask = 1; break;
|
||||
case 0x00000100: type = DCB_OUTPUT_TMDS; mask = 1; break;
|
||||
case 0x00000200: type = DCB_OUTPUT_TMDS; mask = 2; break;
|
||||
case 0x00000500: type = DCB_OUTPUT_TMDS; mask = 3; break;
|
||||
case 0x00000800: type = DCB_OUTPUT_DP; mask = 1; break;
|
||||
case 0x00000900: type = DCB_OUTPUT_DP; mask = 2; break;
|
||||
default:
|
||||
nvkm_error(subdev, "unknown SOR mc %08x\n", ctrl);
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
|
||||
mask = 0x00c0 & (mask << 6);
|
||||
mask |= 0x0001 << or;
|
||||
mask |= 0x0100 << head;
|
||||
|
||||
list_for_each_entry(outp, &disp->base.outp, head) {
|
||||
if ((outp->info.hasht & 0xff) == type &&
|
||||
(outp->info.hashm & mask) == mask) {
|
||||
*data = nvbios_outp_match(bios, outp->info.hasht,
|
||||
outp->info.hashm,
|
||||
ver, hdr, cnt, len, info);
|
||||
if (!*data)
|
||||
return NULL;
|
||||
return outp;
|
||||
}
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static struct nvkm_output *
|
||||
exec_script(struct nv50_disp *disp, int head, int id)
|
||||
{
|
||||
struct nvkm_device *device = disp->base.engine.subdev.device;
|
||||
struct nvkm_bios *bios = device->bios;
|
||||
struct nvkm_output *outp;
|
||||
struct nvbios_outp info;
|
||||
u8 ver, hdr, cnt, len;
|
||||
u32 data, ctrl = 0;
|
||||
int or;
|
||||
|
||||
for (or = 0; !(ctrl & (1 << head)) && or < 8; or++) {
|
||||
ctrl = nvkm_rd32(device, 0x640180 + (or * 0x20));
|
||||
if (ctrl & (1 << head))
|
||||
break;
|
||||
}
|
||||
|
||||
if (or == 8)
|
||||
return NULL;
|
||||
|
||||
outp = exec_lookup(disp, head, or, ctrl, &data, &ver, &hdr, &cnt, &len, &info);
|
||||
if (outp) {
|
||||
struct nvbios_init init = {
|
||||
.subdev = nv_subdev(disp),
|
||||
.bios = bios,
|
||||
.offset = info.script[id],
|
||||
.outp = &outp->info,
|
||||
.crtc = head,
|
||||
.execute = 1,
|
||||
};
|
||||
|
||||
nvbios_exec(&init);
|
||||
}
|
||||
|
||||
return outp;
|
||||
}
|
||||
|
||||
static struct nvkm_output *
|
||||
exec_clkcmp(struct nv50_disp *disp, int head, int id, u32 pclk, u32 *conf)
|
||||
{
|
||||
struct nvkm_device *device = disp->base.engine.subdev.device;
|
||||
struct nvkm_bios *bios = device->bios;
|
||||
struct nvkm_output *outp;
|
||||
struct nvbios_outp info1;
|
||||
struct nvbios_ocfg info2;
|
||||
u8 ver, hdr, cnt, len;
|
||||
u32 data, ctrl = 0;
|
||||
int or;
|
||||
|
||||
for (or = 0; !(ctrl & (1 << head)) && or < 8; or++) {
|
||||
ctrl = nvkm_rd32(device, 0x660180 + (or * 0x20));
|
||||
if (ctrl & (1 << head))
|
||||
break;
|
||||
}
|
||||
|
||||
if (or == 8)
|
||||
return NULL;
|
||||
|
||||
outp = exec_lookup(disp, head, or, ctrl, &data, &ver, &hdr, &cnt, &len, &info1);
|
||||
if (!outp)
|
||||
return NULL;
|
||||
|
||||
switch (outp->info.type) {
|
||||
case DCB_OUTPUT_TMDS:
|
||||
*conf = (ctrl & 0x00000f00) >> 8;
|
||||
if (pclk >= 165000)
|
||||
*conf |= 0x0100;
|
||||
break;
|
||||
case DCB_OUTPUT_LVDS:
|
||||
*conf = disp->sor.lvdsconf;
|
||||
break;
|
||||
case DCB_OUTPUT_DP:
|
||||
*conf = (ctrl & 0x00000f00) >> 8;
|
||||
break;
|
||||
case DCB_OUTPUT_ANALOG:
|
||||
default:
|
||||
*conf = 0x00ff;
|
||||
break;
|
||||
}
|
||||
|
||||
data = nvbios_ocfg_match(bios, data, *conf, &ver, &hdr, &cnt, &len, &info2);
|
||||
if (data && id < 0xff) {
|
||||
data = nvbios_oclk_match(bios, info2.clkcmp[id], pclk);
|
||||
if (data) {
|
||||
struct nvbios_init init = {
|
||||
.subdev = nv_subdev(disp),
|
||||
.bios = bios,
|
||||
.offset = data,
|
||||
.outp = &outp->info,
|
||||
.crtc = head,
|
||||
.execute = 1,
|
||||
};
|
||||
|
||||
nvbios_exec(&init);
|
||||
}
|
||||
}
|
||||
|
||||
return outp;
|
||||
}
|
||||
|
||||
static void
|
||||
gf119_disp_intr_unk1_0(struct nv50_disp *disp, int head)
|
||||
{
|
||||
exec_script(disp, head, 1);
|
||||
}
|
||||
|
||||
static void
|
||||
gf119_disp_intr_unk2_0(struct nv50_disp *disp, int head)
|
||||
{
|
||||
struct nvkm_output *outp = exec_script(disp, head, 2);
|
||||
|
||||
/* see note in nv50_disp_intr_unk20_0() */
|
||||
if (outp && outp->info.type == DCB_OUTPUT_DP) {
|
||||
struct nvkm_output_dp *outpdp = nvkm_output_dp(outp);
|
||||
struct nvbios_init init = {
|
||||
.subdev = nv_subdev(disp),
|
||||
.bios = nvkm_bios(disp),
|
||||
.outp = &outp->info,
|
||||
.crtc = head,
|
||||
.offset = outpdp->info.script[4],
|
||||
.execute = 1,
|
||||
};
|
||||
|
||||
nvbios_exec(&init);
|
||||
atomic_set(&outpdp->lt.done, 0);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
gf119_disp_intr_unk2_1(struct nv50_disp *disp, int head)
|
||||
{
|
||||
struct nvkm_device *device = disp->base.engine.subdev.device;
|
||||
struct nvkm_devinit *devinit = device->devinit;
|
||||
u32 pclk = nvkm_rd32(device, 0x660450 + (head * 0x300)) / 1000;
|
||||
if (pclk)
|
||||
devinit->pll_set(devinit, PLL_VPLL0 + head, pclk);
|
||||
nvkm_wr32(device, 0x612200 + (head * 0x800), 0x00000000);
|
||||
}
|
||||
|
||||
static void
|
||||
gf119_disp_intr_unk2_2_tu(struct nv50_disp *disp, int head,
|
||||
struct dcb_output *outp)
|
||||
{
|
||||
struct nvkm_device *device = disp->base.engine.subdev.device;
|
||||
const int or = ffs(outp->or) - 1;
|
||||
const u32 ctrl = nvkm_rd32(device, 0x660200 + (or * 0x020));
|
||||
const u32 conf = nvkm_rd32(device, 0x660404 + (head * 0x300));
|
||||
const s32 vactive = nvkm_rd32(device, 0x660414 + (head * 0x300)) & 0xffff;
|
||||
const s32 vblanke = nvkm_rd32(device, 0x66041c + (head * 0x300)) & 0xffff;
|
||||
const s32 vblanks = nvkm_rd32(device, 0x660420 + (head * 0x300)) & 0xffff;
|
||||
const u32 pclk = nvkm_rd32(device, 0x660450 + (head * 0x300)) / 1000;
|
||||
const u32 link = ((ctrl & 0xf00) == 0x800) ? 0 : 1;
|
||||
const u32 hoff = (head * 0x800);
|
||||
const u32 soff = ( or * 0x800);
|
||||
const u32 loff = (link * 0x080) + soff;
|
||||
const u32 symbol = 100000;
|
||||
const u32 TU = 64;
|
||||
u32 dpctrl = nvkm_rd32(device, 0x61c10c + loff);
|
||||
u32 clksor = nvkm_rd32(device, 0x612300 + soff);
|
||||
u32 datarate, link_nr, link_bw, bits;
|
||||
u64 ratio, value;
|
||||
|
||||
link_nr = hweight32(dpctrl & 0x000f0000);
|
||||
link_bw = (clksor & 0x007c0000) >> 18;
|
||||
link_bw *= 27000;
|
||||
|
||||
/* symbols/hblank - algorithm taken from comments in tegra driver */
|
||||
value = vblanke + vactive - vblanks - 7;
|
||||
value = value * link_bw;
|
||||
do_div(value, pclk);
|
||||
value = value - (3 * !!(dpctrl & 0x00004000)) - (12 / link_nr);
|
||||
nvkm_mask(device, 0x616620 + hoff, 0x0000ffff, value);
|
||||
|
||||
/* symbols/vblank - algorithm taken from comments in tegra driver */
|
||||
value = vblanks - vblanke - 25;
|
||||
value = value * link_bw;
|
||||
do_div(value, pclk);
|
||||
value = value - ((36 / link_nr) + 3) - 1;
|
||||
nvkm_mask(device, 0x616624 + hoff, 0x00ffffff, value);
|
||||
|
||||
/* watermark */
|
||||
if ((conf & 0x3c0) == 0x180) bits = 30;
|
||||
else if ((conf & 0x3c0) == 0x140) bits = 24;
|
||||
else bits = 18;
|
||||
datarate = (pclk * bits) / 8;
|
||||
|
||||
ratio = datarate;
|
||||
ratio *= symbol;
|
||||
do_div(ratio, link_nr * link_bw);
|
||||
|
||||
value = (symbol - ratio) * TU;
|
||||
value *= ratio;
|
||||
do_div(value, symbol);
|
||||
do_div(value, symbol);
|
||||
|
||||
value += 5;
|
||||
value |= 0x08000000;
|
||||
|
||||
nvkm_wr32(device, 0x616610 + hoff, value);
|
||||
}
|
||||
|
||||
static void
|
||||
gf119_disp_intr_unk2_2(struct nv50_disp *disp, int head)
|
||||
{
|
||||
struct nvkm_device *device = disp->base.engine.subdev.device;
|
||||
struct nvkm_output *outp;
|
||||
u32 pclk = nvkm_rd32(device, 0x660450 + (head * 0x300)) / 1000;
|
||||
u32 conf, addr, data;
|
||||
|
||||
outp = exec_clkcmp(disp, head, 0xff, pclk, &conf);
|
||||
if (!outp)
|
||||
return;
|
||||
|
||||
/* see note in nv50_disp_intr_unk20_2() */
|
||||
if (outp->info.type == DCB_OUTPUT_DP) {
|
||||
u32 sync = nvkm_rd32(device, 0x660404 + (head * 0x300));
|
||||
switch ((sync & 0x000003c0) >> 6) {
|
||||
case 6: pclk = pclk * 30; break;
|
||||
case 5: pclk = pclk * 24; break;
|
||||
case 2:
|
||||
default:
|
||||
pclk = pclk * 18;
|
||||
break;
|
||||
}
|
||||
|
||||
if (nvkm_output_dp_train(outp, pclk, true))
|
||||
OUTP_ERR(outp, "link not trained before attach");
|
||||
} else {
|
||||
if (disp->sor.magic)
|
||||
disp->sor.magic(outp);
|
||||
}
|
||||
|
||||
exec_clkcmp(disp, head, 0, pclk, &conf);
|
||||
|
||||
if (outp->info.type == DCB_OUTPUT_ANALOG) {
|
||||
addr = 0x612280 + (ffs(outp->info.or) - 1) * 0x800;
|
||||
data = 0x00000000;
|
||||
} else {
|
||||
addr = 0x612300 + (ffs(outp->info.or) - 1) * 0x800;
|
||||
data = (conf & 0x0100) ? 0x00000101 : 0x00000000;
|
||||
switch (outp->info.type) {
|
||||
case DCB_OUTPUT_TMDS:
|
||||
nvkm_mask(device, addr, 0x007c0000, 0x00280000);
|
||||
break;
|
||||
case DCB_OUTPUT_DP:
|
||||
gf119_disp_intr_unk2_2_tu(disp, head, &outp->info);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
nvkm_mask(device, addr, 0x00000707, data);
|
||||
}
|
||||
|
||||
static void
|
||||
gf119_disp_intr_unk4_0(struct nv50_disp *disp, int head)
|
||||
{
|
||||
struct nvkm_device *device = disp->base.engine.subdev.device;
|
||||
u32 pclk = nvkm_rd32(device, 0x660450 + (head * 0x300)) / 1000;
|
||||
u32 conf;
|
||||
|
||||
exec_clkcmp(disp, head, 1, pclk, &conf);
|
||||
}
|
||||
|
||||
void
|
||||
gf119_disp_intr_supervisor(struct work_struct *work)
|
||||
{
|
||||
struct nv50_disp *disp =
|
||||
container_of(work, struct nv50_disp, supervisor);
|
||||
struct nv50_disp_impl *impl = (void *)nv_object(disp)->oclass;
|
||||
struct nvkm_subdev *subdev = &disp->base.engine.subdev;
|
||||
struct nvkm_device *device = subdev->device;
|
||||
u32 mask[4];
|
||||
int head;
|
||||
|
||||
nvkm_debug(subdev, "supervisor %d\n", ffs(disp->super));
|
||||
for (head = 0; head < disp->head.nr; head++) {
|
||||
mask[head] = nvkm_rd32(device, 0x6101d4 + (head * 0x800));
|
||||
nvkm_debug(subdev, "head %d: %08x\n", head, mask[head]);
|
||||
}
|
||||
|
||||
if (disp->super & 0x00000001) {
|
||||
nv50_disp_mthd_chan(disp, NV_DBG_DEBUG, 0, impl->mthd.core);
|
||||
for (head = 0; head < disp->head.nr; head++) {
|
||||
if (!(mask[head] & 0x00001000))
|
||||
continue;
|
||||
nvkm_debug(subdev, "supervisor 1.0 - head %d\n", head);
|
||||
gf119_disp_intr_unk1_0(disp, head);
|
||||
}
|
||||
} else
|
||||
if (disp->super & 0x00000002) {
|
||||
for (head = 0; head < disp->head.nr; head++) {
|
||||
if (!(mask[head] & 0x00001000))
|
||||
continue;
|
||||
nvkm_debug(subdev, "supervisor 2.0 - head %d\n", head);
|
||||
gf119_disp_intr_unk2_0(disp, head);
|
||||
}
|
||||
for (head = 0; head < disp->head.nr; head++) {
|
||||
if (!(mask[head] & 0x00010000))
|
||||
continue;
|
||||
nvkm_debug(subdev, "supervisor 2.1 - head %d\n", head);
|
||||
gf119_disp_intr_unk2_1(disp, head);
|
||||
}
|
||||
for (head = 0; head < disp->head.nr; head++) {
|
||||
if (!(mask[head] & 0x00001000))
|
||||
continue;
|
||||
nvkm_debug(subdev, "supervisor 2.2 - head %d\n", head);
|
||||
gf119_disp_intr_unk2_2(disp, head);
|
||||
}
|
||||
} else
|
||||
if (disp->super & 0x00000004) {
|
||||
for (head = 0; head < disp->head.nr; head++) {
|
||||
if (!(mask[head] & 0x00001000))
|
||||
continue;
|
||||
nvkm_debug(subdev, "supervisor 3.0 - head %d\n", head);
|
||||
gf119_disp_intr_unk4_0(disp, head);
|
||||
}
|
||||
}
|
||||
|
||||
for (head = 0; head < disp->head.nr; head++)
|
||||
nvkm_wr32(device, 0x6101d4 + (head * 0x800), 0x00000000);
|
||||
nvkm_wr32(device, 0x6101d0, 0x80000000);
|
||||
}
|
||||
|
||||
static void
|
||||
gf119_disp_intr_error(struct nv50_disp *disp, int chid)
|
||||
{
|
||||
const struct nv50_disp_impl *impl = (void *)nv_object(disp)->oclass;
|
||||
struct nvkm_subdev *subdev = &disp->base.engine.subdev;
|
||||
struct nvkm_device *device = subdev->device;
|
||||
u32 mthd = nvkm_rd32(device, 0x6101f0 + (chid * 12));
|
||||
u32 data = nvkm_rd32(device, 0x6101f4 + (chid * 12));
|
||||
u32 unkn = nvkm_rd32(device, 0x6101f8 + (chid * 12));
|
||||
|
||||
nvkm_error(subdev, "chid %d mthd %04x data %08x %08x %08x\n",
|
||||
chid, (mthd & 0x0000ffc), data, mthd, unkn);
|
||||
|
||||
if (chid == 0) {
|
||||
switch (mthd & 0xffc) {
|
||||
case 0x0080:
|
||||
nv50_disp_mthd_chan(disp, NV_DBG_ERROR, chid - 0,
|
||||
impl->mthd.core);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
} else
|
||||
if (chid <= 4) {
|
||||
switch (mthd & 0xffc) {
|
||||
case 0x0080:
|
||||
nv50_disp_mthd_chan(disp, NV_DBG_ERROR, chid - 1,
|
||||
impl->mthd.base);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
} else
|
||||
if (chid <= 8) {
|
||||
switch (mthd & 0xffc) {
|
||||
case 0x0080:
|
||||
nv50_disp_mthd_chan(disp, NV_DBG_ERROR, chid - 5,
|
||||
impl->mthd.ovly);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
nvkm_wr32(device, 0x61009c, (1 << chid));
|
||||
nvkm_wr32(device, 0x6101f0 + (chid * 12), 0x90000000);
|
||||
}
|
||||
|
||||
void
|
||||
gf119_disp_intr(struct nvkm_subdev *subdev)
|
||||
{
|
||||
struct nv50_disp *disp = (void *)subdev;
|
||||
struct nvkm_device *device = subdev->device;
|
||||
u32 intr = nvkm_rd32(device, 0x610088);
|
||||
int i;
|
||||
|
||||
if (intr & 0x00000001) {
|
||||
u32 stat = nvkm_rd32(device, 0x61008c);
|
||||
while (stat) {
|
||||
int chid = __ffs(stat); stat &= ~(1 << chid);
|
||||
nv50_disp_chan_uevent_send(disp, chid);
|
||||
nvkm_wr32(device, 0x61008c, 1 << chid);
|
||||
}
|
||||
intr &= ~0x00000001;
|
||||
}
|
||||
|
||||
if (intr & 0x00000002) {
|
||||
u32 stat = nvkm_rd32(device, 0x61009c);
|
||||
int chid = ffs(stat) - 1;
|
||||
if (chid >= 0)
|
||||
gf119_disp_intr_error(disp, chid);
|
||||
intr &= ~0x00000002;
|
||||
}
|
||||
|
||||
if (intr & 0x00100000) {
|
||||
u32 stat = nvkm_rd32(device, 0x6100ac);
|
||||
if (stat & 0x00000007) {
|
||||
disp->super = (stat & 0x00000007);
|
||||
schedule_work(&disp->supervisor);
|
||||
nvkm_wr32(device, 0x6100ac, disp->super);
|
||||
stat &= ~0x00000007;
|
||||
}
|
||||
|
||||
if (stat) {
|
||||
nvkm_warn(subdev, "intr24 %08x\n", stat);
|
||||
nvkm_wr32(device, 0x6100ac, stat);
|
||||
}
|
||||
|
||||
intr &= ~0x00100000;
|
||||
}
|
||||
|
||||
for (i = 0; i < disp->head.nr; i++) {
|
||||
u32 mask = 0x01000000 << i;
|
||||
if (mask & intr) {
|
||||
u32 stat = nvkm_rd32(device, 0x6100bc + (i * 0x800));
|
||||
if (stat & 0x00000001)
|
||||
nvkm_disp_vblank(&disp->base, i);
|
||||
nvkm_mask(device, 0x6100bc + (i * 0x800), 0, 0);
|
||||
nvkm_rd32(device, 0x6100c0 + (i * 0x800));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
gf119_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
||||
struct nvkm_oclass *oclass, void *data, u32 size,
|
||||
struct nvkm_object **pobject)
|
||||
{
|
||||
struct nvkm_device *device = (void *)parent;
|
||||
struct nv50_disp *disp;
|
||||
int heads = nvkm_rd32(device, 0x022448);
|
||||
int ret;
|
||||
|
||||
ret = nvkm_disp_create(parent, engine, oclass, heads,
|
||||
"PDISP", "display", &disp);
|
||||
*pobject = nv_object(disp);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = nvkm_event_init(&gf119_disp_chan_uevent, 1, 17, &disp->uevent);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
nv_engine(disp)->sclass = gf119_disp_root_oclass;
|
||||
nv_engine(disp)->cclass = &nv50_disp_cclass;
|
||||
nv_subdev(disp)->intr = gf119_disp_intr;
|
||||
INIT_WORK(&disp->supervisor, gf119_disp_intr_supervisor);
|
||||
disp->sclass = gf119_disp_sclass;
|
||||
disp->head.nr = heads;
|
||||
disp->dac.nr = 3;
|
||||
disp->sor.nr = 4;
|
||||
disp->dac.power = nv50_dac_power;
|
||||
disp->dac.sense = nv50_dac_sense;
|
||||
disp->sor.power = nv50_sor_power;
|
||||
disp->sor.hda_eld = gf119_hda_eld;
|
||||
disp->sor.hdmi = gf119_hdmi_ctrl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct nvkm_oclass *
|
||||
gf110_disp_oclass = &(struct nv50_disp_impl) {
|
||||
.base.base.handle = NV_ENGINE(DISP, 0x90),
|
||||
.base.base.ofuncs = &(struct nvkm_ofuncs) {
|
||||
.ctor = gf119_disp_ctor,
|
||||
.dtor = _nvkm_disp_dtor,
|
||||
.init = _nvkm_disp_init,
|
||||
.fini = _nvkm_disp_fini,
|
||||
},
|
||||
.base.outp.internal.crt = nv50_dac_output_new,
|
||||
.base.outp.internal.tmds = nv50_sor_output_new,
|
||||
.base.outp.internal.lvds = nv50_sor_output_new,
|
||||
.base.outp.internal.dp = gf119_sor_dp_new,
|
||||
.base.vblank = &gf119_disp_vblank_func,
|
||||
.mthd.core = &gf119_disp_core_mthd_chan,
|
||||
.mthd.base = &gf119_disp_base_mthd_chan,
|
||||
.mthd.ovly = &gf119_disp_ovly_mthd_chan,
|
||||
.mthd.prev = -0x020000,
|
||||
.head.scanoutpos = gf119_disp_root_scanoutpos,
|
||||
}.base.base;
|
|
@ -22,197 +22,7 @@
|
|||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "nv50.h"
|
||||
|
||||
#include <nvif/class.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* EVO master channel object
|
||||
******************************************************************************/
|
||||
|
||||
static const struct nv50_disp_mthd_list
|
||||
gk104_disp_core_mthd_head = {
|
||||
.mthd = 0x0300,
|
||||
.addr = 0x000300,
|
||||
.data = {
|
||||
{ 0x0400, 0x660400 },
|
||||
{ 0x0404, 0x660404 },
|
||||
{ 0x0408, 0x660408 },
|
||||
{ 0x040c, 0x66040c },
|
||||
{ 0x0410, 0x660410 },
|
||||
{ 0x0414, 0x660414 },
|
||||
{ 0x0418, 0x660418 },
|
||||
{ 0x041c, 0x66041c },
|
||||
{ 0x0420, 0x660420 },
|
||||
{ 0x0424, 0x660424 },
|
||||
{ 0x0428, 0x660428 },
|
||||
{ 0x042c, 0x66042c },
|
||||
{ 0x0430, 0x660430 },
|
||||
{ 0x0434, 0x660434 },
|
||||
{ 0x0438, 0x660438 },
|
||||
{ 0x0440, 0x660440 },
|
||||
{ 0x0444, 0x660444 },
|
||||
{ 0x0448, 0x660448 },
|
||||
{ 0x044c, 0x66044c },
|
||||
{ 0x0450, 0x660450 },
|
||||
{ 0x0454, 0x660454 },
|
||||
{ 0x0458, 0x660458 },
|
||||
{ 0x045c, 0x66045c },
|
||||
{ 0x0460, 0x660460 },
|
||||
{ 0x0468, 0x660468 },
|
||||
{ 0x046c, 0x66046c },
|
||||
{ 0x0470, 0x660470 },
|
||||
{ 0x0474, 0x660474 },
|
||||
{ 0x047c, 0x66047c },
|
||||
{ 0x0480, 0x660480 },
|
||||
{ 0x0484, 0x660484 },
|
||||
{ 0x0488, 0x660488 },
|
||||
{ 0x048c, 0x66048c },
|
||||
{ 0x0490, 0x660490 },
|
||||
{ 0x0494, 0x660494 },
|
||||
{ 0x0498, 0x660498 },
|
||||
{ 0x04a0, 0x6604a0 },
|
||||
{ 0x04b0, 0x6604b0 },
|
||||
{ 0x04b8, 0x6604b8 },
|
||||
{ 0x04bc, 0x6604bc },
|
||||
{ 0x04c0, 0x6604c0 },
|
||||
{ 0x04c4, 0x6604c4 },
|
||||
{ 0x04c8, 0x6604c8 },
|
||||
{ 0x04d0, 0x6604d0 },
|
||||
{ 0x04d4, 0x6604d4 },
|
||||
{ 0x04e0, 0x6604e0 },
|
||||
{ 0x04e4, 0x6604e4 },
|
||||
{ 0x04e8, 0x6604e8 },
|
||||
{ 0x04ec, 0x6604ec },
|
||||
{ 0x04f0, 0x6604f0 },
|
||||
{ 0x04f4, 0x6604f4 },
|
||||
{ 0x04f8, 0x6604f8 },
|
||||
{ 0x04fc, 0x6604fc },
|
||||
{ 0x0500, 0x660500 },
|
||||
{ 0x0504, 0x660504 },
|
||||
{ 0x0508, 0x660508 },
|
||||
{ 0x050c, 0x66050c },
|
||||
{ 0x0510, 0x660510 },
|
||||
{ 0x0514, 0x660514 },
|
||||
{ 0x0518, 0x660518 },
|
||||
{ 0x051c, 0x66051c },
|
||||
{ 0x0520, 0x660520 },
|
||||
{ 0x0524, 0x660524 },
|
||||
{ 0x052c, 0x66052c },
|
||||
{ 0x0530, 0x660530 },
|
||||
{ 0x054c, 0x66054c },
|
||||
{ 0x0550, 0x660550 },
|
||||
{ 0x0554, 0x660554 },
|
||||
{ 0x0558, 0x660558 },
|
||||
{ 0x055c, 0x66055c },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
const struct nv50_disp_mthd_chan
|
||||
gk104_disp_core_mthd_chan = {
|
||||
.name = "Core",
|
||||
.addr = 0x000000,
|
||||
.data = {
|
||||
{ "Global", 1, &gf110_disp_core_mthd_base },
|
||||
{ "DAC", 3, &gf110_disp_core_mthd_dac },
|
||||
{ "SOR", 8, &gf110_disp_core_mthd_sor },
|
||||
{ "PIOR", 4, &gf110_disp_core_mthd_pior },
|
||||
{ "HEAD", 4, &gk104_disp_core_mthd_head },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* EVO overlay channel objects
|
||||
******************************************************************************/
|
||||
|
||||
static const struct nv50_disp_mthd_list
|
||||
gk104_disp_ovly_mthd_base = {
|
||||
.mthd = 0x0000,
|
||||
.data = {
|
||||
{ 0x0080, 0x665080 },
|
||||
{ 0x0084, 0x665084 },
|
||||
{ 0x0088, 0x665088 },
|
||||
{ 0x008c, 0x66508c },
|
||||
{ 0x0090, 0x665090 },
|
||||
{ 0x0094, 0x665094 },
|
||||
{ 0x00a0, 0x6650a0 },
|
||||
{ 0x00a4, 0x6650a4 },
|
||||
{ 0x00b0, 0x6650b0 },
|
||||
{ 0x00b4, 0x6650b4 },
|
||||
{ 0x00b8, 0x6650b8 },
|
||||
{ 0x00c0, 0x6650c0 },
|
||||
{ 0x00c4, 0x6650c4 },
|
||||
{ 0x00e0, 0x6650e0 },
|
||||
{ 0x00e4, 0x6650e4 },
|
||||
{ 0x00e8, 0x6650e8 },
|
||||
{ 0x0100, 0x665100 },
|
||||
{ 0x0104, 0x665104 },
|
||||
{ 0x0108, 0x665108 },
|
||||
{ 0x010c, 0x66510c },
|
||||
{ 0x0110, 0x665110 },
|
||||
{ 0x0118, 0x665118 },
|
||||
{ 0x011c, 0x66511c },
|
||||
{ 0x0120, 0x665120 },
|
||||
{ 0x0124, 0x665124 },
|
||||
{ 0x0130, 0x665130 },
|
||||
{ 0x0134, 0x665134 },
|
||||
{ 0x0138, 0x665138 },
|
||||
{ 0x013c, 0x66513c },
|
||||
{ 0x0140, 0x665140 },
|
||||
{ 0x0144, 0x665144 },
|
||||
{ 0x0148, 0x665148 },
|
||||
{ 0x014c, 0x66514c },
|
||||
{ 0x0150, 0x665150 },
|
||||
{ 0x0154, 0x665154 },
|
||||
{ 0x0158, 0x665158 },
|
||||
{ 0x015c, 0x66515c },
|
||||
{ 0x0160, 0x665160 },
|
||||
{ 0x0164, 0x665164 },
|
||||
{ 0x0168, 0x665168 },
|
||||
{ 0x016c, 0x66516c },
|
||||
{ 0x0400, 0x665400 },
|
||||
{ 0x0404, 0x665404 },
|
||||
{ 0x0408, 0x665408 },
|
||||
{ 0x040c, 0x66540c },
|
||||
{ 0x0410, 0x665410 },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
const struct nv50_disp_mthd_chan
|
||||
gk104_disp_ovly_mthd_chan = {
|
||||
.name = "Overlay",
|
||||
.addr = 0x001000,
|
||||
.data = {
|
||||
{ "Global", 1, &gk104_disp_ovly_mthd_base },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Base display object
|
||||
******************************************************************************/
|
||||
|
||||
static struct nvkm_oclass
|
||||
gk104_disp_sclass[] = {
|
||||
{ GK104_DISP_CORE_CHANNEL_DMA, &gf110_disp_core_ofuncs.base },
|
||||
{ GK104_DISP_BASE_CHANNEL_DMA, &gf110_disp_base_ofuncs.base },
|
||||
{ GK104_DISP_OVERLAY_CONTROL_DMA, &gf110_disp_ovly_ofuncs.base },
|
||||
{ GK104_DISP_OVERLAY, &gf110_disp_oimm_ofuncs.base },
|
||||
{ GK104_DISP_CURSOR, &gf110_disp_curs_ofuncs.base },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct nvkm_oclass
|
||||
gk104_disp_main_oclass[] = {
|
||||
{ GK104_DISP, &gf110_disp_main_ofuncs },
|
||||
{}
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Display engine implementation
|
||||
******************************************************************************/
|
||||
#include "rootnv50.h"
|
||||
|
||||
static int
|
||||
gk104_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
||||
|
@ -230,14 +40,14 @@ gk104_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = nvkm_event_init(&gf110_disp_chan_uevent, 1, 17, &disp->uevent);
|
||||
ret = nvkm_event_init(&gf119_disp_chan_uevent, 1, 17, &disp->uevent);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
nv_engine(disp)->sclass = gk104_disp_main_oclass;
|
||||
nv_engine(disp)->sclass = gk104_disp_root_oclass;
|
||||
nv_engine(disp)->cclass = &nv50_disp_cclass;
|
||||
nv_subdev(disp)->intr = gf110_disp_intr;
|
||||
INIT_WORK(&disp->supervisor, gf110_disp_intr_supervisor);
|
||||
nv_subdev(disp)->intr = gf119_disp_intr;
|
||||
INIT_WORK(&disp->supervisor, gf119_disp_intr_supervisor);
|
||||
disp->sclass = gk104_disp_sclass;
|
||||
disp->head.nr = heads;
|
||||
disp->dac.nr = 3;
|
||||
|
@ -245,7 +55,7 @@ gk104_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
|||
disp->dac.power = nv50_dac_power;
|
||||
disp->dac.sense = nv50_dac_sense;
|
||||
disp->sor.power = nv50_sor_power;
|
||||
disp->sor.hda_eld = gf110_hda_eld;
|
||||
disp->sor.hda_eld = gf119_hda_eld;
|
||||
disp->sor.hdmi = gk104_hdmi_ctrl;
|
||||
return 0;
|
||||
}
|
||||
|
@ -262,11 +72,11 @@ gk104_disp_oclass = &(struct nv50_disp_impl) {
|
|||
.base.outp.internal.crt = nv50_dac_output_new,
|
||||
.base.outp.internal.tmds = nv50_sor_output_new,
|
||||
.base.outp.internal.lvds = nv50_sor_output_new,
|
||||
.base.outp.internal.dp = gf110_sor_dp_new,
|
||||
.base.vblank = &gf110_disp_vblank_func,
|
||||
.base.outp.internal.dp = gf119_sor_dp_new,
|
||||
.base.vblank = &gf119_disp_vblank_func,
|
||||
.mthd.core = &gk104_disp_core_mthd_chan,
|
||||
.mthd.base = &gf110_disp_base_mthd_chan,
|
||||
.mthd.base = &gf119_disp_base_mthd_chan,
|
||||
.mthd.ovly = &gk104_disp_ovly_mthd_chan,
|
||||
.mthd.prev = -0x020000,
|
||||
.head.scanoutpos = gf110_disp_main_scanoutpos,
|
||||
.head.scanoutpos = gf119_disp_root_scanoutpos,
|
||||
}.base.base;
|
||||
|
|
|
@ -22,32 +22,7 @@
|
|||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "nv50.h"
|
||||
|
||||
#include <nvif/class.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* Base display object
|
||||
******************************************************************************/
|
||||
|
||||
static struct nvkm_oclass
|
||||
gk110_disp_sclass[] = {
|
||||
{ GK110_DISP_CORE_CHANNEL_DMA, &gf110_disp_core_ofuncs.base },
|
||||
{ GK110_DISP_BASE_CHANNEL_DMA, &gf110_disp_base_ofuncs.base },
|
||||
{ GK104_DISP_OVERLAY_CONTROL_DMA, &gf110_disp_ovly_ofuncs.base },
|
||||
{ GK104_DISP_OVERLAY, &gf110_disp_oimm_ofuncs.base },
|
||||
{ GK104_DISP_CURSOR, &gf110_disp_curs_ofuncs.base },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct nvkm_oclass
|
||||
gk110_disp_main_oclass[] = {
|
||||
{ GK110_DISP, &gf110_disp_main_ofuncs },
|
||||
{}
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Display engine implementation
|
||||
******************************************************************************/
|
||||
#include "rootnv50.h"
|
||||
|
||||
static int
|
||||
gk110_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
||||
|
@ -65,14 +40,14 @@ gk110_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = nvkm_event_init(&gf110_disp_chan_uevent, 1, 17, &disp->uevent);
|
||||
ret = nvkm_event_init(&gf119_disp_chan_uevent, 1, 17, &disp->uevent);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
nv_engine(disp)->sclass = gk110_disp_main_oclass;
|
||||
nv_engine(disp)->sclass = gk110_disp_root_oclass;
|
||||
nv_engine(disp)->cclass = &nv50_disp_cclass;
|
||||
nv_subdev(disp)->intr = gf110_disp_intr;
|
||||
INIT_WORK(&disp->supervisor, gf110_disp_intr_supervisor);
|
||||
nv_subdev(disp)->intr = gf119_disp_intr;
|
||||
INIT_WORK(&disp->supervisor, gf119_disp_intr_supervisor);
|
||||
disp->sclass = gk110_disp_sclass;
|
||||
disp->head.nr = heads;
|
||||
disp->dac.nr = 3;
|
||||
|
@ -80,7 +55,7 @@ gk110_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
|||
disp->dac.power = nv50_dac_power;
|
||||
disp->dac.sense = nv50_dac_sense;
|
||||
disp->sor.power = nv50_sor_power;
|
||||
disp->sor.hda_eld = gf110_hda_eld;
|
||||
disp->sor.hda_eld = gf119_hda_eld;
|
||||
disp->sor.hdmi = gk104_hdmi_ctrl;
|
||||
return 0;
|
||||
}
|
||||
|
@ -97,11 +72,11 @@ gk110_disp_oclass = &(struct nv50_disp_impl) {
|
|||
.base.outp.internal.crt = nv50_dac_output_new,
|
||||
.base.outp.internal.tmds = nv50_sor_output_new,
|
||||
.base.outp.internal.lvds = nv50_sor_output_new,
|
||||
.base.outp.internal.dp = gf110_sor_dp_new,
|
||||
.base.vblank = &gf110_disp_vblank_func,
|
||||
.base.outp.internal.dp = gf119_sor_dp_new,
|
||||
.base.vblank = &gf119_disp_vblank_func,
|
||||
.mthd.core = &gk104_disp_core_mthd_chan,
|
||||
.mthd.base = &gf110_disp_base_mthd_chan,
|
||||
.mthd.base = &gf119_disp_base_mthd_chan,
|
||||
.mthd.ovly = &gk104_disp_ovly_mthd_chan,
|
||||
.mthd.prev = -0x020000,
|
||||
.head.scanoutpos = gf110_disp_main_scanoutpos,
|
||||
.head.scanoutpos = gf119_disp_root_scanoutpos,
|
||||
}.base.base;
|
||||
|
|
|
@ -22,32 +22,7 @@
|
|||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "nv50.h"
|
||||
|
||||
#include <nvif/class.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* Base display object
|
||||
******************************************************************************/
|
||||
|
||||
static struct nvkm_oclass
|
||||
gm107_disp_sclass[] = {
|
||||
{ GM107_DISP_CORE_CHANNEL_DMA, &gf110_disp_core_ofuncs.base },
|
||||
{ GK110_DISP_BASE_CHANNEL_DMA, &gf110_disp_base_ofuncs.base },
|
||||
{ GK104_DISP_OVERLAY_CONTROL_DMA, &gf110_disp_ovly_ofuncs.base },
|
||||
{ GK104_DISP_OVERLAY, &gf110_disp_oimm_ofuncs.base },
|
||||
{ GK104_DISP_CURSOR, &gf110_disp_curs_ofuncs.base },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct nvkm_oclass
|
||||
gm107_disp_main_oclass[] = {
|
||||
{ GM107_DISP, &gf110_disp_main_ofuncs },
|
||||
{}
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Display engine implementation
|
||||
******************************************************************************/
|
||||
#include "rootnv50.h"
|
||||
|
||||
static int
|
||||
gm107_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
||||
|
@ -65,14 +40,14 @@ gm107_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = nvkm_event_init(&gf110_disp_chan_uevent, 1, 17, &disp->uevent);
|
||||
ret = nvkm_event_init(&gf119_disp_chan_uevent, 1, 17, &disp->uevent);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
nv_engine(disp)->sclass = gm107_disp_main_oclass;
|
||||
nv_engine(disp)->sclass = gm107_disp_root_oclass;
|
||||
nv_engine(disp)->cclass = &nv50_disp_cclass;
|
||||
nv_subdev(disp)->intr = gf110_disp_intr;
|
||||
INIT_WORK(&disp->supervisor, gf110_disp_intr_supervisor);
|
||||
nv_subdev(disp)->intr = gf119_disp_intr;
|
||||
INIT_WORK(&disp->supervisor, gf119_disp_intr_supervisor);
|
||||
disp->sclass = gm107_disp_sclass;
|
||||
disp->head.nr = heads;
|
||||
disp->dac.nr = 3;
|
||||
|
@ -80,7 +55,7 @@ gm107_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
|||
disp->dac.power = nv50_dac_power;
|
||||
disp->dac.sense = nv50_dac_sense;
|
||||
disp->sor.power = nv50_sor_power;
|
||||
disp->sor.hda_eld = gf110_hda_eld;
|
||||
disp->sor.hda_eld = gf119_hda_eld;
|
||||
disp->sor.hdmi = gk104_hdmi_ctrl;
|
||||
return 0;
|
||||
}
|
||||
|
@ -97,11 +72,11 @@ gm107_disp_oclass = &(struct nv50_disp_impl) {
|
|||
.base.outp.internal.crt = nv50_dac_output_new,
|
||||
.base.outp.internal.tmds = nv50_sor_output_new,
|
||||
.base.outp.internal.lvds = nv50_sor_output_new,
|
||||
.base.outp.internal.dp = gf110_sor_dp_new,
|
||||
.base.vblank = &gf110_disp_vblank_func,
|
||||
.base.outp.internal.dp = gf119_sor_dp_new,
|
||||
.base.vblank = &gf119_disp_vblank_func,
|
||||
.mthd.core = &gk104_disp_core_mthd_chan,
|
||||
.mthd.base = &gf110_disp_base_mthd_chan,
|
||||
.mthd.base = &gf119_disp_base_mthd_chan,
|
||||
.mthd.ovly = &gk104_disp_ovly_mthd_chan,
|
||||
.mthd.prev = -0x020000,
|
||||
.head.scanoutpos = gf110_disp_main_scanoutpos,
|
||||
.head.scanoutpos = gf119_disp_root_scanoutpos,
|
||||
}.base.base;
|
||||
|
|
|
@ -22,33 +22,7 @@
|
|||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "nv50.h"
|
||||
#include "outpdp.h"
|
||||
|
||||
#include <nvif/class.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* Base display object
|
||||
******************************************************************************/
|
||||
|
||||
static struct nvkm_oclass
|
||||
gm204_disp_sclass[] = {
|
||||
{ GM204_DISP_CORE_CHANNEL_DMA, &gf110_disp_core_ofuncs.base },
|
||||
{ GK110_DISP_BASE_CHANNEL_DMA, &gf110_disp_base_ofuncs.base },
|
||||
{ GK104_DISP_OVERLAY_CONTROL_DMA, &gf110_disp_ovly_ofuncs.base },
|
||||
{ GK104_DISP_OVERLAY, &gf110_disp_oimm_ofuncs.base },
|
||||
{ GK104_DISP_CURSOR, &gf110_disp_curs_ofuncs.base },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct nvkm_oclass
|
||||
gm204_disp_main_oclass[] = {
|
||||
{ GM204_DISP, &gf110_disp_main_ofuncs },
|
||||
{}
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Display engine implementation
|
||||
******************************************************************************/
|
||||
#include "rootnv50.h"
|
||||
|
||||
static int
|
||||
gm204_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
||||
|
@ -66,14 +40,14 @@ gm204_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = nvkm_event_init(&gf110_disp_chan_uevent, 1, 17, &disp->uevent);
|
||||
ret = nvkm_event_init(&gf119_disp_chan_uevent, 1, 17, &disp->uevent);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
nv_engine(disp)->sclass = gm204_disp_main_oclass;
|
||||
nv_engine(disp)->sclass = gm204_disp_root_oclass;
|
||||
nv_engine(disp)->cclass = &nv50_disp_cclass;
|
||||
nv_subdev(disp)->intr = gf110_disp_intr;
|
||||
INIT_WORK(&disp->supervisor, gf110_disp_intr_supervisor);
|
||||
nv_subdev(disp)->intr = gf119_disp_intr;
|
||||
INIT_WORK(&disp->supervisor, gf119_disp_intr_supervisor);
|
||||
disp->sclass = gm204_disp_sclass;
|
||||
disp->head.nr = heads;
|
||||
disp->dac.nr = 3;
|
||||
|
@ -81,8 +55,8 @@ gm204_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
|||
disp->dac.power = nv50_dac_power;
|
||||
disp->dac.sense = nv50_dac_sense;
|
||||
disp->sor.power = nv50_sor_power;
|
||||
disp->sor.hda_eld = gf110_hda_eld;
|
||||
disp->sor.hdmi = gf110_hdmi_ctrl;
|
||||
disp->sor.hda_eld = gf119_hda_eld;
|
||||
disp->sor.hdmi = gf119_hdmi_ctrl;
|
||||
disp->sor.magic = gm204_sor_magic;
|
||||
return 0;
|
||||
}
|
||||
|
@ -100,10 +74,10 @@ gm204_disp_oclass = &(struct nv50_disp_impl) {
|
|||
.base.outp.internal.tmds = nv50_sor_output_new,
|
||||
.base.outp.internal.lvds = nv50_sor_output_new,
|
||||
.base.outp.internal.dp = gm204_sor_dp_new,
|
||||
.base.vblank = &gf110_disp_vblank_func,
|
||||
.base.vblank = &gf119_disp_vblank_func,
|
||||
.mthd.core = &gk104_disp_core_mthd_chan,
|
||||
.mthd.base = &gf110_disp_base_mthd_chan,
|
||||
.mthd.base = &gf119_disp_base_mthd_chan,
|
||||
.mthd.ovly = &gk104_disp_ovly_mthd_chan,
|
||||
.mthd.prev = -0x020000,
|
||||
.head.scanoutpos = gf110_disp_main_scanoutpos,
|
||||
.head.scanoutpos = gf119_disp_root_scanoutpos,
|
||||
}.base.base;
|
||||
|
|
|
@ -22,77 +22,7 @@
|
|||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "nv50.h"
|
||||
|
||||
#include <nvif/class.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* EVO overlay channel objects
|
||||
******************************************************************************/
|
||||
|
||||
static const struct nv50_disp_mthd_list
|
||||
gt200_disp_ovly_mthd_base = {
|
||||
.mthd = 0x0000,
|
||||
.addr = 0x000000,
|
||||
.data = {
|
||||
{ 0x0080, 0x000000 },
|
||||
{ 0x0084, 0x6109a0 },
|
||||
{ 0x0088, 0x6109c0 },
|
||||
{ 0x008c, 0x6109c8 },
|
||||
{ 0x0090, 0x6109b4 },
|
||||
{ 0x0094, 0x610970 },
|
||||
{ 0x00a0, 0x610998 },
|
||||
{ 0x00a4, 0x610964 },
|
||||
{ 0x00b0, 0x610c98 },
|
||||
{ 0x00b4, 0x610ca4 },
|
||||
{ 0x00b8, 0x610cac },
|
||||
{ 0x00c0, 0x610958 },
|
||||
{ 0x00e0, 0x6109a8 },
|
||||
{ 0x00e4, 0x6109d0 },
|
||||
{ 0x00e8, 0x6109d8 },
|
||||
{ 0x0100, 0x61094c },
|
||||
{ 0x0104, 0x610984 },
|
||||
{ 0x0108, 0x61098c },
|
||||
{ 0x0800, 0x6109f8 },
|
||||
{ 0x0808, 0x610a08 },
|
||||
{ 0x080c, 0x610a10 },
|
||||
{ 0x0810, 0x610a00 },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
static const struct nv50_disp_mthd_chan
|
||||
gt200_disp_ovly_mthd_chan = {
|
||||
.name = "Overlay",
|
||||
.addr = 0x000540,
|
||||
.data = {
|
||||
{ "Global", 1, >200_disp_ovly_mthd_base },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Base display object
|
||||
******************************************************************************/
|
||||
|
||||
static struct nvkm_oclass
|
||||
gt200_disp_sclass[] = {
|
||||
{ GT200_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
|
||||
{ GT200_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
|
||||
{ GT200_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
|
||||
{ G82_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
|
||||
{ G82_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct nvkm_oclass
|
||||
gt200_disp_main_oclass[] = {
|
||||
{ GT200_DISP, &nv50_disp_main_ofuncs },
|
||||
{}
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Display engine implementation
|
||||
******************************************************************************/
|
||||
#include "rootnv50.h"
|
||||
|
||||
static int
|
||||
gt200_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
||||
|
@ -112,7 +42,7 @@ gt200_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
nv_engine(disp)->sclass = gt200_disp_main_oclass;
|
||||
nv_engine(disp)->sclass = gt200_disp_root_oclass;
|
||||
nv_engine(disp)->cclass = &nv50_disp_cclass;
|
||||
nv_subdev(disp)->intr = nv50_disp_intr;
|
||||
INIT_WORK(&disp->supervisor, nv50_disp_intr_supervisor);
|
||||
|
@ -148,5 +78,5 @@ gt200_disp_oclass = &(struct nv50_disp_impl) {
|
|||
.mthd.base = &g84_disp_base_mthd_chan,
|
||||
.mthd.ovly = >200_disp_ovly_mthd_chan,
|
||||
.mthd.prev = 0x000004,
|
||||
.head.scanoutpos = nv50_disp_main_scanoutpos,
|
||||
.head.scanoutpos = nv50_disp_root_scanoutpos,
|
||||
}.base.base;
|
||||
|
|
|
@ -22,32 +22,7 @@
|
|||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "nv50.h"
|
||||
|
||||
#include <nvif/class.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* Base display object
|
||||
******************************************************************************/
|
||||
|
||||
static struct nvkm_oclass
|
||||
gt215_disp_sclass[] = {
|
||||
{ GT214_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
|
||||
{ GT214_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
|
||||
{ GT214_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
|
||||
{ GT214_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
|
||||
{ GT214_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct nvkm_oclass
|
||||
gt215_disp_main_oclass[] = {
|
||||
{ GT214_DISP, &nv50_disp_main_ofuncs },
|
||||
{}
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Display engine implementation
|
||||
******************************************************************************/
|
||||
#include "rootnv50.h"
|
||||
|
||||
static int
|
||||
gt215_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
||||
|
@ -67,7 +42,7 @@ gt215_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
nv_engine(disp)->sclass = gt215_disp_main_oclass;
|
||||
nv_engine(disp)->sclass = gt215_disp_root_oclass;
|
||||
nv_engine(disp)->cclass = &nv50_disp_cclass;
|
||||
nv_subdev(disp)->intr = nv50_disp_intr;
|
||||
INIT_WORK(&disp->supervisor, nv50_disp_intr_supervisor);
|
||||
|
@ -105,5 +80,5 @@ gt215_disp_oclass = &(struct nv50_disp_impl) {
|
|||
.mthd.base = &g84_disp_base_mthd_chan,
|
||||
.mthd.ovly = &g84_disp_ovly_mthd_chan,
|
||||
.mthd.prev = 0x000004,
|
||||
.head.scanoutpos = nv50_disp_main_scanoutpos,
|
||||
.head.scanoutpos = nv50_disp_root_scanoutpos,
|
||||
}.base.base;
|
||||
|
|
|
@ -33,7 +33,7 @@
|
|||
#include <nvif/unpack.h>
|
||||
|
||||
int
|
||||
gf110_hda_eld(NV50_DISP_MTHD_V1)
|
||||
gf119_hda_eld(NV50_DISP_MTHD_V1)
|
||||
{
|
||||
struct nvkm_device *device = disp->base.engine.subdev.device;
|
||||
union {
|
|
@ -29,7 +29,7 @@
|
|||
#include <nvif/unpack.h>
|
||||
|
||||
int
|
||||
gf110_hdmi_ctrl(NV50_DISP_MTHD_V1)
|
||||
gf119_hdmi_ctrl(NV50_DISP_MTHD_V1)
|
||||
{
|
||||
struct nvkm_device *device = disp->base.engine.subdev.device;
|
||||
const u32 hoff = (head * 0x800);
|
|
@ -23,105 +23,6 @@
|
|||
*/
|
||||
#include "priv.h"
|
||||
|
||||
#include <core/client.h>
|
||||
|
||||
#include <nvif/class.h>
|
||||
#include <nvif/unpack.h>
|
||||
|
||||
static int
|
||||
nv04_disp_scanoutpos(struct nvkm_object *object, struct nvkm_disp *disp,
|
||||
void *data, u32 size, int head)
|
||||
{
|
||||
struct nvkm_device *device = disp->engine.subdev.device;
|
||||
const u32 hoff = head * 0x2000;
|
||||
union {
|
||||
struct nv04_disp_scanoutpos_v0 v0;
|
||||
} *args = data;
|
||||
u32 line;
|
||||
int ret;
|
||||
|
||||
nvif_ioctl(object, "disp scanoutpos size %d\n", size);
|
||||
if (nvif_unpack(args->v0, 0, 0, false)) {
|
||||
nvif_ioctl(object, "disp scanoutpos vers %d\n",
|
||||
args->v0.version);
|
||||
args->v0.vblanks = nvkm_rd32(device, 0x680800 + hoff) & 0xffff;
|
||||
args->v0.vtotal = nvkm_rd32(device, 0x680804 + hoff) & 0xffff;
|
||||
args->v0.vblanke = args->v0.vtotal - 1;
|
||||
|
||||
args->v0.hblanks = nvkm_rd32(device, 0x680820 + hoff) & 0xffff;
|
||||
args->v0.htotal = nvkm_rd32(device, 0x680824 + hoff) & 0xffff;
|
||||
args->v0.hblanke = args->v0.htotal - 1;
|
||||
|
||||
/*
|
||||
* If output is vga instead of digital then vtotal/htotal is
|
||||
* invalid so we have to give up and trigger the timestamping
|
||||
* fallback in the drm core.
|
||||
*/
|
||||
if (!args->v0.vtotal || !args->v0.htotal)
|
||||
return -ENOTSUPP;
|
||||
|
||||
args->v0.time[0] = ktime_to_ns(ktime_get());
|
||||
line = nvkm_rd32(device, 0x600868 + hoff);
|
||||
args->v0.time[1] = ktime_to_ns(ktime_get());
|
||||
args->v0.hline = (line & 0xffff0000) >> 16;
|
||||
args->v0.vline = (line & 0x0000ffff);
|
||||
} else
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
nv04_disp_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size)
|
||||
{
|
||||
union {
|
||||
struct nv04_disp_mthd_v0 v0;
|
||||
} *args = data;
|
||||
struct nvkm_disp *disp = (void *)object->engine;
|
||||
int head, ret;
|
||||
|
||||
nvif_ioctl(object, "disp mthd size %d\n", size);
|
||||
if (nvif_unpack(args->v0, 0, 0, true)) {
|
||||
nvif_ioctl(object, "disp mthd vers %d mthd %02x head %d\n",
|
||||
args->v0.version, args->v0.method, args->v0.head);
|
||||
mthd = args->v0.method;
|
||||
head = args->v0.head;
|
||||
} else
|
||||
return ret;
|
||||
|
||||
if (head < 0 || head >= 2)
|
||||
return -ENXIO;
|
||||
|
||||
switch (mthd) {
|
||||
case NV04_DISP_SCANOUTPOS:
|
||||
return nv04_disp_scanoutpos(object, disp, data, size, head);
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static struct nvkm_ofuncs
|
||||
nv04_disp_ofuncs = {
|
||||
.ctor = _nvkm_object_ctor,
|
||||
.dtor = nvkm_object_destroy,
|
||||
.init = _nvkm_object_init,
|
||||
.fini = _nvkm_object_fini,
|
||||
.mthd = nv04_disp_mthd,
|
||||
.ntfy = nvkm_disp_ntfy,
|
||||
};
|
||||
|
||||
static struct nvkm_oclass
|
||||
nv04_disp_sclass[] = {
|
||||
{ NV04_DISP, &nv04_disp_ofuncs },
|
||||
{},
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Display engine implementation
|
||||
******************************************************************************/
|
||||
|
||||
static void
|
||||
nv04_disp_vblank_init(struct nvkm_event *event, int type, int head)
|
||||
{
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -54,113 +54,37 @@ struct nv50_disp_impl {
|
|||
} head;
|
||||
};
|
||||
|
||||
int nv50_disp_main_scanoutpos(NV50_DISP_MTHD_V0);
|
||||
int nv50_disp_main_mthd(struct nvkm_object *, u32, void *, u32);
|
||||
int nv50_disp_root_scanoutpos(NV50_DISP_MTHD_V0);
|
||||
int nv50_disp_root_mthd(struct nvkm_object *, u32, void *, u32);
|
||||
|
||||
int gf110_disp_main_scanoutpos(NV50_DISP_MTHD_V0);
|
||||
int gf119_disp_root_scanoutpos(NV50_DISP_MTHD_V0);
|
||||
|
||||
int nv50_dac_power(NV50_DISP_MTHD_V1);
|
||||
int nv50_dac_sense(NV50_DISP_MTHD_V1);
|
||||
|
||||
int gt215_hda_eld(NV50_DISP_MTHD_V1);
|
||||
int gf110_hda_eld(NV50_DISP_MTHD_V1);
|
||||
int gf119_hda_eld(NV50_DISP_MTHD_V1);
|
||||
|
||||
int g84_hdmi_ctrl(NV50_DISP_MTHD_V1);
|
||||
int gt215_hdmi_ctrl(NV50_DISP_MTHD_V1);
|
||||
int gf110_hdmi_ctrl(NV50_DISP_MTHD_V1);
|
||||
int gf119_hdmi_ctrl(NV50_DISP_MTHD_V1);
|
||||
int gk104_hdmi_ctrl(NV50_DISP_MTHD_V1);
|
||||
|
||||
int nv50_sor_power(NV50_DISP_MTHD_V1);
|
||||
int nv50_pior_power(NV50_DISP_MTHD_V1);
|
||||
|
||||
#include <core/parent.h>
|
||||
|
||||
struct nv50_disp_base {
|
||||
struct nvkm_parent base;
|
||||
struct nvkm_ramht *ramht;
|
||||
u32 chan;
|
||||
};
|
||||
|
||||
struct nv50_disp_chan_impl {
|
||||
struct nvkm_ofuncs base;
|
||||
int chid;
|
||||
int (*attach)(struct nvkm_object *, struct nvkm_object *, u32);
|
||||
void (*detach)(struct nvkm_object *, int);
|
||||
};
|
||||
|
||||
#include <core/namedb.h>
|
||||
|
||||
struct nv50_disp_chan {
|
||||
struct nvkm_namedb base;
|
||||
int chid;
|
||||
};
|
||||
|
||||
int nv50_disp_chan_ntfy(struct nvkm_object *, u32, struct nvkm_event **);
|
||||
int nv50_disp_chan_map(struct nvkm_object *, u64 *, u32 *);
|
||||
u32 nv50_disp_chan_rd32(struct nvkm_object *, u64);
|
||||
void nv50_disp_chan_wr32(struct nvkm_object *, u64, u32);
|
||||
extern const struct nvkm_event_func nv50_disp_chan_uevent;
|
||||
int nv50_disp_chan_uevent_ctor(struct nvkm_object *, void *, u32,
|
||||
struct nvkm_notify *);
|
||||
void nv50_disp_chan_uevent_send(struct nv50_disp *, int);
|
||||
|
||||
extern const struct nvkm_event_func gf110_disp_chan_uevent;
|
||||
|
||||
#define nv50_disp_chan_init(a) \
|
||||
nvkm_namedb_init(&(a)->base)
|
||||
#define nv50_disp_chan_fini(a,b) \
|
||||
nvkm_namedb_fini(&(a)->base, (b))
|
||||
|
||||
struct nv50_disp_dmac {
|
||||
struct nv50_disp_chan base;
|
||||
u32 push;
|
||||
};
|
||||
|
||||
void nv50_disp_dmac_dtor(struct nvkm_object *);
|
||||
|
||||
struct nv50_disp_pioc {
|
||||
struct nv50_disp_chan base;
|
||||
};
|
||||
|
||||
void nv50_disp_pioc_dtor(struct nvkm_object *);
|
||||
|
||||
struct nv50_disp_mthd_list {
|
||||
u32 mthd;
|
||||
u32 addr;
|
||||
struct {
|
||||
u32 mthd;
|
||||
u32 addr;
|
||||
const char *name;
|
||||
} data[];
|
||||
};
|
||||
|
||||
struct nv50_disp_mthd_chan {
|
||||
const char *name;
|
||||
u32 addr;
|
||||
struct {
|
||||
const char *name;
|
||||
int nr;
|
||||
const struct nv50_disp_mthd_list *mthd;
|
||||
} data[];
|
||||
};
|
||||
|
||||
extern struct nv50_disp_chan_impl nv50_disp_core_ofuncs;
|
||||
int nv50_disp_core_ctor(struct nvkm_object *, struct nvkm_object *,
|
||||
struct nvkm_oclass *, void *, u32,
|
||||
struct nvkm_object **);
|
||||
extern const struct nv50_disp_mthd_list nv50_disp_core_mthd_base;
|
||||
extern const struct nv50_disp_mthd_list nv50_disp_core_mthd_sor;
|
||||
extern const struct nv50_disp_mthd_list nv50_disp_core_mthd_pior;
|
||||
extern struct nv50_disp_chan_impl nv50_disp_base_ofuncs;
|
||||
int nv50_disp_base_ctor(struct nvkm_object *, struct nvkm_object *,
|
||||
struct nvkm_oclass *, void *, u32,
|
||||
struct nvkm_object **);
|
||||
extern const struct nv50_disp_mthd_list nv50_disp_base_mthd_image;
|
||||
extern struct nv50_disp_chan_impl nv50_disp_ovly_ofuncs;
|
||||
int nv50_disp_ovly_ctor(struct nvkm_object *, struct nvkm_object *,
|
||||
struct nvkm_oclass *, void *, u32,
|
||||
struct nvkm_object **);
|
||||
extern const struct nv50_disp_mthd_list nv50_disp_ovly_mthd_base;
|
||||
extern struct nv50_disp_chan_impl nv50_disp_oimm_ofuncs;
|
||||
int nv50_disp_oimm_ctor(struct nvkm_object *, struct nvkm_object *,
|
||||
struct nvkm_oclass *, void *, u32,
|
||||
|
@ -169,44 +93,26 @@ extern struct nv50_disp_chan_impl nv50_disp_curs_ofuncs;
|
|||
int nv50_disp_curs_ctor(struct nvkm_object *, struct nvkm_object *,
|
||||
struct nvkm_oclass *, void *, u32,
|
||||
struct nvkm_object **);
|
||||
extern struct nvkm_ofuncs nv50_disp_main_ofuncs;
|
||||
int nv50_disp_main_ctor(struct nvkm_object *, struct nvkm_object *,
|
||||
extern struct nvkm_ofuncs nv50_disp_root_ofuncs;
|
||||
int nv50_disp_root_ctor(struct nvkm_object *, struct nvkm_object *,
|
||||
struct nvkm_oclass *, void *, u32,
|
||||
struct nvkm_object **);
|
||||
void nv50_disp_main_dtor(struct nvkm_object *);
|
||||
void nv50_disp_root_dtor(struct nvkm_object *);
|
||||
extern struct nvkm_oclass nv50_disp_cclass;
|
||||
void nv50_disp_mthd_chan(struct nv50_disp *, int debug, int head,
|
||||
const struct nv50_disp_mthd_chan *);
|
||||
void nv50_disp_intr_supervisor(struct work_struct *);
|
||||
void nv50_disp_intr(struct nvkm_subdev *);
|
||||
extern const struct nvkm_event_func nv50_disp_vblank_func;
|
||||
|
||||
extern const struct nv50_disp_mthd_chan g84_disp_core_mthd_chan;
|
||||
extern const struct nv50_disp_mthd_list g84_disp_core_mthd_dac;
|
||||
extern const struct nv50_disp_mthd_list g84_disp_core_mthd_head;
|
||||
extern const struct nv50_disp_mthd_chan g84_disp_base_mthd_chan;
|
||||
extern const struct nv50_disp_mthd_chan g84_disp_ovly_mthd_chan;
|
||||
|
||||
extern const struct nv50_disp_mthd_chan g94_disp_core_mthd_chan;
|
||||
|
||||
extern struct nv50_disp_chan_impl gf110_disp_core_ofuncs;
|
||||
extern const struct nv50_disp_mthd_list gf110_disp_core_mthd_base;
|
||||
extern const struct nv50_disp_mthd_list gf110_disp_core_mthd_dac;
|
||||
extern const struct nv50_disp_mthd_list gf110_disp_core_mthd_sor;
|
||||
extern const struct nv50_disp_mthd_list gf110_disp_core_mthd_pior;
|
||||
extern struct nv50_disp_chan_impl gf110_disp_base_ofuncs;
|
||||
extern struct nv50_disp_chan_impl gf110_disp_ovly_ofuncs;
|
||||
extern const struct nv50_disp_mthd_chan gf110_disp_base_mthd_chan;
|
||||
extern struct nv50_disp_chan_impl gf110_disp_oimm_ofuncs;
|
||||
extern struct nv50_disp_chan_impl gf110_disp_curs_ofuncs;
|
||||
extern struct nvkm_ofuncs gf110_disp_main_ofuncs;
|
||||
extern struct nvkm_oclass gf110_disp_cclass;
|
||||
void gf110_disp_intr_supervisor(struct work_struct *);
|
||||
void gf110_disp_intr(struct nvkm_subdev *);
|
||||
extern const struct nvkm_event_func gf110_disp_vblank_func;
|
||||
|
||||
extern const struct nv50_disp_mthd_chan gk104_disp_core_mthd_chan;
|
||||
extern const struct nv50_disp_mthd_chan gk104_disp_ovly_mthd_chan;
|
||||
extern struct nv50_disp_chan_impl gf119_disp_core_ofuncs;
|
||||
extern struct nv50_disp_chan_impl gf119_disp_base_ofuncs;
|
||||
extern struct nv50_disp_chan_impl gf119_disp_ovly_ofuncs;
|
||||
extern struct nv50_disp_chan_impl gf119_disp_oimm_ofuncs;
|
||||
extern struct nv50_disp_chan_impl gf119_disp_curs_ofuncs;
|
||||
extern struct nvkm_ofuncs gf119_disp_root_ofuncs;
|
||||
extern struct nvkm_oclass gf119_disp_cclass;
|
||||
void gf119_disp_intr_supervisor(struct work_struct *);
|
||||
void gf119_disp_intr(struct nvkm_subdev *);
|
||||
extern const struct nvkm_event_func gf119_disp_vblank_func;
|
||||
|
||||
extern struct nvkm_output_dp_impl nv50_pior_dp_impl;
|
||||
extern struct nvkm_oclass *nv50_disp_outp_sclass[];
|
||||
|
@ -216,9 +122,9 @@ u32 g94_sor_dp_lane_map(struct nvkm_device *, u8 lane);
|
|||
int g94_sor_dp_lnk_pwr(struct nvkm_output_dp *, int);
|
||||
extern struct nvkm_oclass *g94_disp_outp_sclass[];
|
||||
|
||||
extern struct nvkm_output_dp_impl gf110_sor_dp_impl;
|
||||
int gf110_sor_dp_lnk_ctl(struct nvkm_output_dp *, int, int, bool);
|
||||
extern struct nvkm_oclass *gf110_disp_outp_sclass[];
|
||||
extern struct nvkm_output_dp_impl gf119_sor_dp_impl;
|
||||
int gf119_sor_dp_lnk_ctl(struct nvkm_output_dp *, int, int, bool);
|
||||
extern struct nvkm_oclass *gf119_disp_outp_sclass[];
|
||||
|
||||
void gm204_sor_magic(struct nvkm_output *outp);
|
||||
extern struct nvkm_output_dp_impl gm204_sor_dp_impl;
|
||||
|
|
|
@ -0,0 +1,37 @@
|
|||
/*
|
||||
* Copyright 2012 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "channv50.h"
|
||||
|
||||
struct nv50_disp_chan_impl
|
||||
gf119_disp_oimm_ofuncs = {
|
||||
.base.ctor = nv50_disp_oimm_ctor,
|
||||
.base.dtor = nv50_disp_pioc_dtor,
|
||||
.base.init = gf119_disp_pioc_init,
|
||||
.base.fini = gf119_disp_pioc_fini,
|
||||
.base.ntfy = nv50_disp_chan_ntfy,
|
||||
.base.map = nv50_disp_chan_map,
|
||||
.base.rd32 = nv50_disp_chan_rd32,
|
||||
.base.wr32 = nv50_disp_chan_wr32,
|
||||
.chid = 9,
|
||||
};
|
|
@ -0,0 +1,73 @@
|
|||
/*
|
||||
* Copyright 2012 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "channv50.h"
|
||||
|
||||
#include <core/client.h>
|
||||
|
||||
#include <nvif/class.h>
|
||||
#include <nvif/unpack.h>
|
||||
|
||||
int
|
||||
nv50_disp_oimm_ctor(struct nvkm_object *parent,
|
||||
struct nvkm_object *engine,
|
||||
struct nvkm_oclass *oclass, void *data, u32 size,
|
||||
struct nvkm_object **pobject)
|
||||
{
|
||||
union {
|
||||
struct nv50_disp_overlay_v0 v0;
|
||||
} *args = data;
|
||||
struct nv50_disp *disp = (void *)engine;
|
||||
struct nv50_disp_pioc *pioc;
|
||||
int ret;
|
||||
|
||||
nvif_ioctl(parent, "create disp overlay size %d\n", size);
|
||||
if (nvif_unpack(args->v0, 0, 0, false)) {
|
||||
nvif_ioctl(parent, "create disp overlay vers %d head %d\n",
|
||||
args->v0.version, args->v0.head);
|
||||
if (args->v0.head > disp->head.nr)
|
||||
return -EINVAL;
|
||||
} else
|
||||
return ret;
|
||||
|
||||
ret = nv50_disp_pioc_create_(parent, engine, oclass, args->v0.head,
|
||||
sizeof(*pioc), (void **)&pioc);
|
||||
*pobject = nv_object(pioc);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct nv50_disp_chan_impl
|
||||
nv50_disp_oimm_ofuncs = {
|
||||
.base.ctor = nv50_disp_oimm_ctor,
|
||||
.base.dtor = nv50_disp_pioc_dtor,
|
||||
.base.init = nv50_disp_pioc_init,
|
||||
.base.fini = nv50_disp_pioc_fini,
|
||||
.base.ntfy = nv50_disp_chan_ntfy,
|
||||
.base.map = nv50_disp_chan_map,
|
||||
.base.rd32 = nv50_disp_chan_rd32,
|
||||
.base.wr32 = nv50_disp_chan_wr32,
|
||||
.chid = 5,
|
||||
};
|
|
@ -58,7 +58,7 @@ int nv50_pior_dp_new(struct nvkm_disp *, int, struct dcb_output *,
|
|||
int g94_sor_dp_new(struct nvkm_disp *, int, struct dcb_output *,
|
||||
struct nvkm_output **);
|
||||
|
||||
int gf110_sor_dp_new(struct nvkm_disp *, int, struct dcb_output *,
|
||||
int gf119_sor_dp_new(struct nvkm_disp *, int, struct dcb_output *,
|
||||
struct nvkm_output **);
|
||||
|
||||
int gm204_sor_dp_new(struct nvkm_disp *, int, struct dcb_output *,
|
||||
|
|
|
@ -0,0 +1,62 @@
|
|||
/*
|
||||
* Copyright 2012 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "dmacnv50.h"
|
||||
|
||||
static const struct nv50_disp_mthd_list
|
||||
g84_disp_ovly_mthd_base = {
|
||||
.mthd = 0x0000,
|
||||
.addr = 0x000000,
|
||||
.data = {
|
||||
{ 0x0080, 0x000000 },
|
||||
{ 0x0084, 0x6109a0 },
|
||||
{ 0x0088, 0x6109c0 },
|
||||
{ 0x008c, 0x6109c8 },
|
||||
{ 0x0090, 0x6109b4 },
|
||||
{ 0x0094, 0x610970 },
|
||||
{ 0x00a0, 0x610998 },
|
||||
{ 0x00a4, 0x610964 },
|
||||
{ 0x00c0, 0x610958 },
|
||||
{ 0x00e0, 0x6109a8 },
|
||||
{ 0x00e4, 0x6109d0 },
|
||||
{ 0x00e8, 0x6109d8 },
|
||||
{ 0x0100, 0x61094c },
|
||||
{ 0x0104, 0x610984 },
|
||||
{ 0x0108, 0x61098c },
|
||||
{ 0x0800, 0x6109f8 },
|
||||
{ 0x0808, 0x610a08 },
|
||||
{ 0x080c, 0x610a10 },
|
||||
{ 0x0810, 0x610a00 },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
const struct nv50_disp_mthd_chan
|
||||
g84_disp_ovly_mthd_chan = {
|
||||
.name = "Overlay",
|
||||
.addr = 0x000540,
|
||||
.data = {
|
||||
{ "Global", 1, &g84_disp_ovly_mthd_base },
|
||||
{}
|
||||
}
|
||||
};
|
|
@ -0,0 +1,101 @@
|
|||
/*
|
||||
* Copyright 2012 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "dmacnv50.h"
|
||||
|
||||
static const struct nv50_disp_mthd_list
|
||||
gf119_disp_ovly_mthd_base = {
|
||||
.mthd = 0x0000,
|
||||
.data = {
|
||||
{ 0x0080, 0x665080 },
|
||||
{ 0x0084, 0x665084 },
|
||||
{ 0x0088, 0x665088 },
|
||||
{ 0x008c, 0x66508c },
|
||||
{ 0x0090, 0x665090 },
|
||||
{ 0x0094, 0x665094 },
|
||||
{ 0x00a0, 0x6650a0 },
|
||||
{ 0x00a4, 0x6650a4 },
|
||||
{ 0x00b0, 0x6650b0 },
|
||||
{ 0x00b4, 0x6650b4 },
|
||||
{ 0x00b8, 0x6650b8 },
|
||||
{ 0x00c0, 0x6650c0 },
|
||||
{ 0x00e0, 0x6650e0 },
|
||||
{ 0x00e4, 0x6650e4 },
|
||||
{ 0x00e8, 0x6650e8 },
|
||||
{ 0x0100, 0x665100 },
|
||||
{ 0x0104, 0x665104 },
|
||||
{ 0x0108, 0x665108 },
|
||||
{ 0x010c, 0x66510c },
|
||||
{ 0x0110, 0x665110 },
|
||||
{ 0x0118, 0x665118 },
|
||||
{ 0x011c, 0x66511c },
|
||||
{ 0x0120, 0x665120 },
|
||||
{ 0x0124, 0x665124 },
|
||||
{ 0x0130, 0x665130 },
|
||||
{ 0x0134, 0x665134 },
|
||||
{ 0x0138, 0x665138 },
|
||||
{ 0x013c, 0x66513c },
|
||||
{ 0x0140, 0x665140 },
|
||||
{ 0x0144, 0x665144 },
|
||||
{ 0x0148, 0x665148 },
|
||||
{ 0x014c, 0x66514c },
|
||||
{ 0x0150, 0x665150 },
|
||||
{ 0x0154, 0x665154 },
|
||||
{ 0x0158, 0x665158 },
|
||||
{ 0x015c, 0x66515c },
|
||||
{ 0x0160, 0x665160 },
|
||||
{ 0x0164, 0x665164 },
|
||||
{ 0x0168, 0x665168 },
|
||||
{ 0x016c, 0x66516c },
|
||||
{ 0x0400, 0x665400 },
|
||||
{ 0x0408, 0x665408 },
|
||||
{ 0x040c, 0x66540c },
|
||||
{ 0x0410, 0x665410 },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
const struct nv50_disp_mthd_chan
|
||||
gf119_disp_ovly_mthd_chan = {
|
||||
.name = "Overlay",
|
||||
.addr = 0x001000,
|
||||
.data = {
|
||||
{ "Global", 1, &gf119_disp_ovly_mthd_base },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
struct nv50_disp_chan_impl
|
||||
gf119_disp_ovly_ofuncs = {
|
||||
.base.ctor = nv50_disp_ovly_ctor,
|
||||
.base.dtor = nv50_disp_dmac_dtor,
|
||||
.base.init = gf119_disp_dmac_init,
|
||||
.base.fini = gf119_disp_dmac_fini,
|
||||
.base.ntfy = nv50_disp_chan_ntfy,
|
||||
.base.map = nv50_disp_chan_map,
|
||||
.base.rd32 = nv50_disp_chan_rd32,
|
||||
.base.wr32 = nv50_disp_chan_wr32,
|
||||
.chid = 5,
|
||||
.attach = gf119_disp_dmac_object_attach,
|
||||
.detach = gf119_disp_dmac_object_detach,
|
||||
};
|
|
@ -0,0 +1,88 @@
|
|||
/*
|
||||
* Copyright 2012 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "dmacnv50.h"
|
||||
|
||||
static const struct nv50_disp_mthd_list
|
||||
gk104_disp_ovly_mthd_base = {
|
||||
.mthd = 0x0000,
|
||||
.data = {
|
||||
{ 0x0080, 0x665080 },
|
||||
{ 0x0084, 0x665084 },
|
||||
{ 0x0088, 0x665088 },
|
||||
{ 0x008c, 0x66508c },
|
||||
{ 0x0090, 0x665090 },
|
||||
{ 0x0094, 0x665094 },
|
||||
{ 0x00a0, 0x6650a0 },
|
||||
{ 0x00a4, 0x6650a4 },
|
||||
{ 0x00b0, 0x6650b0 },
|
||||
{ 0x00b4, 0x6650b4 },
|
||||
{ 0x00b8, 0x6650b8 },
|
||||
{ 0x00c0, 0x6650c0 },
|
||||
{ 0x00c4, 0x6650c4 },
|
||||
{ 0x00e0, 0x6650e0 },
|
||||
{ 0x00e4, 0x6650e4 },
|
||||
{ 0x00e8, 0x6650e8 },
|
||||
{ 0x0100, 0x665100 },
|
||||
{ 0x0104, 0x665104 },
|
||||
{ 0x0108, 0x665108 },
|
||||
{ 0x010c, 0x66510c },
|
||||
{ 0x0110, 0x665110 },
|
||||
{ 0x0118, 0x665118 },
|
||||
{ 0x011c, 0x66511c },
|
||||
{ 0x0120, 0x665120 },
|
||||
{ 0x0124, 0x665124 },
|
||||
{ 0x0130, 0x665130 },
|
||||
{ 0x0134, 0x665134 },
|
||||
{ 0x0138, 0x665138 },
|
||||
{ 0x013c, 0x66513c },
|
||||
{ 0x0140, 0x665140 },
|
||||
{ 0x0144, 0x665144 },
|
||||
{ 0x0148, 0x665148 },
|
||||
{ 0x014c, 0x66514c },
|
||||
{ 0x0150, 0x665150 },
|
||||
{ 0x0154, 0x665154 },
|
||||
{ 0x0158, 0x665158 },
|
||||
{ 0x015c, 0x66515c },
|
||||
{ 0x0160, 0x665160 },
|
||||
{ 0x0164, 0x665164 },
|
||||
{ 0x0168, 0x665168 },
|
||||
{ 0x016c, 0x66516c },
|
||||
{ 0x0400, 0x665400 },
|
||||
{ 0x0404, 0x665404 },
|
||||
{ 0x0408, 0x665408 },
|
||||
{ 0x040c, 0x66540c },
|
||||
{ 0x0410, 0x665410 },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
const struct nv50_disp_mthd_chan
|
||||
gk104_disp_ovly_mthd_chan = {
|
||||
.name = "Overlay",
|
||||
.addr = 0x001000,
|
||||
.data = {
|
||||
{ "Global", 1, &gk104_disp_ovly_mthd_base },
|
||||
{}
|
||||
}
|
||||
};
|
|
@ -0,0 +1,65 @@
|
|||
/*
|
||||
* Copyright 2012 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "dmacnv50.h"
|
||||
|
||||
static const struct nv50_disp_mthd_list
|
||||
gt200_disp_ovly_mthd_base = {
|
||||
.mthd = 0x0000,
|
||||
.addr = 0x000000,
|
||||
.data = {
|
||||
{ 0x0080, 0x000000 },
|
||||
{ 0x0084, 0x6109a0 },
|
||||
{ 0x0088, 0x6109c0 },
|
||||
{ 0x008c, 0x6109c8 },
|
||||
{ 0x0090, 0x6109b4 },
|
||||
{ 0x0094, 0x610970 },
|
||||
{ 0x00a0, 0x610998 },
|
||||
{ 0x00a4, 0x610964 },
|
||||
{ 0x00b0, 0x610c98 },
|
||||
{ 0x00b4, 0x610ca4 },
|
||||
{ 0x00b8, 0x610cac },
|
||||
{ 0x00c0, 0x610958 },
|
||||
{ 0x00e0, 0x6109a8 },
|
||||
{ 0x00e4, 0x6109d0 },
|
||||
{ 0x00e8, 0x6109d8 },
|
||||
{ 0x0100, 0x61094c },
|
||||
{ 0x0104, 0x610984 },
|
||||
{ 0x0108, 0x61098c },
|
||||
{ 0x0800, 0x6109f8 },
|
||||
{ 0x0808, 0x610a08 },
|
||||
{ 0x080c, 0x610a10 },
|
||||
{ 0x0810, 0x610a00 },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
const struct nv50_disp_mthd_chan
|
||||
gt200_disp_ovly_mthd_chan = {
|
||||
.name = "Overlay",
|
||||
.addr = 0x000540,
|
||||
.data = {
|
||||
{ "Global", 1, >200_disp_ovly_mthd_base },
|
||||
{}
|
||||
}
|
||||
};
|
|
@ -0,0 +1,115 @@
|
|||
/*
|
||||
* Copyright 2012 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "dmacnv50.h"
|
||||
|
||||
#include <core/client.h>
|
||||
|
||||
#include <nvif/class.h>
|
||||
#include <nvif/unpack.h>
|
||||
|
||||
const struct nv50_disp_mthd_list
|
||||
nv50_disp_ovly_mthd_base = {
|
||||
.mthd = 0x0000,
|
||||
.addr = 0x000000,
|
||||
.data = {
|
||||
{ 0x0080, 0x000000 },
|
||||
{ 0x0084, 0x0009a0 },
|
||||
{ 0x0088, 0x0009c0 },
|
||||
{ 0x008c, 0x0009c8 },
|
||||
{ 0x0090, 0x6109b4 },
|
||||
{ 0x0094, 0x610970 },
|
||||
{ 0x00a0, 0x610998 },
|
||||
{ 0x00a4, 0x610964 },
|
||||
{ 0x00c0, 0x610958 },
|
||||
{ 0x00e0, 0x6109a8 },
|
||||
{ 0x00e4, 0x6109d0 },
|
||||
{ 0x00e8, 0x6109d8 },
|
||||
{ 0x0100, 0x61094c },
|
||||
{ 0x0104, 0x610984 },
|
||||
{ 0x0108, 0x61098c },
|
||||
{ 0x0800, 0x6109f8 },
|
||||
{ 0x0808, 0x610a08 },
|
||||
{ 0x080c, 0x610a10 },
|
||||
{ 0x0810, 0x610a00 },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
const struct nv50_disp_mthd_chan
|
||||
nv50_disp_ovly_mthd_chan = {
|
||||
.name = "Overlay",
|
||||
.addr = 0x000540,
|
||||
.data = {
|
||||
{ "Global", 1, &nv50_disp_ovly_mthd_base },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
int
|
||||
nv50_disp_ovly_ctor(struct nvkm_object *parent,
|
||||
struct nvkm_object *engine,
|
||||
struct nvkm_oclass *oclass, void *data, u32 size,
|
||||
struct nvkm_object **pobject)
|
||||
{
|
||||
union {
|
||||
struct nv50_disp_overlay_channel_dma_v0 v0;
|
||||
} *args = data;
|
||||
struct nv50_disp *disp = (void *)engine;
|
||||
struct nv50_disp_dmac *dmac;
|
||||
int ret;
|
||||
|
||||
nvif_ioctl(parent, "create disp overlay channel dma size %d\n", size);
|
||||
if (nvif_unpack(args->v0, 0, 0, false)) {
|
||||
nvif_ioctl(parent, "create disp overlay channel dma vers %d "
|
||||
"pushbuf %016llx head %d\n",
|
||||
args->v0.version, args->v0.pushbuf, args->v0.head);
|
||||
if (args->v0.head > disp->head.nr)
|
||||
return -EINVAL;
|
||||
} else
|
||||
return ret;
|
||||
|
||||
ret = nv50_disp_dmac_create_(parent, engine, oclass, args->v0.pushbuf,
|
||||
args->v0.head, sizeof(*dmac),
|
||||
(void **)&dmac);
|
||||
*pobject = nv_object(dmac);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct nv50_disp_chan_impl
|
||||
nv50_disp_ovly_ofuncs = {
|
||||
.base.ctor = nv50_disp_ovly_ctor,
|
||||
.base.dtor = nv50_disp_dmac_dtor,
|
||||
.base.init = nv50_disp_dmac_init,
|
||||
.base.fini = nv50_disp_dmac_fini,
|
||||
.base.ntfy = nv50_disp_chan_ntfy,
|
||||
.base.map = nv50_disp_chan_map,
|
||||
.base.rd32 = nv50_disp_chan_rd32,
|
||||
.base.wr32 = nv50_disp_chan_wr32,
|
||||
.chid = 3,
|
||||
.attach = nv50_disp_dmac_object_attach,
|
||||
.detach = nv50_disp_dmac_object_detach,
|
||||
};
|
|
@ -0,0 +1,85 @@
|
|||
/*
|
||||
* Copyright 2012 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "channv50.h"
|
||||
|
||||
#include <subdev/timer.h>
|
||||
|
||||
int
|
||||
gf119_disp_pioc_fini(struct nvkm_object *object, bool suspend)
|
||||
{
|
||||
struct nv50_disp *disp = (void *)object->engine;
|
||||
struct nv50_disp_pioc *pioc = (void *)object;
|
||||
struct nvkm_subdev *subdev = &disp->base.engine.subdev;
|
||||
struct nvkm_device *device = subdev->device;
|
||||
int chid = pioc->base.chid;
|
||||
|
||||
nvkm_mask(device, 0x610490 + (chid * 0x10), 0x00000001, 0x00000000);
|
||||
if (nvkm_msec(device, 2000,
|
||||
if (!(nvkm_rd32(device, 0x610490 + (chid * 0x10)) & 0x00030000))
|
||||
break;
|
||||
) < 0) {
|
||||
nvkm_error(subdev, "ch %d fini: %08x\n", chid,
|
||||
nvkm_rd32(device, 0x610490 + (chid * 0x10)));
|
||||
if (suspend)
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
/* disable error reporting and completion notification */
|
||||
nvkm_mask(device, 0x610090, 0x00000001 << chid, 0x00000000);
|
||||
nvkm_mask(device, 0x6100a0, 0x00000001 << chid, 0x00000000);
|
||||
|
||||
return nv50_disp_chan_fini(&pioc->base, suspend);
|
||||
}
|
||||
|
||||
int
|
||||
gf119_disp_pioc_init(struct nvkm_object *object)
|
||||
{
|
||||
struct nv50_disp *disp = (void *)object->engine;
|
||||
struct nv50_disp_pioc *pioc = (void *)object;
|
||||
struct nvkm_subdev *subdev = &disp->base.engine.subdev;
|
||||
struct nvkm_device *device = subdev->device;
|
||||
int chid = pioc->base.chid;
|
||||
int ret;
|
||||
|
||||
ret = nv50_disp_chan_init(&pioc->base);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* enable error reporting */
|
||||
nvkm_mask(device, 0x6100a0, 0x00000001 << chid, 0x00000001 << chid);
|
||||
|
||||
/* activate channel */
|
||||
nvkm_wr32(device, 0x610490 + (chid * 0x10), 0x00000001);
|
||||
if (nvkm_msec(device, 2000,
|
||||
u32 tmp = nvkm_rd32(device, 0x610490 + (chid * 0x10));
|
||||
if ((tmp & 0x00030000) == 0x00010000)
|
||||
break;
|
||||
) < 0) {
|
||||
nvkm_error(subdev, "ch %d init: %08x\n", chid,
|
||||
nvkm_rd32(device, 0x610490 + (chid * 0x10)));
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
|
@ -0,0 +1,104 @@
|
|||
/*
|
||||
* Copyright 2012 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "channv50.h"
|
||||
|
||||
#include <subdev/timer.h>
|
||||
|
||||
int
|
||||
nv50_disp_pioc_fini(struct nvkm_object *object, bool suspend)
|
||||
{
|
||||
struct nv50_disp *disp = (void *)object->engine;
|
||||
struct nv50_disp_pioc *pioc = (void *)object;
|
||||
struct nvkm_subdev *subdev = &disp->base.engine.subdev;
|
||||
struct nvkm_device *device = subdev->device;
|
||||
int chid = pioc->base.chid;
|
||||
|
||||
nvkm_mask(device, 0x610200 + (chid * 0x10), 0x00000001, 0x00000000);
|
||||
if (nvkm_msec(device, 2000,
|
||||
if (!(nvkm_rd32(device, 0x610200 + (chid * 0x10)) & 0x00030000))
|
||||
break;
|
||||
) < 0) {
|
||||
nvkm_error(subdev, "ch %d timeout: %08x\n", chid,
|
||||
nvkm_rd32(device, 0x610200 + (chid * 0x10)));
|
||||
if (suspend)
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
return nv50_disp_chan_fini(&pioc->base, suspend);
|
||||
}
|
||||
|
||||
int
|
||||
nv50_disp_pioc_init(struct nvkm_object *object)
|
||||
{
|
||||
struct nv50_disp *disp = (void *)object->engine;
|
||||
struct nv50_disp_pioc *pioc = (void *)object;
|
||||
struct nvkm_subdev *subdev = &disp->base.engine.subdev;
|
||||
struct nvkm_device *device = subdev->device;
|
||||
int chid = pioc->base.chid;
|
||||
int ret;
|
||||
|
||||
ret = nv50_disp_chan_init(&pioc->base);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
nvkm_wr32(device, 0x610200 + (chid * 0x10), 0x00002000);
|
||||
if (nvkm_msec(device, 2000,
|
||||
if (!(nvkm_rd32(device, 0x610200 + (chid * 0x10)) & 0x00030000))
|
||||
break;
|
||||
) < 0) {
|
||||
nvkm_error(subdev, "ch %d timeout0: %08x\n", chid,
|
||||
nvkm_rd32(device, 0x610200 + (chid * 0x10)));
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
nvkm_wr32(device, 0x610200 + (chid * 0x10), 0x00000001);
|
||||
if (nvkm_msec(device, 2000,
|
||||
u32 tmp = nvkm_rd32(device, 0x610200 + (chid * 0x10));
|
||||
if ((tmp & 0x00030000) == 0x00010000)
|
||||
break;
|
||||
) < 0) {
|
||||
nvkm_error(subdev, "ch %d timeout1: %08x\n", chid,
|
||||
nvkm_rd32(device, 0x610200 + (chid * 0x10)));
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void
|
||||
nv50_disp_pioc_dtor(struct nvkm_object *object)
|
||||
{
|
||||
struct nv50_disp_pioc *pioc = (void *)object;
|
||||
nv50_disp_chan_destroy(&pioc->base);
|
||||
}
|
||||
|
||||
int
|
||||
nv50_disp_pioc_create_(struct nvkm_object *parent,
|
||||
struct nvkm_object *engine,
|
||||
struct nvkm_oclass *oclass, int head,
|
||||
int length, void **pobject)
|
||||
{
|
||||
return nv50_disp_chan_create_(parent, engine, oclass, head,
|
||||
length, pobject);
|
||||
}
|
|
@ -56,4 +56,6 @@ int nvkm_disp_vblank_ctor(struct nvkm_object *, void *data, u32 size,
|
|||
struct nvkm_notify *);
|
||||
void nvkm_disp_vblank(struct nvkm_disp *, int head);
|
||||
int nvkm_disp_ntfy(struct nvkm_object *, u32, struct nvkm_event **);
|
||||
|
||||
extern struct nvkm_oclass nv04_disp_sclass[];
|
||||
#endif
|
||||
|
|
|
@ -0,0 +1,43 @@
|
|||
/*
|
||||
* Copyright 2012 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "rootnv50.h"
|
||||
#include "dmacnv50.h"
|
||||
|
||||
#include <nvif/class.h>
|
||||
|
||||
struct nvkm_oclass
|
||||
g84_disp_sclass[] = {
|
||||
{ G82_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
|
||||
{ G82_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
|
||||
{ G82_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
|
||||
{ G82_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
|
||||
{ G82_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
|
||||
{}
|
||||
};
|
||||
|
||||
struct nvkm_oclass
|
||||
g84_disp_root_oclass[] = {
|
||||
{ G82_DISP, &nv50_disp_root_ofuncs },
|
||||
{}
|
||||
};
|
|
@ -0,0 +1,43 @@
|
|||
/*
|
||||
* Copyright 2012 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "rootnv50.h"
|
||||
#include "dmacnv50.h"
|
||||
|
||||
#include <nvif/class.h>
|
||||
|
||||
struct nvkm_oclass
|
||||
g94_disp_sclass[] = {
|
||||
{ GT206_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
|
||||
{ GT200_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
|
||||
{ GT200_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
|
||||
{ G82_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
|
||||
{ G82_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
|
||||
{}
|
||||
};
|
||||
|
||||
struct nvkm_oclass
|
||||
g94_disp_root_oclass[] = {
|
||||
{ GT206_DISP, &nv50_disp_root_ofuncs },
|
||||
{}
|
||||
};
|
|
@ -0,0 +1,176 @@
|
|||
/*
|
||||
* Copyright 2012 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "rootnv50.h"
|
||||
#include "dmacnv50.h"
|
||||
|
||||
#include <core/client.h>
|
||||
#include <core/ramht.h>
|
||||
#include <subdev/timer.h>
|
||||
|
||||
#include <nvif/class.h>
|
||||
#include <nvif/unpack.h>
|
||||
|
||||
int
|
||||
gf119_disp_root_scanoutpos(NV50_DISP_MTHD_V0)
|
||||
{
|
||||
struct nvkm_device *device = disp->base.engine.subdev.device;
|
||||
const u32 total = nvkm_rd32(device, 0x640414 + (head * 0x300));
|
||||
const u32 blanke = nvkm_rd32(device, 0x64041c + (head * 0x300));
|
||||
const u32 blanks = nvkm_rd32(device, 0x640420 + (head * 0x300));
|
||||
union {
|
||||
struct nv04_disp_scanoutpos_v0 v0;
|
||||
} *args = data;
|
||||
int ret;
|
||||
|
||||
nvif_ioctl(object, "disp scanoutpos size %d\n", size);
|
||||
if (nvif_unpack(args->v0, 0, 0, false)) {
|
||||
nvif_ioctl(object, "disp scanoutpos vers %d\n",
|
||||
args->v0.version);
|
||||
args->v0.vblanke = (blanke & 0xffff0000) >> 16;
|
||||
args->v0.hblanke = (blanke & 0x0000ffff);
|
||||
args->v0.vblanks = (blanks & 0xffff0000) >> 16;
|
||||
args->v0.hblanks = (blanks & 0x0000ffff);
|
||||
args->v0.vtotal = ( total & 0xffff0000) >> 16;
|
||||
args->v0.htotal = ( total & 0x0000ffff);
|
||||
args->v0.time[0] = ktime_to_ns(ktime_get());
|
||||
args->v0.vline = /* vline read locks hline */
|
||||
nvkm_rd32(device, 0x616340 + (head * 0x800)) & 0xffff;
|
||||
args->v0.time[1] = ktime_to_ns(ktime_get());
|
||||
args->v0.hline =
|
||||
nvkm_rd32(device, 0x616344 + (head * 0x800)) & 0xffff;
|
||||
} else
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
gf119_disp_root_init(struct nvkm_object *object)
|
||||
{
|
||||
struct nv50_disp *disp = (void *)object->engine;
|
||||
struct nv50_disp_root *root = (void *)object;
|
||||
struct nvkm_device *device = disp->base.engine.subdev.device;
|
||||
int ret, i;
|
||||
u32 tmp;
|
||||
|
||||
ret = nvkm_parent_init(&root->base);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* The below segments of code copying values from one register to
|
||||
* another appear to inform EVO of the display capabilities or
|
||||
* something similar.
|
||||
*/
|
||||
|
||||
/* ... CRTC caps */
|
||||
for (i = 0; i < disp->head.nr; i++) {
|
||||
tmp = nvkm_rd32(device, 0x616104 + (i * 0x800));
|
||||
nvkm_wr32(device, 0x6101b4 + (i * 0x800), tmp);
|
||||
tmp = nvkm_rd32(device, 0x616108 + (i * 0x800));
|
||||
nvkm_wr32(device, 0x6101b8 + (i * 0x800), tmp);
|
||||
tmp = nvkm_rd32(device, 0x61610c + (i * 0x800));
|
||||
nvkm_wr32(device, 0x6101bc + (i * 0x800), tmp);
|
||||
}
|
||||
|
||||
/* ... DAC caps */
|
||||
for (i = 0; i < disp->dac.nr; i++) {
|
||||
tmp = nvkm_rd32(device, 0x61a000 + (i * 0x800));
|
||||
nvkm_wr32(device, 0x6101c0 + (i * 0x800), tmp);
|
||||
}
|
||||
|
||||
/* ... SOR caps */
|
||||
for (i = 0; i < disp->sor.nr; i++) {
|
||||
tmp = nvkm_rd32(device, 0x61c000 + (i * 0x800));
|
||||
nvkm_wr32(device, 0x6301c4 + (i * 0x800), tmp);
|
||||
}
|
||||
|
||||
/* steal display away from vbios, or something like that */
|
||||
if (nvkm_rd32(device, 0x6100ac) & 0x00000100) {
|
||||
nvkm_wr32(device, 0x6100ac, 0x00000100);
|
||||
nvkm_mask(device, 0x6194e8, 0x00000001, 0x00000000);
|
||||
if (nvkm_msec(device, 2000,
|
||||
if (!(nvkm_rd32(device, 0x6194e8) & 0x00000002))
|
||||
break;
|
||||
) < 0)
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
/* point at display engine memory area (hash table, objects) */
|
||||
nvkm_wr32(device, 0x610010, (nv_gpuobj(object->parent)->addr >> 8) | 9);
|
||||
|
||||
/* enable supervisor interrupts, disable everything else */
|
||||
nvkm_wr32(device, 0x610090, 0x00000000);
|
||||
nvkm_wr32(device, 0x6100a0, 0x00000000);
|
||||
nvkm_wr32(device, 0x6100b0, 0x00000307);
|
||||
|
||||
/* disable underflow reporting, preventing an intermittent issue
|
||||
* on some gk104 boards where the production vbios left this
|
||||
* setting enabled by default.
|
||||
*
|
||||
* ftp://download.nvidia.com/open-gpu-doc/gk104-disable-underflow-reporting/1/gk104-disable-underflow-reporting.txt
|
||||
*/
|
||||
for (i = 0; i < disp->head.nr; i++)
|
||||
nvkm_mask(device, 0x616308 + (i * 0x800), 0x00000111, 0x00000010);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
gf119_disp_root_fini(struct nvkm_object *object, bool suspend)
|
||||
{
|
||||
struct nv50_disp *disp = (void *)object->engine;
|
||||
struct nv50_disp_root *root = (void *)object;
|
||||
struct nvkm_device *device = disp->base.engine.subdev.device;
|
||||
|
||||
/* disable all interrupts */
|
||||
nvkm_wr32(device, 0x6100b0, 0x00000000);
|
||||
|
||||
return nvkm_parent_fini(&root->base, suspend);
|
||||
}
|
||||
|
||||
struct nvkm_ofuncs
|
||||
gf119_disp_root_ofuncs = {
|
||||
.ctor = nv50_disp_root_ctor,
|
||||
.dtor = nv50_disp_root_dtor,
|
||||
.init = gf119_disp_root_init,
|
||||
.fini = gf119_disp_root_fini,
|
||||
.mthd = nv50_disp_root_mthd,
|
||||
.ntfy = nvkm_disp_ntfy,
|
||||
};
|
||||
|
||||
struct nvkm_oclass
|
||||
gf119_disp_root_oclass[] = {
|
||||
{ GF110_DISP, &gf119_disp_root_ofuncs },
|
||||
{}
|
||||
};
|
||||
|
||||
struct nvkm_oclass
|
||||
gf119_disp_sclass[] = {
|
||||
{ GF110_DISP_CORE_CHANNEL_DMA, &gf119_disp_core_ofuncs.base },
|
||||
{ GF110_DISP_BASE_CHANNEL_DMA, &gf119_disp_base_ofuncs.base },
|
||||
{ GF110_DISP_OVERLAY_CONTROL_DMA, &gf119_disp_ovly_ofuncs.base },
|
||||
{ GF110_DISP_OVERLAY, &gf119_disp_oimm_ofuncs.base },
|
||||
{ GF110_DISP_CURSOR, &gf119_disp_curs_ofuncs.base },
|
||||
{}
|
||||
};
|
|
@ -0,0 +1,43 @@
|
|||
/*
|
||||
* Copyright 2012 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "rootnv50.h"
|
||||
#include "dmacnv50.h"
|
||||
|
||||
#include <nvif/class.h>
|
||||
|
||||
struct nvkm_oclass
|
||||
gk104_disp_sclass[] = {
|
||||
{ GK104_DISP_CORE_CHANNEL_DMA, &gf119_disp_core_ofuncs.base },
|
||||
{ GK104_DISP_BASE_CHANNEL_DMA, &gf119_disp_base_ofuncs.base },
|
||||
{ GK104_DISP_OVERLAY_CONTROL_DMA, &gf119_disp_ovly_ofuncs.base },
|
||||
{ GK104_DISP_OVERLAY, &gf119_disp_oimm_ofuncs.base },
|
||||
{ GK104_DISP_CURSOR, &gf119_disp_curs_ofuncs.base },
|
||||
{}
|
||||
};
|
||||
|
||||
struct nvkm_oclass
|
||||
gk104_disp_root_oclass[] = {
|
||||
{ GK104_DISP, &gf119_disp_root_ofuncs },
|
||||
{}
|
||||
};
|
|
@ -0,0 +1,43 @@
|
|||
/*
|
||||
* Copyright 2012 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "rootnv50.h"
|
||||
#include "dmacnv50.h"
|
||||
|
||||
#include <nvif/class.h>
|
||||
|
||||
struct nvkm_oclass
|
||||
gk110_disp_sclass[] = {
|
||||
{ GK110_DISP_CORE_CHANNEL_DMA, &gf119_disp_core_ofuncs.base },
|
||||
{ GK110_DISP_BASE_CHANNEL_DMA, &gf119_disp_base_ofuncs.base },
|
||||
{ GK104_DISP_OVERLAY_CONTROL_DMA, &gf119_disp_ovly_ofuncs.base },
|
||||
{ GK104_DISP_OVERLAY, &gf119_disp_oimm_ofuncs.base },
|
||||
{ GK104_DISP_CURSOR, &gf119_disp_curs_ofuncs.base },
|
||||
{}
|
||||
};
|
||||
|
||||
struct nvkm_oclass
|
||||
gk110_disp_root_oclass[] = {
|
||||
{ GK110_DISP, &gf119_disp_root_ofuncs },
|
||||
{}
|
||||
};
|
|
@ -0,0 +1,43 @@
|
|||
/*
|
||||
* Copyright 2012 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "rootnv50.h"
|
||||
#include "dmacnv50.h"
|
||||
|
||||
#include <nvif/class.h>
|
||||
|
||||
struct nvkm_oclass
|
||||
gm107_disp_sclass[] = {
|
||||
{ GM107_DISP_CORE_CHANNEL_DMA, &gf119_disp_core_ofuncs.base },
|
||||
{ GK110_DISP_BASE_CHANNEL_DMA, &gf119_disp_base_ofuncs.base },
|
||||
{ GK104_DISP_OVERLAY_CONTROL_DMA, &gf119_disp_ovly_ofuncs.base },
|
||||
{ GK104_DISP_OVERLAY, &gf119_disp_oimm_ofuncs.base },
|
||||
{ GK104_DISP_CURSOR, &gf119_disp_curs_ofuncs.base },
|
||||
{}
|
||||
};
|
||||
|
||||
struct nvkm_oclass
|
||||
gm107_disp_root_oclass[] = {
|
||||
{ GM107_DISP, &gf119_disp_root_ofuncs },
|
||||
{}
|
||||
};
|
|
@ -0,0 +1,43 @@
|
|||
/*
|
||||
* Copyright 2012 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "rootnv50.h"
|
||||
#include "dmacnv50.h"
|
||||
|
||||
#include <nvif/class.h>
|
||||
|
||||
struct nvkm_oclass
|
||||
gm204_disp_sclass[] = {
|
||||
{ GM204_DISP_CORE_CHANNEL_DMA, &gf119_disp_core_ofuncs.base },
|
||||
{ GK110_DISP_BASE_CHANNEL_DMA, &gf119_disp_base_ofuncs.base },
|
||||
{ GK104_DISP_OVERLAY_CONTROL_DMA, &gf119_disp_ovly_ofuncs.base },
|
||||
{ GK104_DISP_OVERLAY, &gf119_disp_oimm_ofuncs.base },
|
||||
{ GK104_DISP_CURSOR, &gf119_disp_curs_ofuncs.base },
|
||||
{}
|
||||
};
|
||||
|
||||
struct nvkm_oclass
|
||||
gm204_disp_root_oclass[] = {
|
||||
{ GM204_DISP, &gf119_disp_root_ofuncs },
|
||||
{}
|
||||
};
|
|
@ -0,0 +1,43 @@
|
|||
/*
|
||||
* Copyright 2012 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "rootnv50.h"
|
||||
#include "dmacnv50.h"
|
||||
|
||||
#include <nvif/class.h>
|
||||
|
||||
struct nvkm_oclass
|
||||
gt200_disp_sclass[] = {
|
||||
{ GT200_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
|
||||
{ GT200_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
|
||||
{ GT200_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
|
||||
{ G82_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
|
||||
{ G82_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
|
||||
{}
|
||||
};
|
||||
|
||||
struct nvkm_oclass
|
||||
gt200_disp_root_oclass[] = {
|
||||
{ GT200_DISP, &nv50_disp_root_ofuncs },
|
||||
{}
|
||||
};
|
|
@ -0,0 +1,43 @@
|
|||
/*
|
||||
* Copyright 2012 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "rootnv50.h"
|
||||
#include "dmacnv50.h"
|
||||
|
||||
#include <nvif/class.h>
|
||||
|
||||
struct nvkm_oclass
|
||||
gt215_disp_sclass[] = {
|
||||
{ GT214_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
|
||||
{ GT214_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
|
||||
{ GT214_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
|
||||
{ GT214_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
|
||||
{ GT214_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
|
||||
{}
|
||||
};
|
||||
|
||||
struct nvkm_oclass
|
||||
gt215_disp_root_oclass[] = {
|
||||
{ GT214_DISP, &nv50_disp_root_ofuncs },
|
||||
{}
|
||||
};
|
|
@ -0,0 +1,119 @@
|
|||
/*
|
||||
* Copyright 2012 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "priv.h"
|
||||
|
||||
#include <core/client.h>
|
||||
|
||||
#include <nvif/class.h>
|
||||
#include <nvif/unpack.h>
|
||||
|
||||
static int
|
||||
nv04_disp_scanoutpos(struct nvkm_object *object, struct nvkm_disp *disp,
|
||||
void *data, u32 size, int head)
|
||||
{
|
||||
struct nvkm_device *device = disp->engine.subdev.device;
|
||||
const u32 hoff = head * 0x2000;
|
||||
union {
|
||||
struct nv04_disp_scanoutpos_v0 v0;
|
||||
} *args = data;
|
||||
u32 line;
|
||||
int ret;
|
||||
|
||||
nvif_ioctl(object, "disp scanoutpos size %d\n", size);
|
||||
if (nvif_unpack(args->v0, 0, 0, false)) {
|
||||
nvif_ioctl(object, "disp scanoutpos vers %d\n",
|
||||
args->v0.version);
|
||||
args->v0.vblanks = nvkm_rd32(device, 0x680800 + hoff) & 0xffff;
|
||||
args->v0.vtotal = nvkm_rd32(device, 0x680804 + hoff) & 0xffff;
|
||||
args->v0.vblanke = args->v0.vtotal - 1;
|
||||
|
||||
args->v0.hblanks = nvkm_rd32(device, 0x680820 + hoff) & 0xffff;
|
||||
args->v0.htotal = nvkm_rd32(device, 0x680824 + hoff) & 0xffff;
|
||||
args->v0.hblanke = args->v0.htotal - 1;
|
||||
|
||||
/*
|
||||
* If output is vga instead of digital then vtotal/htotal is
|
||||
* invalid so we have to give up and trigger the timestamping
|
||||
* fallback in the drm core.
|
||||
*/
|
||||
if (!args->v0.vtotal || !args->v0.htotal)
|
||||
return -ENOTSUPP;
|
||||
|
||||
args->v0.time[0] = ktime_to_ns(ktime_get());
|
||||
line = nvkm_rd32(device, 0x600868 + hoff);
|
||||
args->v0.time[1] = ktime_to_ns(ktime_get());
|
||||
args->v0.hline = (line & 0xffff0000) >> 16;
|
||||
args->v0.vline = (line & 0x0000ffff);
|
||||
} else
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
nv04_disp_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size)
|
||||
{
|
||||
union {
|
||||
struct nv04_disp_mthd_v0 v0;
|
||||
} *args = data;
|
||||
struct nvkm_disp *disp = (void *)object->engine;
|
||||
int head, ret;
|
||||
|
||||
nvif_ioctl(object, "disp mthd size %d\n", size);
|
||||
if (nvif_unpack(args->v0, 0, 0, true)) {
|
||||
nvif_ioctl(object, "disp mthd vers %d mthd %02x head %d\n",
|
||||
args->v0.version, args->v0.method, args->v0.head);
|
||||
mthd = args->v0.method;
|
||||
head = args->v0.head;
|
||||
} else
|
||||
return ret;
|
||||
|
||||
if (head < 0 || head >= 2)
|
||||
return -ENXIO;
|
||||
|
||||
switch (mthd) {
|
||||
case NV04_DISP_SCANOUTPOS:
|
||||
return nv04_disp_scanoutpos(object, disp, data, size, head);
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static struct nvkm_ofuncs
|
||||
nv04_disp_ofuncs = {
|
||||
.ctor = _nvkm_object_ctor,
|
||||
.dtor = nvkm_object_destroy,
|
||||
.init = _nvkm_object_init,
|
||||
.fini = _nvkm_object_fini,
|
||||
.mthd = nv04_disp_mthd,
|
||||
.ntfy = nvkm_disp_ntfy,
|
||||
};
|
||||
|
||||
struct nvkm_oclass
|
||||
nv04_disp_sclass[] = {
|
||||
{ NV04_DISP, &nv04_disp_ofuncs },
|
||||
{},
|
||||
};
|
|
@ -0,0 +1,328 @@
|
|||
/*
|
||||
* Copyright 2012 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "rootnv50.h"
|
||||
#include "dmacnv50.h"
|
||||
|
||||
#include <core/client.h>
|
||||
#include <core/ramht.h>
|
||||
#include <subdev/timer.h>
|
||||
|
||||
#include <nvif/class.h>
|
||||
#include <nvif/unpack.h>
|
||||
|
||||
int
|
||||
nv50_disp_root_scanoutpos(NV50_DISP_MTHD_V0)
|
||||
{
|
||||
struct nvkm_device *device = disp->base.engine.subdev.device;
|
||||
const u32 blanke = nvkm_rd32(device, 0x610aec + (head * 0x540));
|
||||
const u32 blanks = nvkm_rd32(device, 0x610af4 + (head * 0x540));
|
||||
const u32 total = nvkm_rd32(device, 0x610afc + (head * 0x540));
|
||||
union {
|
||||
struct nv04_disp_scanoutpos_v0 v0;
|
||||
} *args = data;
|
||||
int ret;
|
||||
|
||||
nvif_ioctl(object, "disp scanoutpos size %d\n", size);
|
||||
if (nvif_unpack(args->v0, 0, 0, false)) {
|
||||
nvif_ioctl(object, "disp scanoutpos vers %d\n",
|
||||
args->v0.version);
|
||||
args->v0.vblanke = (blanke & 0xffff0000) >> 16;
|
||||
args->v0.hblanke = (blanke & 0x0000ffff);
|
||||
args->v0.vblanks = (blanks & 0xffff0000) >> 16;
|
||||
args->v0.hblanks = (blanks & 0x0000ffff);
|
||||
args->v0.vtotal = ( total & 0xffff0000) >> 16;
|
||||
args->v0.htotal = ( total & 0x0000ffff);
|
||||
args->v0.time[0] = ktime_to_ns(ktime_get());
|
||||
args->v0.vline = /* vline read locks hline */
|
||||
nvkm_rd32(device, 0x616340 + (head * 0x800)) & 0xffff;
|
||||
args->v0.time[1] = ktime_to_ns(ktime_get());
|
||||
args->v0.hline =
|
||||
nvkm_rd32(device, 0x616344 + (head * 0x800)) & 0xffff;
|
||||
} else
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
nv50_disp_root_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size)
|
||||
{
|
||||
const struct nv50_disp_impl *impl = (void *)nv_oclass(object->engine);
|
||||
union {
|
||||
struct nv50_disp_mthd_v0 v0;
|
||||
struct nv50_disp_mthd_v1 v1;
|
||||
} *args = data;
|
||||
struct nv50_disp *disp = (void *)object->engine;
|
||||
struct nvkm_output *outp = NULL;
|
||||
struct nvkm_output *temp;
|
||||
u16 type, mask = 0;
|
||||
int head, ret;
|
||||
|
||||
if (mthd != NV50_DISP_MTHD)
|
||||
return -EINVAL;
|
||||
|
||||
nvif_ioctl(object, "disp mthd size %d\n", size);
|
||||
if (nvif_unpack(args->v0, 0, 0, true)) {
|
||||
nvif_ioctl(object, "disp mthd vers %d mthd %02x head %d\n",
|
||||
args->v0.version, args->v0.method, args->v0.head);
|
||||
mthd = args->v0.method;
|
||||
head = args->v0.head;
|
||||
} else
|
||||
if (nvif_unpack(args->v1, 1, 1, true)) {
|
||||
nvif_ioctl(object, "disp mthd vers %d mthd %02x "
|
||||
"type %04x mask %04x\n",
|
||||
args->v1.version, args->v1.method,
|
||||
args->v1.hasht, args->v1.hashm);
|
||||
mthd = args->v1.method;
|
||||
type = args->v1.hasht;
|
||||
mask = args->v1.hashm;
|
||||
head = ffs((mask >> 8) & 0x0f) - 1;
|
||||
} else
|
||||
return ret;
|
||||
|
||||
if (head < 0 || head >= disp->head.nr)
|
||||
return -ENXIO;
|
||||
|
||||
if (mask) {
|
||||
list_for_each_entry(temp, &disp->base.outp, head) {
|
||||
if ((temp->info.hasht == type) &&
|
||||
(temp->info.hashm & mask) == mask) {
|
||||
outp = temp;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (outp == NULL)
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
switch (mthd) {
|
||||
case NV50_DISP_SCANOUTPOS:
|
||||
return impl->head.scanoutpos(object, disp, data, size, head);
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
switch (mthd * !!outp) {
|
||||
case NV50_DISP_MTHD_V1_DAC_PWR:
|
||||
return disp->dac.power(object, disp, data, size, head, outp);
|
||||
case NV50_DISP_MTHD_V1_DAC_LOAD:
|
||||
return disp->dac.sense(object, disp, data, size, head, outp);
|
||||
case NV50_DISP_MTHD_V1_SOR_PWR:
|
||||
return disp->sor.power(object, disp, data, size, head, outp);
|
||||
case NV50_DISP_MTHD_V1_SOR_HDA_ELD:
|
||||
if (!disp->sor.hda_eld)
|
||||
return -ENODEV;
|
||||
return disp->sor.hda_eld(object, disp, data, size, head, outp);
|
||||
case NV50_DISP_MTHD_V1_SOR_HDMI_PWR:
|
||||
if (!disp->sor.hdmi)
|
||||
return -ENODEV;
|
||||
return disp->sor.hdmi(object, disp, data, size, head, outp);
|
||||
case NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT: {
|
||||
union {
|
||||
struct nv50_disp_sor_lvds_script_v0 v0;
|
||||
} *args = data;
|
||||
nvif_ioctl(object, "disp sor lvds script size %d\n", size);
|
||||
if (nvif_unpack(args->v0, 0, 0, false)) {
|
||||
nvif_ioctl(object, "disp sor lvds script "
|
||||
"vers %d name %04x\n",
|
||||
args->v0.version, args->v0.script);
|
||||
disp->sor.lvdsconf = args->v0.script;
|
||||
return 0;
|
||||
} else
|
||||
return ret;
|
||||
}
|
||||
break;
|
||||
case NV50_DISP_MTHD_V1_SOR_DP_PWR: {
|
||||
struct nvkm_output_dp *outpdp = nvkm_output_dp(outp);
|
||||
union {
|
||||
struct nv50_disp_sor_dp_pwr_v0 v0;
|
||||
} *args = data;
|
||||
nvif_ioctl(object, "disp sor dp pwr size %d\n", size);
|
||||
if (nvif_unpack(args->v0, 0, 0, false)) {
|
||||
nvif_ioctl(object, "disp sor dp pwr vers %d state %d\n",
|
||||
args->v0.version, args->v0.state);
|
||||
if (args->v0.state == 0) {
|
||||
nvkm_notify_put(&outpdp->irq);
|
||||
outpdp->func->lnk_pwr(outpdp, 0);
|
||||
atomic_set(&outpdp->lt.done, 0);
|
||||
return 0;
|
||||
} else
|
||||
if (args->v0.state != 0) {
|
||||
nvkm_output_dp_train(&outpdp->base, 0, true);
|
||||
return 0;
|
||||
}
|
||||
} else
|
||||
return ret;
|
||||
}
|
||||
break;
|
||||
case NV50_DISP_MTHD_V1_PIOR_PWR:
|
||||
if (!disp->pior.power)
|
||||
return -ENODEV;
|
||||
return disp->pior.power(object, disp, data, size, head, outp);
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
int
|
||||
nv50_disp_root_ctor(struct nvkm_object *parent,
|
||||
struct nvkm_object *engine,
|
||||
struct nvkm_oclass *oclass, void *data, u32 size,
|
||||
struct nvkm_object **pobject)
|
||||
{
|
||||
struct nv50_disp *disp = (void *)engine;
|
||||
struct nv50_disp_root *root;
|
||||
struct nvkm_device *device = disp->base.engine.subdev.device;
|
||||
struct nvkm_gpuobj *instmem = (void *)parent;
|
||||
int ret;
|
||||
|
||||
ret = nvkm_parent_create(parent, engine, oclass, 0,
|
||||
disp->sclass, 0, &root);
|
||||
*pobject = nv_object(root);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
||||
return nvkm_ramht_new(device, 0x1000, 0, instmem, &root->ramht);
|
||||
}
|
||||
|
||||
void
|
||||
nv50_disp_root_dtor(struct nvkm_object *object)
|
||||
{
|
||||
struct nv50_disp_root *root = (void *)object;
|
||||
nvkm_ramht_del(&root->ramht);
|
||||
nvkm_parent_destroy(&root->base);
|
||||
}
|
||||
|
||||
static int
|
||||
nv50_disp_root_init(struct nvkm_object *object)
|
||||
{
|
||||
struct nv50_disp *disp = (void *)object->engine;
|
||||
struct nv50_disp_root *root = (void *)object;
|
||||
struct nvkm_device *device = disp->base.engine.subdev.device;
|
||||
int ret, i;
|
||||
u32 tmp;
|
||||
|
||||
ret = nvkm_parent_init(&root->base);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* The below segments of code copying values from one register to
|
||||
* another appear to inform EVO of the display capabilities or
|
||||
* something similar. NFI what the 0x614004 caps are for..
|
||||
*/
|
||||
tmp = nvkm_rd32(device, 0x614004);
|
||||
nvkm_wr32(device, 0x610184, tmp);
|
||||
|
||||
/* ... CRTC caps */
|
||||
for (i = 0; i < disp->head.nr; i++) {
|
||||
tmp = nvkm_rd32(device, 0x616100 + (i * 0x800));
|
||||
nvkm_wr32(device, 0x610190 + (i * 0x10), tmp);
|
||||
tmp = nvkm_rd32(device, 0x616104 + (i * 0x800));
|
||||
nvkm_wr32(device, 0x610194 + (i * 0x10), tmp);
|
||||
tmp = nvkm_rd32(device, 0x616108 + (i * 0x800));
|
||||
nvkm_wr32(device, 0x610198 + (i * 0x10), tmp);
|
||||
tmp = nvkm_rd32(device, 0x61610c + (i * 0x800));
|
||||
nvkm_wr32(device, 0x61019c + (i * 0x10), tmp);
|
||||
}
|
||||
|
||||
/* ... DAC caps */
|
||||
for (i = 0; i < disp->dac.nr; i++) {
|
||||
tmp = nvkm_rd32(device, 0x61a000 + (i * 0x800));
|
||||
nvkm_wr32(device, 0x6101d0 + (i * 0x04), tmp);
|
||||
}
|
||||
|
||||
/* ... SOR caps */
|
||||
for (i = 0; i < disp->sor.nr; i++) {
|
||||
tmp = nvkm_rd32(device, 0x61c000 + (i * 0x800));
|
||||
nvkm_wr32(device, 0x6101e0 + (i * 0x04), tmp);
|
||||
}
|
||||
|
||||
/* ... PIOR caps */
|
||||
for (i = 0; i < disp->pior.nr; i++) {
|
||||
tmp = nvkm_rd32(device, 0x61e000 + (i * 0x800));
|
||||
nvkm_wr32(device, 0x6101f0 + (i * 0x04), tmp);
|
||||
}
|
||||
|
||||
/* steal display away from vbios, or something like that */
|
||||
if (nvkm_rd32(device, 0x610024) & 0x00000100) {
|
||||
nvkm_wr32(device, 0x610024, 0x00000100);
|
||||
nvkm_mask(device, 0x6194e8, 0x00000001, 0x00000000);
|
||||
if (nvkm_msec(device, 2000,
|
||||
if (!(nvkm_rd32(device, 0x6194e8) & 0x00000002))
|
||||
break;
|
||||
) < 0)
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
/* point at display engine memory area (hash table, objects) */
|
||||
nvkm_wr32(device, 0x610010, (root->ramht->gpuobj->addr >> 8) | 9);
|
||||
|
||||
/* enable supervisor interrupts, disable everything else */
|
||||
nvkm_wr32(device, 0x61002c, 0x00000370);
|
||||
nvkm_wr32(device, 0x610028, 0x00000000);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
nv50_disp_root_fini(struct nvkm_object *object, bool suspend)
|
||||
{
|
||||
struct nv50_disp *disp = (void *)object->engine;
|
||||
struct nv50_disp_root *root = (void *)object;
|
||||
struct nvkm_device *device = disp->base.engine.subdev.device;
|
||||
|
||||
/* disable all interrupts */
|
||||
nvkm_wr32(device, 0x610024, 0x00000000);
|
||||
nvkm_wr32(device, 0x610020, 0x00000000);
|
||||
|
||||
return nvkm_parent_fini(&root->base, suspend);
|
||||
}
|
||||
|
||||
struct nvkm_ofuncs
|
||||
nv50_disp_root_ofuncs = {
|
||||
.ctor = nv50_disp_root_ctor,
|
||||
.dtor = nv50_disp_root_dtor,
|
||||
.init = nv50_disp_root_init,
|
||||
.fini = nv50_disp_root_fini,
|
||||
.mthd = nv50_disp_root_mthd,
|
||||
.ntfy = nvkm_disp_ntfy,
|
||||
};
|
||||
|
||||
struct nvkm_oclass
|
||||
nv50_disp_root_oclass[] = {
|
||||
{ NV50_DISP, &nv50_disp_root_ofuncs },
|
||||
{}
|
||||
};
|
||||
|
||||
struct nvkm_oclass
|
||||
nv50_disp_sclass[] = {
|
||||
{ NV50_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
|
||||
{ NV50_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
|
||||
{ NV50_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
|
||||
{ NV50_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
|
||||
{ NV50_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
|
||||
{}
|
||||
};
|
|
@ -0,0 +1,36 @@
|
|||
#ifndef __NV50_DISP_ROOT_H__
|
||||
#define __NV50_DISP_ROOT_H__
|
||||
#include "nv50.h"
|
||||
#include "channv50.h"
|
||||
#include "dmacnv50.h"
|
||||
#include <core/parent.h>
|
||||
|
||||
#include <nvif/class.h>
|
||||
|
||||
struct nv50_disp_root {
|
||||
struct nvkm_parent base;
|
||||
struct nvkm_ramht *ramht;
|
||||
u32 chan;
|
||||
};
|
||||
|
||||
extern struct nvkm_oclass nv50_disp_root_oclass[];
|
||||
extern struct nvkm_oclass nv50_disp_sclass[];
|
||||
extern struct nvkm_oclass g84_disp_root_oclass[];
|
||||
extern struct nvkm_oclass g84_disp_sclass[];
|
||||
extern struct nvkm_oclass g94_disp_root_oclass[];
|
||||
extern struct nvkm_oclass g94_disp_sclass[];
|
||||
extern struct nvkm_oclass gt200_disp_root_oclass[];
|
||||
extern struct nvkm_oclass gt200_disp_sclass[];
|
||||
extern struct nvkm_oclass gt215_disp_root_oclass[];
|
||||
extern struct nvkm_oclass gt215_disp_sclass[];
|
||||
extern struct nvkm_oclass gf119_disp_root_oclass[];
|
||||
extern struct nvkm_oclass gf119_disp_sclass[];
|
||||
extern struct nvkm_oclass gk104_disp_root_oclass[];
|
||||
extern struct nvkm_oclass gk104_disp_sclass[];
|
||||
extern struct nvkm_oclass gk110_disp_root_oclass[];
|
||||
extern struct nvkm_oclass gk110_disp_sclass[];
|
||||
extern struct nvkm_oclass gm107_disp_root_oclass[];
|
||||
extern struct nvkm_oclass gm107_disp_sclass[];
|
||||
extern struct nvkm_oclass gm204_disp_root_oclass[];
|
||||
extern struct nvkm_oclass gm204_disp_sclass[];
|
||||
#endif
|
|
@ -25,32 +25,32 @@
|
|||
#include "outpdp.h"
|
||||
|
||||
static inline u32
|
||||
gf110_sor_soff(struct nvkm_output_dp *outp)
|
||||
gf119_sor_soff(struct nvkm_output_dp *outp)
|
||||
{
|
||||
return (ffs(outp->base.info.or) - 1) * 0x800;
|
||||
}
|
||||
|
||||
static inline u32
|
||||
gf110_sor_loff(struct nvkm_output_dp *outp)
|
||||
gf119_sor_loff(struct nvkm_output_dp *outp)
|
||||
{
|
||||
return gf110_sor_soff(outp) + !(outp->base.info.sorconf.link & 1) * 0x80;
|
||||
return gf119_sor_soff(outp) + !(outp->base.info.sorconf.link & 1) * 0x80;
|
||||
}
|
||||
|
||||
static int
|
||||
gf110_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern)
|
||||
gf119_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern)
|
||||
{
|
||||
struct nvkm_device *device = outp->base.disp->engine.subdev.device;
|
||||
const u32 loff = gf110_sor_loff(outp);
|
||||
const u32 loff = gf119_sor_loff(outp);
|
||||
nvkm_mask(device, 0x61c110 + loff, 0x0f0f0f0f, 0x01010101 * pattern);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
gf110_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef)
|
||||
gf119_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef)
|
||||
{
|
||||
struct nvkm_device *device = outp->base.disp->engine.subdev.device;
|
||||
const u32 soff = gf110_sor_soff(outp);
|
||||
const u32 loff = gf110_sor_loff(outp);
|
||||
const u32 soff = gf119_sor_soff(outp);
|
||||
const u32 loff = gf119_sor_loff(outp);
|
||||
u32 dpctrl = 0x00000000;
|
||||
u32 clksor = 0x00000000;
|
||||
|
||||
|
@ -65,13 +65,13 @@ gf110_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef)
|
|||
}
|
||||
|
||||
static int
|
||||
gf110_sor_dp_drv_ctl(struct nvkm_output_dp *outp,
|
||||
gf119_sor_dp_drv_ctl(struct nvkm_output_dp *outp,
|
||||
int ln, int vs, int pe, int pc)
|
||||
{
|
||||
struct nvkm_device *device = outp->base.disp->engine.subdev.device;
|
||||
struct nvkm_bios *bios = device->bios;
|
||||
const u32 shift = g94_sor_dp_lane_map(device, ln);
|
||||
const u32 loff = gf110_sor_loff(outp);
|
||||
const u32 loff = gf119_sor_loff(outp);
|
||||
u32 addr, data[4];
|
||||
u8 ver, hdr, cnt, len;
|
||||
struct nvbios_dpout info;
|
||||
|
@ -102,16 +102,16 @@ gf110_sor_dp_drv_ctl(struct nvkm_output_dp *outp,
|
|||
}
|
||||
|
||||
static const struct nvkm_output_dp_func
|
||||
gf110_sor_dp_func = {
|
||||
.pattern = gf110_sor_dp_pattern,
|
||||
gf119_sor_dp_func = {
|
||||
.pattern = gf119_sor_dp_pattern,
|
||||
.lnk_pwr = g94_sor_dp_lnk_pwr,
|
||||
.lnk_ctl = gf110_sor_dp_lnk_ctl,
|
||||
.drv_ctl = gf110_sor_dp_drv_ctl,
|
||||
.lnk_ctl = gf119_sor_dp_lnk_ctl,
|
||||
.drv_ctl = gf119_sor_dp_drv_ctl,
|
||||
};
|
||||
|
||||
int
|
||||
gf110_sor_dp_new(struct nvkm_disp *disp, int index,
|
||||
gf119_sor_dp_new(struct nvkm_disp *disp, int index,
|
||||
struct dcb_output *dcbE, struct nvkm_output **poutp)
|
||||
{
|
||||
return nvkm_output_dp_new_(&gf110_sor_dp_func, disp, index, dcbE, poutp);
|
||||
return nvkm_output_dp_new_(&gf119_sor_dp_func, disp, index, dcbE, poutp);
|
||||
}
|
|
@ -131,7 +131,7 @@ static const struct nvkm_output_dp_func
|
|||
gm204_sor_dp_func = {
|
||||
.pattern = gm204_sor_dp_pattern,
|
||||
.lnk_pwr = gm204_sor_dp_lnk_pwr,
|
||||
.lnk_ctl = gf110_sor_dp_lnk_ctl,
|
||||
.lnk_ctl = gf119_sor_dp_lnk_ctl,
|
||||
.drv_ctl = gm204_sor_dp_drv_ctl,
|
||||
};
|
||||
|
||||
|
|
|
@ -73,12 +73,14 @@ static bool
|
|||
nv50_sw_chan_mthd(struct nvkm_sw_chan *base, int subc, u32 mthd, u32 data)
|
||||
{
|
||||
struct nv50_sw_chan *chan = nv50_sw_chan(base);
|
||||
struct nvkm_engine *engine = chan->base.base.gpuobj.object.engine;
|
||||
struct nvkm_device *device = engine->subdev.device;
|
||||
switch (mthd) {
|
||||
case 0x018c: chan->vblank.ctxdma = data; return true;
|
||||
case 0x0400: chan->vblank.offset = data; return true;
|
||||
case 0x0404: chan->vblank.value = data; return true;
|
||||
case 0x0408:
|
||||
if (data < nvkm_disp(chan)->vblank.index_nr) {
|
||||
if (data < device->disp->vblank.index_nr) {
|
||||
nvkm_notify_get(&chan->vblank.notify[data]);
|
||||
return true;
|
||||
}
|
||||
|
@ -111,7 +113,7 @@ nv50_sw_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
|||
struct nvkm_oclass *oclass, void *data, u32 size,
|
||||
struct nvkm_object **pobject)
|
||||
{
|
||||
struct nvkm_disp *disp = nvkm_disp(parent);
|
||||
struct nvkm_disp *disp = parent->engine->subdev.device->disp;
|
||||
struct nv50_sw_cclass *pclass = (void *)oclass;
|
||||
struct nv50_sw_chan *chan;
|
||||
int ret, i;
|
||||
|
|
Loading…
Reference in New Issue