mirror of https://gitee.com/openkylin/linux.git
Yaml conversion of grf, pmu and power-domain bindings,
Power-domains for rk3568 + necessary plumbing, Fixes for the usbphy bindings. -----BEGIN PGP SIGNATURE----- iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAmDO+jQQHGhlaWtvQHNu dGVjaC5kZQAKCRDzpnnJnNEdgYg1CACf0H/kkI9syxvF9eiUKL7lDmbY4gARrfcl lJTBU1HVeTIqi+yie09dGAEHFW8YE3xTVuCZ/Qe+N78F1PZQcRC9nCKMWb0n3CUL /Ba5D/jkKbVMY2VQng9vU1q+5BRbdRzHYlhvNAJAKaP5T3i1jc9oCnXrXLCc1I1G FbGtxZW5GgvUb+oMX9giKoJ25MorzQdsEt37QdOESgzD44xtf+BHid6pILf6yTxb DB7gynRsiSbZmzvBSIObnA4tM/MUSBCs2dIKqY8FEcv0+MPvd7wqD2H2ntAmVnfj nqUeT3jmpUO4VCpu2FB0htTj8/jJLAq26fXKJLlKzNkFSMBrAw2v =jW+J -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQJDBAABCgAtFiEElf+HevZ4QCAJmMQ+jBrnPN6EHHcFAmDT5sQPHG9sb2ZAbGl4 b20ubmV0AAoJEIwa5zzehBx3GuIP/2eaGTMjsBWGqj8PmgFZZLjs9wbvO9WNGtqJ 1dFlyNUNOliR27wK7X7NtA6a2njFN8nZMEMxSQOBa8JWSugWnKEFCPQsS1jhtRJ1 ip2WeCXDAsx5OTTOvikz8HUxXSvHQvcYnnrEtvwikWcI7m422tkqnqpkGbVV8Kux NkOq2bZO6tRzsqohOtjxswWStaLQKZfuZpTMuY5TkjSO7jGygoF56t1fnCN+iBRQ I6Nr3HOixYAlHYL14YHxcHzHe47MEp+hWJnl+Ghgx1WkR7YXuVBxSWExMbur1z5S kYsmIxEshToZH/TCmVPVIsPJoeJWDYpjknLo/6n81jA06gHGt33bRJd+FkS7NxYi HxZqYTtMcN+E5kU17xMm5aZLEKh62yrPYSGbx+jQ2tpbxNOEq+XJqCWdokONv2Rw CklzdYE1ZdN3W1U3loJQaDD3D3QOsCvxBv+apm0b4yWR15JZOWgTaMzHXHd3LcPe jMltZYSMGvDsrrEC3AxGUyiJabwKue6CVN100/eFOkJeGjbKSgRQwFAsgLLmZbcr gYNaubWBzIycds4bMn8CDPlI+ta+9MwRk8Yim4P/BtnXBekiYt6lur6TYRA/i83F PCtNlmlNs+oINCSYOKHvQGkbGZXK2CnErBPL3l/xdZYo91C2mBI73IESCumiO2R1 YohIFxzz =Qtie -----END PGP SIGNATURE----- Merge tag 'v5.14-rockchip-drivers1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/drivers Yaml conversion of grf, pmu and power-domain bindings, Power-domains for rk3568 + necessary plumbing, Fixes for the usbphy bindings. * tag 'v5.14-rockchip-drivers1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: dt-bindings: soc: rockchip: drop unnecessary #phy-cells from grf.yaml dt-bindings: soc: rockchip: grf: add compatible for RK3308 USB grf dt-bindings: phy: rename phy nodename in phy-rockchip-inno-usb2.yaml dt-bindings: soc: rockchip: convert grf.txt to YAML soc: rockchip: power-domain: add rk3568 powerdomains dt-bindings: power: rockchip: Add bindings for RK3568 Soc dt-bindings: power: rockchip: Convert to json-schema dt-bindings: arm: rockchip: add more compatible strings to pmu.yaml dt-bindings: arm: rockchip: convert pmu.txt to YAML soc: rockchip: power-domain: Add a meaningful power domain name dt-bindings: add power-domain header for RK3568 SoCs Link: https://lore.kernel.org/r/4647955.GXAFRqVoOG@phil Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
2afd1c20e7
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@ -1,16 +0,0 @@
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Rockchip power-management-unit:
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-------------------------------
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The pmu is used to turn off and on different power domains of the SoCs
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This includes the power to the CPU cores.
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Required node properties:
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- compatible value : = "rockchip,rk3066-pmu";
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- reg : physical base address and the size of the registers window
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Example:
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pmu@20004000 {
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compatible = "rockchip,rk3066-pmu";
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reg = <0x20004000 0x100>;
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};
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@ -0,0 +1,55 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/rockchip/pmu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Rockchip Power Management Unit (PMU)
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maintainers:
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- Elaine Zhang <zhangqing@rock-chips.com>
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- Heiko Stuebner <heiko@sntech.de>
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description: |
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The PMU is used to turn on and off different power domains of the SoCs.
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This includes the power to the CPU cores.
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select:
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properties:
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compatible:
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contains:
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enum:
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- rockchip,px30-pmu
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- rockchip,rk3066-pmu
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- rockchip,rk3288-pmu
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- rockchip,rk3399-pmu
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required:
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- compatible
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properties:
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compatible:
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items:
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- enum:
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- rockchip,px30-pmu
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- rockchip,rk3066-pmu
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- rockchip,rk3288-pmu
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- rockchip,rk3399-pmu
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- const: syscon
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- const: simple-mfd
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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additionalProperties: true
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examples:
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- |
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pmu@20004000 {
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compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
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reg = <0x20004000 0x100>;
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};
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@ -29,9 +29,6 @@ properties:
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"#clock-cells":
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const: 0
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"#phy-cells":
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const: 0
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clocks:
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maxItems: 1
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@ -119,7 +116,6 @@ required:
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- reg
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- clock-output-names
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- "#clock-cells"
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- "#phy-cells"
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- host-port
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- otg-port
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@ -130,26 +126,25 @@ examples:
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#include <dt-bindings/clock/rk3399-cru.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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u2phy0: usb2-phy@e450 {
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u2phy0: usb2phy@e450 {
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compatible = "rockchip,rk3399-usb2phy";
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reg = <0xe450 0x10>;
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clocks = <&cru SCLK_USB2PHY0_REF>;
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clock-names = "phyclk";
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clock-output-names = "clk_usbphy0_480m";
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#clock-cells = <0>;
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#phy-cells = <0>;
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u2phy0_host: host-port {
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#phy-cells = <0>;
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "linestate";
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#phy-cells = <0>;
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};
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u2phy0_otg: otg-port {
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#phy-cells = <0>;
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interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "otg-bvalid", "otg-id", "linestate";
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#phy-cells = <0>;
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};
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};
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@ -0,0 +1,248 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/power/rockchip,power-controller.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Rockchip Power Domains
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maintainers:
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- Elaine Zhang <zhangqing@rock-chips.com>
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- Heiko Stuebner <heiko@sntech.de>
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description: |
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Rockchip processors include support for multiple power domains
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which can be powered up/down by software based on different
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application scenarios to save power.
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Power domains contained within power-controller node are
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generic power domain providers documented in
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Documentation/devicetree/bindings/power/power-domain.yaml.
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IP cores belonging to a power domain should contain a
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"power-domains" property that is a phandle for the
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power domain node representing the domain.
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properties:
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$nodename:
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const: power-controller
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compatible:
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enum:
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- rockchip,px30-power-controller
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- rockchip,rk3036-power-controller
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- rockchip,rk3066-power-controller
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- rockchip,rk3128-power-controller
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- rockchip,rk3188-power-controller
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- rockchip,rk3228-power-controller
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- rockchip,rk3288-power-controller
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- rockchip,rk3328-power-controller
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- rockchip,rk3366-power-controller
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- rockchip,rk3368-power-controller
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- rockchip,rk3399-power-controller
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- rockchip,rk3568-power-controller
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"#power-domain-cells":
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const: 1
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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required:
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- compatible
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- "#power-domain-cells"
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additionalProperties: false
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patternProperties:
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"^power-domain@[0-9a-f]+$":
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$ref: "#/$defs/pd-node"
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unevaluatedProperties: false
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properties:
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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patternProperties:
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"^power-domain@[0-9a-f]+$":
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$ref: "#/$defs/pd-node"
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unevaluatedProperties: false
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properties:
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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patternProperties:
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"^power-domain@[0-9a-f]+$":
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$ref: "#/$defs/pd-node"
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unevaluatedProperties: false
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properties:
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"#power-domain-cells":
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const: 0
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$defs:
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pd-node:
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type: object
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description: |
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Represents the power domains within the power controller node.
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properties:
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reg:
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maxItems: 1
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description: |
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Power domain index. Valid values are defined in
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"include/dt-bindings/power/px30-power.h"
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"include/dt-bindings/power/rk3036-power.h"
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"include/dt-bindings/power/rk3066-power.h"
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"include/dt-bindings/power/rk3128-power.h"
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"include/dt-bindings/power/rk3188-power.h"
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"include/dt-bindings/power/rk3228-power.h"
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"include/dt-bindings/power/rk3288-power.h"
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"include/dt-bindings/power/rk3328-power.h"
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"include/dt-bindings/power/rk3366-power.h"
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"include/dt-bindings/power/rk3368-power.h"
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"include/dt-bindings/power/rk3399-power.h"
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"include/dt-bindings/power/rk3568-power.h"
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clocks:
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minItems: 1
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maxItems: 30
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description: |
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A number of phandles to clocks that need to be enabled
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while power domain switches state.
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pm_qos:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description: |
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A number of phandles to qos blocks which need to be saved and restored
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while power domain switches state.
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"#power-domain-cells":
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enum: [0, 1]
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description:
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Must be 0 for nodes representing a single PM domain and 1 for nodes
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providing multiple PM domains.
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required:
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- reg
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- "#power-domain-cells"
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examples:
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- |
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#include <dt-bindings/clock/rk3399-cru.h>
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#include <dt-bindings/power/rk3399-power.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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qos_hdcp: qos@ffa90000 {
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compatible = "rockchip,rk3399-qos", "syscon";
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reg = <0x0 0xffa90000 0x0 0x20>;
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};
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qos_iep: qos@ffa98000 {
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compatible = "rockchip,rk3399-qos", "syscon";
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reg = <0x0 0xffa98000 0x0 0x20>;
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};
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qos_rga_r: qos@ffab0000 {
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compatible = "rockchip,rk3399-qos", "syscon";
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reg = <0x0 0xffab0000 0x0 0x20>;
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};
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qos_rga_w: qos@ffab0080 {
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compatible = "rockchip,rk3399-qos", "syscon";
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reg = <0x0 0xffab0080 0x0 0x20>;
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};
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qos_video_m0: qos@ffab8000 {
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compatible = "rockchip,rk3399-qos", "syscon";
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reg = <0x0 0xffab8000 0x0 0x20>;
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};
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qos_video_m1_r: qos@ffac0000 {
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compatible = "rockchip,rk3399-qos", "syscon";
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reg = <0x0 0xffac0000 0x0 0x20>;
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};
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qos_video_m1_w: qos@ffac0080 {
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compatible = "rockchip,rk3399-qos", "syscon";
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reg = <0x0 0xffac0080 0x0 0x20>;
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};
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power-management@ff310000 {
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compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
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reg = <0x0 0xff310000 0x0 0x1000>;
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power-controller {
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compatible = "rockchip,rk3399-power-controller";
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#power-domain-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* These power domains are grouped by VD_CENTER */
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power-domain@RK3399_PD_IEP {
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reg = <RK3399_PD_IEP>;
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clocks = <&cru ACLK_IEP>,
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<&cru HCLK_IEP>;
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pm_qos = <&qos_iep>;
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#power-domain-cells = <0>;
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};
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power-domain@RK3399_PD_RGA {
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reg = <RK3399_PD_RGA>;
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clocks = <&cru ACLK_RGA>,
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<&cru HCLK_RGA>;
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pm_qos = <&qos_rga_r>,
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<&qos_rga_w>;
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#power-domain-cells = <0>;
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};
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power-domain@RK3399_PD_VCODEC {
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reg = <RK3399_PD_VCODEC>;
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clocks = <&cru ACLK_VCODEC>,
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<&cru HCLK_VCODEC>;
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pm_qos = <&qos_video_m0>;
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#power-domain-cells = <0>;
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};
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power-domain@RK3399_PD_VDU {
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reg = <RK3399_PD_VDU>;
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clocks = <&cru ACLK_VDU>,
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<&cru HCLK_VDU>;
|
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pm_qos = <&qos_video_m1_r>,
|
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<&qos_video_m1_w>;
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#power-domain-cells = <0>;
|
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};
|
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power-domain@RK3399_PD_VIO {
|
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reg = <RK3399_PD_VIO>;
|
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#power-domain-cells = <1>;
|
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#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
power-domain@RK3399_PD_HDCP {
|
||||
reg = <RK3399_PD_HDCP>;
|
||||
clocks = <&cru ACLK_HDCP>,
|
||||
<&cru HCLK_HDCP>,
|
||||
<&cru PCLK_HDCP>;
|
||||
pm_qos = <&qos_hdcp>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1,61 +0,0 @@
|
|||
* Rockchip General Register Files (GRF)
|
||||
|
||||
The general register file will be used to do static set by software, which
|
||||
is composed of many registers for system control.
|
||||
|
||||
From RK3368 SoCs, the GRF is divided into two sections,
|
||||
- GRF, used for general non-secure system,
|
||||
- SGRF, used for general secure system,
|
||||
- PMUGRF, used for always on system
|
||||
|
||||
On RK3328 SoCs, the GRF adds a section for USB2PHYGRF,
|
||||
|
||||
ON RK3308 SoC, the GRF is divided into four sections:
|
||||
- GRF, used for general non-secure system,
|
||||
- SGRF, used for general secure system,
|
||||
- DETECTGRF, used for audio codec system,
|
||||
- COREGRF, used for pvtm,
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: GRF should be one of the following:
|
||||
- "rockchip,px30-grf", "syscon": for px30
|
||||
- "rockchip,rk3036-grf", "syscon": for rk3036
|
||||
- "rockchip,rk3066-grf", "syscon": for rk3066
|
||||
- "rockchip,rk3188-grf", "syscon": for rk3188
|
||||
- "rockchip,rk3228-grf", "syscon": for rk3228
|
||||
- "rockchip,rk3288-grf", "syscon": for rk3288
|
||||
- "rockchip,rk3308-grf", "syscon": for rk3308
|
||||
- "rockchip,rk3328-grf", "syscon": for rk3328
|
||||
- "rockchip,rk3368-grf", "syscon": for rk3368
|
||||
- "rockchip,rk3399-grf", "syscon": for rk3399
|
||||
- "rockchip,rv1108-grf", "syscon": for rv1108
|
||||
- compatible: DETECTGRF should be one of the following:
|
||||
- "rockchip,rk3308-detect-grf", "syscon": for rk3308
|
||||
- compatilbe: COREGRF should be one of the following:
|
||||
- "rockchip,rk3308-core-grf", "syscon": for rk3308
|
||||
- compatible: PMUGRF should be one of the following:
|
||||
- "rockchip,px30-pmugrf", "syscon": for px30
|
||||
- "rockchip,rk3368-pmugrf", "syscon": for rk3368
|
||||
- "rockchip,rk3399-pmugrf", "syscon": for rk3399
|
||||
- compatible: SGRF should be one of the following:
|
||||
- "rockchip,rk3288-sgrf", "syscon": for rk3288
|
||||
- compatible: USB2PHYGRF should be one of the following:
|
||||
- "rockchip,px30-usb2phy-grf", "syscon": for px30
|
||||
- "rockchip,rk3328-usb2phy-grf", "syscon": for rk3328
|
||||
- compatible: USBGRF should be one of the following:
|
||||
- "rockchip,rv1108-usbgrf", "syscon": for rv1108
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
||||
Example: GRF and PMUGRF of RK3399 SoCs
|
||||
|
||||
pmugrf: syscon@ff320000 {
|
||||
compatible = "rockchip,rk3399-pmugrf", "syscon";
|
||||
reg = <0x0 0xff320000 0x0 0x1000>;
|
||||
};
|
||||
|
||||
grf: syscon@ff770000 {
|
||||
compatible = "rockchip,rk3399-grf", "syscon";
|
||||
reg = <0x0 0xff770000 0x0 0x10000>;
|
||||
};
|
||||
|
|
@ -0,0 +1,261 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/soc/rockchip/grf.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip General Register Files (GRF)
|
||||
|
||||
maintainers:
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- rockchip,rk3288-sgrf
|
||||
- rockchip,rv1108-pmugrf
|
||||
- rockchip,rv1108-usbgrf
|
||||
- const: syscon
|
||||
- items:
|
||||
- enum:
|
||||
- rockchip,px30-grf
|
||||
- rockchip,px30-pmugrf
|
||||
- rockchip,px30-usb2phy-grf
|
||||
- rockchip,rk3036-grf
|
||||
- rockchip,rk3066-grf
|
||||
- rockchip,rk3188-grf
|
||||
- rockchip,rk3228-grf
|
||||
- rockchip,rk3288-grf
|
||||
- rockchip,rk3308-core-grf
|
||||
- rockchip,rk3308-detect-grf
|
||||
- rockchip,rk3308-grf
|
||||
- rockchip,rk3308-usb2phy-grf
|
||||
- rockchip,rk3328-grf
|
||||
- rockchip,rk3328-usb2phy-grf
|
||||
- rockchip,rk3368-grf
|
||||
- rockchip,rk3368-pmugrf
|
||||
- rockchip,rk3399-grf
|
||||
- rockchip,rk3399-pmugrf
|
||||
- rockchip,rk3568-grf
|
||||
- rockchip,rk3568-pmugrf
|
||||
- rockchip,rv1108-grf
|
||||
- const: syscon
|
||||
- const: simple-mfd
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#address-cells":
|
||||
const: 1
|
||||
|
||||
"#size-cells":
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties:
|
||||
type: object
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: rockchip,px30-grf
|
||||
|
||||
then:
|
||||
properties:
|
||||
lvds:
|
||||
description:
|
||||
Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: rockchip,rk3288-grf
|
||||
|
||||
then:
|
||||
properties:
|
||||
edp-phy:
|
||||
description:
|
||||
Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- rockchip,rk3066-grf
|
||||
- rockchip,rk3188-grf
|
||||
- rockchip,rk3288-grf
|
||||
|
||||
then:
|
||||
properties:
|
||||
usbphy:
|
||||
type: object
|
||||
|
||||
$ref: "/schemas/phy/rockchip-usb-phy.yaml#"
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: rockchip,rk3328-grf
|
||||
|
||||
then:
|
||||
properties:
|
||||
gpio:
|
||||
type: object
|
||||
|
||||
$ref: "/schemas/gpio/rockchip,rk3328-grf-gpio.yaml#"
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
power-controller:
|
||||
type: object
|
||||
|
||||
$ref: "/schemas/power/rockchip,power-controller.yaml#"
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: rockchip,rk3399-grf
|
||||
|
||||
then:
|
||||
properties:
|
||||
mipi-dphy-rx0:
|
||||
type: object
|
||||
|
||||
$ref: "/schemas/phy/rockchip-mipi-dphy-rx0.yaml#"
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
pcie-phy:
|
||||
description:
|
||||
Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
|
||||
|
||||
patternProperties:
|
||||
"phy@[0-9a-f]+$":
|
||||
description:
|
||||
Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- rockchip,px30-pmugrf
|
||||
- rockchip,rk3036-grf
|
||||
- rockchip,rk3308-grf
|
||||
- rockchip,rk3368-pmugrf
|
||||
|
||||
then:
|
||||
properties:
|
||||
reboot-mode:
|
||||
type: object
|
||||
|
||||
$ref: "/schemas/power/reset/syscon-reboot-mode.yaml#"
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- rockchip,px30-usb2phy-grf
|
||||
- rockchip,rk3228-grf
|
||||
- rockchip,rk3308-usb2phy-grf
|
||||
- rockchip,rk3328-usb2phy-grf
|
||||
- rockchip,rk3399-grf
|
||||
- rockchip,rv1108-grf
|
||||
|
||||
then:
|
||||
required:
|
||||
- "#address-cells"
|
||||
- "#size-cells"
|
||||
|
||||
patternProperties:
|
||||
"usb2phy@[0-9a-f]+$":
|
||||
type: object
|
||||
|
||||
$ref: "/schemas/phy/phy-rockchip-inno-usb2.yaml#"
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- rockchip,px30-pmugrf
|
||||
- rockchip,px30-grf
|
||||
- rockchip,rk3228-grf
|
||||
- rockchip,rk3288-grf
|
||||
- rockchip,rk3328-grf
|
||||
- rockchip,rk3368-pmugrf
|
||||
- rockchip,rk3368-grf
|
||||
- rockchip,rk3399-pmugrf
|
||||
- rockchip,rk3399-grf
|
||||
|
||||
then:
|
||||
properties:
|
||||
io-domains:
|
||||
description:
|
||||
Documentation/devicetree/bindings/power/rockchip-io-domain.txt
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/rk3399-cru.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/rk3399-power.h>
|
||||
grf: syscon@ff770000 {
|
||||
compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
|
||||
reg = <0xff770000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
mipi_dphy_rx0: mipi-dphy-rx0 {
|
||||
compatible = "rockchip,rk3399-mipi-dphy-rx0";
|
||||
clocks = <&cru SCLK_MIPIDPHY_REF>,
|
||||
<&cru SCLK_DPHY_RX0_CFG>,
|
||||
<&cru PCLK_VIO_GRF>;
|
||||
clock-names = "dphy-ref", "dphy-cfg", "grf";
|
||||
power-domains = <&power RK3399_PD_VIO>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
u2phy0: usb2phy@e450 {
|
||||
compatible = "rockchip,rk3399-usb2phy";
|
||||
reg = <0xe450 0x10>;
|
||||
clocks = <&cru SCLK_USB2PHY0_REF>;
|
||||
clock-names = "phyclk";
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "clk_usbphy0_480m";
|
||||
|
||||
u2phy0_host: host-port {
|
||||
#phy-cells = <0>;
|
||||
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "linestate";
|
||||
};
|
||||
|
||||
u2phy0_otg: otg-port {
|
||||
#phy-cells = <0>;
|
||||
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "otg-bvalid", "otg-id",
|
||||
"linestate";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1,136 +0,0 @@
|
|||
* Rockchip Power Domains
|
||||
|
||||
Rockchip processors include support for multiple power domains which can be
|
||||
powered up/down by software based on different application scenes to save power.
|
||||
|
||||
Required properties for power domain controller:
|
||||
- compatible: Should be one of the following.
|
||||
"rockchip,px30-power-controller" - for PX30 SoCs.
|
||||
"rockchip,rk3036-power-controller" - for RK3036 SoCs.
|
||||
"rockchip,rk3066-power-controller" - for RK3066 SoCs.
|
||||
"rockchip,rk3128-power-controller" - for RK3128 SoCs.
|
||||
"rockchip,rk3188-power-controller" - for RK3188 SoCs.
|
||||
"rockchip,rk3228-power-controller" - for RK3228 SoCs.
|
||||
"rockchip,rk3288-power-controller" - for RK3288 SoCs.
|
||||
"rockchip,rk3328-power-controller" - for RK3328 SoCs.
|
||||
"rockchip,rk3366-power-controller" - for RK3366 SoCs.
|
||||
"rockchip,rk3368-power-controller" - for RK3368 SoCs.
|
||||
"rockchip,rk3399-power-controller" - for RK3399 SoCs.
|
||||
- #power-domain-cells: Number of cells in a power-domain specifier.
|
||||
Should be 1 for multiple PM domains.
|
||||
- #address-cells: Should be 1.
|
||||
- #size-cells: Should be 0.
|
||||
|
||||
Required properties for power domain sub nodes:
|
||||
- reg: index of the power domain, should use macros in:
|
||||
"include/dt-bindings/power/px30-power.h" - for PX30 type power domain.
|
||||
"include/dt-bindings/power/rk3036-power.h" - for RK3036 type power domain.
|
||||
"include/dt-bindings/power/rk3066-power.h" - for RK3066 type power domain.
|
||||
"include/dt-bindings/power/rk3128-power.h" - for RK3128 type power domain.
|
||||
"include/dt-bindings/power/rk3188-power.h" - for RK3188 type power domain.
|
||||
"include/dt-bindings/power/rk3228-power.h" - for RK3228 type power domain.
|
||||
"include/dt-bindings/power/rk3288-power.h" - for RK3288 type power domain.
|
||||
"include/dt-bindings/power/rk3328-power.h" - for RK3328 type power domain.
|
||||
"include/dt-bindings/power/rk3366-power.h" - for RK3366 type power domain.
|
||||
"include/dt-bindings/power/rk3368-power.h" - for RK3368 type power domain.
|
||||
"include/dt-bindings/power/rk3399-power.h" - for RK3399 type power domain.
|
||||
- clocks (optional): phandles to clocks which need to be enabled while power domain
|
||||
switches state.
|
||||
- pm_qos (optional): phandles to qos blocks which need to be saved and restored
|
||||
while power domain switches state.
|
||||
|
||||
Qos Example:
|
||||
|
||||
qos_gpu: qos_gpu@ffaf0000 {
|
||||
compatible ="syscon";
|
||||
reg = <0x0 0xffaf0000 0x0 0x20>;
|
||||
};
|
||||
|
||||
Example:
|
||||
|
||||
power: power-controller {
|
||||
compatible = "rockchip,rk3288-power-controller";
|
||||
#power-domain-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pd_gpu {
|
||||
reg = <RK3288_PD_GPU>;
|
||||
clocks = <&cru ACLK_GPU>;
|
||||
pm_qos = <&qos_gpu>;
|
||||
};
|
||||
};
|
||||
|
||||
power: power-controller {
|
||||
compatible = "rockchip,rk3368-power-controller";
|
||||
#power-domain-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pd_gpu_1 {
|
||||
reg = <RK3368_PD_GPU_1>;
|
||||
clocks = <&cru ACLK_GPU_CFG>;
|
||||
};
|
||||
};
|
||||
|
||||
Example 2:
|
||||
power: power-controller {
|
||||
compatible = "rockchip,rk3399-power-controller";
|
||||
#power-domain-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pd_vio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <RK3399_PD_VIO>;
|
||||
|
||||
pd_vo {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <RK3399_PD_VO>;
|
||||
|
||||
pd_vopb {
|
||||
reg = <RK3399_PD_VOPB>;
|
||||
};
|
||||
|
||||
pd_vopl {
|
||||
reg = <RK3399_PD_VOPL>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
Node of a device using power domains must have a power-domains property,
|
||||
containing a phandle to the power device node and an index specifying which
|
||||
power domain to use.
|
||||
The index should use macros in:
|
||||
"include/dt-bindings/power/px30-power.h" - for px30 type power domain.
|
||||
"include/dt-bindings/power/rk3036-power.h" - for rk3036 type power domain.
|
||||
"include/dt-bindings/power/rk3128-power.h" - for rk3128 type power domain.
|
||||
"include/dt-bindings/power/rk3128-power.h" - for rk3228 type power domain.
|
||||
"include/dt-bindings/power/rk3288-power.h" - for rk3288 type power domain.
|
||||
"include/dt-bindings/power/rk3328-power.h" - for rk3328 type power domain.
|
||||
"include/dt-bindings/power/rk3366-power.h" - for rk3366 type power domain.
|
||||
"include/dt-bindings/power/rk3368-power.h" - for rk3368 type power domain.
|
||||
"include/dt-bindings/power/rk3399-power.h" - for rk3399 type power domain.
|
||||
|
||||
Example of the node using power domain:
|
||||
|
||||
node {
|
||||
/* ... */
|
||||
power-domains = <&power RK3288_PD_GPU>;
|
||||
/* ... */
|
||||
};
|
||||
|
||||
node {
|
||||
/* ... */
|
||||
power-domains = <&power RK3368_PD_GPU_1>;
|
||||
/* ... */
|
||||
};
|
||||
|
||||
node {
|
||||
/* ... */
|
||||
power-domains = <&power RK3399_PD_VOPB>;
|
||||
/* ... */
|
||||
};
|
||||
|
|
@ -27,8 +27,10 @@
|
|||
#include <dt-bindings/power/rk3366-power.h>
|
||||
#include <dt-bindings/power/rk3368-power.h>
|
||||
#include <dt-bindings/power/rk3399-power.h>
|
||||
#include <dt-bindings/power/rk3568-power.h>
|
||||
|
||||
struct rockchip_domain_info {
|
||||
const char *name;
|
||||
int pwr_mask;
|
||||
int status_mask;
|
||||
int req_mask;
|
||||
|
|
@ -85,8 +87,9 @@ struct rockchip_pmu {
|
|||
|
||||
#define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd)
|
||||
|
||||
#define DOMAIN(pwr, status, req, idle, ack, wakeup) \
|
||||
#define DOMAIN(_name, pwr, status, req, idle, ack, wakeup) \
|
||||
{ \
|
||||
.name = _name, \
|
||||
.pwr_mask = (pwr), \
|
||||
.status_mask = (status), \
|
||||
.req_mask = (req), \
|
||||
|
|
@ -95,8 +98,9 @@ struct rockchip_pmu {
|
|||
.active_wakeup = (wakeup), \
|
||||
}
|
||||
|
||||
#define DOMAIN_M(pwr, status, req, idle, ack, wakeup) \
|
||||
#define DOMAIN_M(_name, pwr, status, req, idle, ack, wakeup) \
|
||||
{ \
|
||||
.name = _name, \
|
||||
.pwr_w_mask = (pwr) << 16, \
|
||||
.pwr_mask = (pwr), \
|
||||
.status_mask = (status), \
|
||||
|
|
@ -107,8 +111,9 @@ struct rockchip_pmu {
|
|||
.active_wakeup = wakeup, \
|
||||
}
|
||||
|
||||
#define DOMAIN_RK3036(req, ack, idle, wakeup) \
|
||||
#define DOMAIN_RK3036(_name, req, ack, idle, wakeup) \
|
||||
{ \
|
||||
.name = _name, \
|
||||
.req_mask = (req), \
|
||||
.req_w_mask = (req) << 16, \
|
||||
.ack_mask = (ack), \
|
||||
|
|
@ -116,20 +121,23 @@ struct rockchip_pmu {
|
|||
.active_wakeup = wakeup, \
|
||||
}
|
||||
|
||||
#define DOMAIN_PX30(pwr, status, req, wakeup) \
|
||||
DOMAIN_M(pwr, status, req, (req) << 16, req, wakeup)
|
||||
#define DOMAIN_PX30(name, pwr, status, req, wakeup) \
|
||||
DOMAIN_M(name, pwr, status, req, (req) << 16, req, wakeup)
|
||||
|
||||
#define DOMAIN_RK3288(pwr, status, req, wakeup) \
|
||||
DOMAIN(pwr, status, req, req, (req) << 16, wakeup)
|
||||
#define DOMAIN_RK3288(name, pwr, status, req, wakeup) \
|
||||
DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup)
|
||||
|
||||
#define DOMAIN_RK3328(pwr, status, req, wakeup) \
|
||||
DOMAIN_M(pwr, pwr, req, (req) << 10, req, wakeup)
|
||||
#define DOMAIN_RK3328(name, pwr, status, req, wakeup) \
|
||||
DOMAIN_M(name, pwr, pwr, req, (req) << 10, req, wakeup)
|
||||
|
||||
#define DOMAIN_RK3368(pwr, status, req, wakeup) \
|
||||
DOMAIN(pwr, status, req, (req) << 16, req, wakeup)
|
||||
#define DOMAIN_RK3368(name, pwr, status, req, wakeup) \
|
||||
DOMAIN(name, pwr, status, req, (req) << 16, req, wakeup)
|
||||
|
||||
#define DOMAIN_RK3399(pwr, status, req, wakeup) \
|
||||
DOMAIN(pwr, status, req, req, req, wakeup)
|
||||
#define DOMAIN_RK3399(name, pwr, status, req, wakeup) \
|
||||
DOMAIN(name, pwr, status, req, req, req, wakeup)
|
||||
|
||||
#define DOMAIN_RK3568(name, pwr, req, wakeup) \
|
||||
DOMAIN_M(name, pwr, pwr, req, req, req, wakeup)
|
||||
|
||||
static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
|
||||
{
|
||||
|
|
@ -490,7 +498,10 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
|
|||
goto err_unprepare_clocks;
|
||||
}
|
||||
|
||||
pd->genpd.name = node->name;
|
||||
if (pd->info->name)
|
||||
pd->genpd.name = pd->info->name;
|
||||
else
|
||||
pd->genpd.name = kbasename(node->full_name);
|
||||
pd->genpd.power_off = rockchip_pd_power_off;
|
||||
pd->genpd.power_on = rockchip_pd_power_on;
|
||||
pd->genpd.attach_dev = rockchip_pd_attach_dev;
|
||||
|
|
@ -716,129 +727,141 @@ static int rockchip_pm_domain_probe(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
static const struct rockchip_domain_info px30_pm_domains[] = {
|
||||
[PX30_PD_USB] = DOMAIN_PX30(BIT(5), BIT(5), BIT(10), false),
|
||||
[PX30_PD_SDCARD] = DOMAIN_PX30(BIT(8), BIT(8), BIT(9), false),
|
||||
[PX30_PD_GMAC] = DOMAIN_PX30(BIT(10), BIT(10), BIT(6), false),
|
||||
[PX30_PD_MMC_NAND] = DOMAIN_PX30(BIT(11), BIT(11), BIT(5), false),
|
||||
[PX30_PD_VPU] = DOMAIN_PX30(BIT(12), BIT(12), BIT(14), false),
|
||||
[PX30_PD_VO] = DOMAIN_PX30(BIT(13), BIT(13), BIT(7), false),
|
||||
[PX30_PD_VI] = DOMAIN_PX30(BIT(14), BIT(14), BIT(8), false),
|
||||
[PX30_PD_GPU] = DOMAIN_PX30(BIT(15), BIT(15), BIT(2), false),
|
||||
[PX30_PD_USB] = DOMAIN_PX30("usb", BIT(5), BIT(5), BIT(10), false),
|
||||
[PX30_PD_SDCARD] = DOMAIN_PX30("sdcard", BIT(8), BIT(8), BIT(9), false),
|
||||
[PX30_PD_GMAC] = DOMAIN_PX30("gmac", BIT(10), BIT(10), BIT(6), false),
|
||||
[PX30_PD_MMC_NAND] = DOMAIN_PX30("mmc_nand", BIT(11), BIT(11), BIT(5), false),
|
||||
[PX30_PD_VPU] = DOMAIN_PX30("vpu", BIT(12), BIT(12), BIT(14), false),
|
||||
[PX30_PD_VO] = DOMAIN_PX30("vo", BIT(13), BIT(13), BIT(7), false),
|
||||
[PX30_PD_VI] = DOMAIN_PX30("vi", BIT(14), BIT(14), BIT(8), false),
|
||||
[PX30_PD_GPU] = DOMAIN_PX30("gpu", BIT(15), BIT(15), BIT(2), false),
|
||||
};
|
||||
|
||||
static const struct rockchip_domain_info rk3036_pm_domains[] = {
|
||||
[RK3036_PD_MSCH] = DOMAIN_RK3036(BIT(14), BIT(23), BIT(30), true),
|
||||
[RK3036_PD_CORE] = DOMAIN_RK3036(BIT(13), BIT(17), BIT(24), false),
|
||||
[RK3036_PD_PERI] = DOMAIN_RK3036(BIT(12), BIT(18), BIT(25), false),
|
||||
[RK3036_PD_VIO] = DOMAIN_RK3036(BIT(11), BIT(19), BIT(26), false),
|
||||
[RK3036_PD_VPU] = DOMAIN_RK3036(BIT(10), BIT(20), BIT(27), false),
|
||||
[RK3036_PD_GPU] = DOMAIN_RK3036(BIT(9), BIT(21), BIT(28), false),
|
||||
[RK3036_PD_SYS] = DOMAIN_RK3036(BIT(8), BIT(22), BIT(29), false),
|
||||
[RK3036_PD_MSCH] = DOMAIN_RK3036("msch", BIT(14), BIT(23), BIT(30), true),
|
||||
[RK3036_PD_CORE] = DOMAIN_RK3036("core", BIT(13), BIT(17), BIT(24), false),
|
||||
[RK3036_PD_PERI] = DOMAIN_RK3036("peri", BIT(12), BIT(18), BIT(25), false),
|
||||
[RK3036_PD_VIO] = DOMAIN_RK3036("vio", BIT(11), BIT(19), BIT(26), false),
|
||||
[RK3036_PD_VPU] = DOMAIN_RK3036("vpu", BIT(10), BIT(20), BIT(27), false),
|
||||
[RK3036_PD_GPU] = DOMAIN_RK3036("gpu", BIT(9), BIT(21), BIT(28), false),
|
||||
[RK3036_PD_SYS] = DOMAIN_RK3036("sys", BIT(8), BIT(22), BIT(29), false),
|
||||
};
|
||||
|
||||
static const struct rockchip_domain_info rk3066_pm_domains[] = {
|
||||
[RK3066_PD_GPU] = DOMAIN(BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false),
|
||||
[RK3066_PD_VIDEO] = DOMAIN(BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false),
|
||||
[RK3066_PD_VIO] = DOMAIN(BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false),
|
||||
[RK3066_PD_PERI] = DOMAIN(BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false),
|
||||
[RK3066_PD_CPU] = DOMAIN(0, BIT(5), BIT(1), BIT(26), BIT(31), false),
|
||||
[RK3066_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false),
|
||||
[RK3066_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false),
|
||||
[RK3066_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false),
|
||||
[RK3066_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false),
|
||||
[RK3066_PD_CPU] = DOMAIN("cpu", 0, BIT(5), BIT(1), BIT(26), BIT(31), false),
|
||||
};
|
||||
|
||||
static const struct rockchip_domain_info rk3128_pm_domains[] = {
|
||||
[RK3128_PD_CORE] = DOMAIN_RK3288(BIT(0), BIT(0), BIT(4), false),
|
||||
[RK3128_PD_MSCH] = DOMAIN_RK3288(0, 0, BIT(6), true),
|
||||
[RK3128_PD_VIO] = DOMAIN_RK3288(BIT(3), BIT(3), BIT(2), false),
|
||||
[RK3128_PD_VIDEO] = DOMAIN_RK3288(BIT(2), BIT(2), BIT(1), false),
|
||||
[RK3128_PD_GPU] = DOMAIN_RK3288(BIT(1), BIT(1), BIT(3), false),
|
||||
[RK3128_PD_CORE] = DOMAIN_RK3288("core", BIT(0), BIT(0), BIT(4), false),
|
||||
[RK3128_PD_MSCH] = DOMAIN_RK3288("msch", 0, 0, BIT(6), true),
|
||||
[RK3128_PD_VIO] = DOMAIN_RK3288("vio", BIT(3), BIT(3), BIT(2), false),
|
||||
[RK3128_PD_VIDEO] = DOMAIN_RK3288("video", BIT(2), BIT(2), BIT(1), false),
|
||||
[RK3128_PD_GPU] = DOMAIN_RK3288("gpu", BIT(1), BIT(1), BIT(3), false),
|
||||
};
|
||||
|
||||
static const struct rockchip_domain_info rk3188_pm_domains[] = {
|
||||
[RK3188_PD_GPU] = DOMAIN(BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false),
|
||||
[RK3188_PD_VIDEO] = DOMAIN(BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false),
|
||||
[RK3188_PD_VIO] = DOMAIN(BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false),
|
||||
[RK3188_PD_PERI] = DOMAIN(BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false),
|
||||
[RK3188_PD_CPU] = DOMAIN(BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false),
|
||||
[RK3188_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false),
|
||||
[RK3188_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false),
|
||||
[RK3188_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false),
|
||||
[RK3188_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false),
|
||||
[RK3188_PD_CPU] = DOMAIN("cpu", BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false),
|
||||
};
|
||||
|
||||
static const struct rockchip_domain_info rk3228_pm_domains[] = {
|
||||
[RK3228_PD_CORE] = DOMAIN_RK3036(BIT(0), BIT(0), BIT(16), true),
|
||||
[RK3228_PD_MSCH] = DOMAIN_RK3036(BIT(1), BIT(1), BIT(17), true),
|
||||
[RK3228_PD_BUS] = DOMAIN_RK3036(BIT(2), BIT(2), BIT(18), true),
|
||||
[RK3228_PD_SYS] = DOMAIN_RK3036(BIT(3), BIT(3), BIT(19), true),
|
||||
[RK3228_PD_VIO] = DOMAIN_RK3036(BIT(4), BIT(4), BIT(20), false),
|
||||
[RK3228_PD_VOP] = DOMAIN_RK3036(BIT(5), BIT(5), BIT(21), false),
|
||||
[RK3228_PD_VPU] = DOMAIN_RK3036(BIT(6), BIT(6), BIT(22), false),
|
||||
[RK3228_PD_RKVDEC] = DOMAIN_RK3036(BIT(7), BIT(7), BIT(23), false),
|
||||
[RK3228_PD_GPU] = DOMAIN_RK3036(BIT(8), BIT(8), BIT(24), false),
|
||||
[RK3228_PD_PERI] = DOMAIN_RK3036(BIT(9), BIT(9), BIT(25), true),
|
||||
[RK3228_PD_GMAC] = DOMAIN_RK3036(BIT(10), BIT(10), BIT(26), false),
|
||||
[RK3228_PD_CORE] = DOMAIN_RK3036("core", BIT(0), BIT(0), BIT(16), true),
|
||||
[RK3228_PD_MSCH] = DOMAIN_RK3036("msch", BIT(1), BIT(1), BIT(17), true),
|
||||
[RK3228_PD_BUS] = DOMAIN_RK3036("bus", BIT(2), BIT(2), BIT(18), true),
|
||||
[RK3228_PD_SYS] = DOMAIN_RK3036("sys", BIT(3), BIT(3), BIT(19), true),
|
||||
[RK3228_PD_VIO] = DOMAIN_RK3036("vio", BIT(4), BIT(4), BIT(20), false),
|
||||
[RK3228_PD_VOP] = DOMAIN_RK3036("vop", BIT(5), BIT(5), BIT(21), false),
|
||||
[RK3228_PD_VPU] = DOMAIN_RK3036("vpu", BIT(6), BIT(6), BIT(22), false),
|
||||
[RK3228_PD_RKVDEC] = DOMAIN_RK3036("vdec", BIT(7), BIT(7), BIT(23), false),
|
||||
[RK3228_PD_GPU] = DOMAIN_RK3036("gpu", BIT(8), BIT(8), BIT(24), false),
|
||||
[RK3228_PD_PERI] = DOMAIN_RK3036("peri", BIT(9), BIT(9), BIT(25), true),
|
||||
[RK3228_PD_GMAC] = DOMAIN_RK3036("gmac", BIT(10), BIT(10), BIT(26), false),
|
||||
};
|
||||
|
||||
static const struct rockchip_domain_info rk3288_pm_domains[] = {
|
||||
[RK3288_PD_VIO] = DOMAIN_RK3288(BIT(7), BIT(7), BIT(4), false),
|
||||
[RK3288_PD_HEVC] = DOMAIN_RK3288(BIT(14), BIT(10), BIT(9), false),
|
||||
[RK3288_PD_VIDEO] = DOMAIN_RK3288(BIT(8), BIT(8), BIT(3), false),
|
||||
[RK3288_PD_GPU] = DOMAIN_RK3288(BIT(9), BIT(9), BIT(2), false),
|
||||
[RK3288_PD_VIO] = DOMAIN_RK3288("vio", BIT(7), BIT(7), BIT(4), false),
|
||||
[RK3288_PD_HEVC] = DOMAIN_RK3288("hevc", BIT(14), BIT(10), BIT(9), false),
|
||||
[RK3288_PD_VIDEO] = DOMAIN_RK3288("video", BIT(8), BIT(8), BIT(3), false),
|
||||
[RK3288_PD_GPU] = DOMAIN_RK3288("gpu", BIT(9), BIT(9), BIT(2), false),
|
||||
};
|
||||
|
||||
static const struct rockchip_domain_info rk3328_pm_domains[] = {
|
||||
[RK3328_PD_CORE] = DOMAIN_RK3328(0, BIT(0), BIT(0), false),
|
||||
[RK3328_PD_GPU] = DOMAIN_RK3328(0, BIT(1), BIT(1), false),
|
||||
[RK3328_PD_BUS] = DOMAIN_RK3328(0, BIT(2), BIT(2), true),
|
||||
[RK3328_PD_MSCH] = DOMAIN_RK3328(0, BIT(3), BIT(3), true),
|
||||
[RK3328_PD_PERI] = DOMAIN_RK3328(0, BIT(4), BIT(4), true),
|
||||
[RK3328_PD_VIDEO] = DOMAIN_RK3328(0, BIT(5), BIT(5), false),
|
||||
[RK3328_PD_HEVC] = DOMAIN_RK3328(0, BIT(6), BIT(6), false),
|
||||
[RK3328_PD_VIO] = DOMAIN_RK3328(0, BIT(8), BIT(8), false),
|
||||
[RK3328_PD_VPU] = DOMAIN_RK3328(0, BIT(9), BIT(9), false),
|
||||
[RK3328_PD_CORE] = DOMAIN_RK3328("core", 0, BIT(0), BIT(0), false),
|
||||
[RK3328_PD_GPU] = DOMAIN_RK3328("gpu", 0, BIT(1), BIT(1), false),
|
||||
[RK3328_PD_BUS] = DOMAIN_RK3328("bus", 0, BIT(2), BIT(2), true),
|
||||
[RK3328_PD_MSCH] = DOMAIN_RK3328("msch", 0, BIT(3), BIT(3), true),
|
||||
[RK3328_PD_PERI] = DOMAIN_RK3328("peri", 0, BIT(4), BIT(4), true),
|
||||
[RK3328_PD_VIDEO] = DOMAIN_RK3328("video", 0, BIT(5), BIT(5), false),
|
||||
[RK3328_PD_HEVC] = DOMAIN_RK3328("hevc", 0, BIT(6), BIT(6), false),
|
||||
[RK3328_PD_VIO] = DOMAIN_RK3328("vio", 0, BIT(8), BIT(8), false),
|
||||
[RK3328_PD_VPU] = DOMAIN_RK3328("vpu", 0, BIT(9), BIT(9), false),
|
||||
};
|
||||
|
||||
static const struct rockchip_domain_info rk3366_pm_domains[] = {
|
||||
[RK3366_PD_PERI] = DOMAIN_RK3368(BIT(10), BIT(10), BIT(6), true),
|
||||
[RK3366_PD_VIO] = DOMAIN_RK3368(BIT(14), BIT(14), BIT(8), false),
|
||||
[RK3366_PD_VIDEO] = DOMAIN_RK3368(BIT(13), BIT(13), BIT(7), false),
|
||||
[RK3366_PD_RKVDEC] = DOMAIN_RK3368(BIT(11), BIT(11), BIT(7), false),
|
||||
[RK3366_PD_WIFIBT] = DOMAIN_RK3368(BIT(8), BIT(8), BIT(9), false),
|
||||
[RK3366_PD_VPU] = DOMAIN_RK3368(BIT(12), BIT(12), BIT(7), false),
|
||||
[RK3366_PD_GPU] = DOMAIN_RK3368(BIT(15), BIT(15), BIT(2), false),
|
||||
[RK3366_PD_PERI] = DOMAIN_RK3368("peri", BIT(10), BIT(10), BIT(6), true),
|
||||
[RK3366_PD_VIO] = DOMAIN_RK3368("vio", BIT(14), BIT(14), BIT(8), false),
|
||||
[RK3366_PD_VIDEO] = DOMAIN_RK3368("video", BIT(13), BIT(13), BIT(7), false),
|
||||
[RK3366_PD_RKVDEC] = DOMAIN_RK3368("vdec", BIT(11), BIT(11), BIT(7), false),
|
||||
[RK3366_PD_WIFIBT] = DOMAIN_RK3368("wifibt", BIT(8), BIT(8), BIT(9), false),
|
||||
[RK3366_PD_VPU] = DOMAIN_RK3368("vpu", BIT(12), BIT(12), BIT(7), false),
|
||||
[RK3366_PD_GPU] = DOMAIN_RK3368("gpu", BIT(15), BIT(15), BIT(2), false),
|
||||
};
|
||||
|
||||
static const struct rockchip_domain_info rk3368_pm_domains[] = {
|
||||
[RK3368_PD_PERI] = DOMAIN_RK3368(BIT(13), BIT(12), BIT(6), true),
|
||||
[RK3368_PD_VIO] = DOMAIN_RK3368(BIT(15), BIT(14), BIT(8), false),
|
||||
[RK3368_PD_VIDEO] = DOMAIN_RK3368(BIT(14), BIT(13), BIT(7), false),
|
||||
[RK3368_PD_GPU_0] = DOMAIN_RK3368(BIT(16), BIT(15), BIT(2), false),
|
||||
[RK3368_PD_GPU_1] = DOMAIN_RK3368(BIT(17), BIT(16), BIT(2), false),
|
||||
[RK3368_PD_PERI] = DOMAIN_RK3368("peri", BIT(13), BIT(12), BIT(6), true),
|
||||
[RK3368_PD_VIO] = DOMAIN_RK3368("vio", BIT(15), BIT(14), BIT(8), false),
|
||||
[RK3368_PD_VIDEO] = DOMAIN_RK3368("video", BIT(14), BIT(13), BIT(7), false),
|
||||
[RK3368_PD_GPU_0] = DOMAIN_RK3368("gpu_0", BIT(16), BIT(15), BIT(2), false),
|
||||
[RK3368_PD_GPU_1] = DOMAIN_RK3368("gpu_1", BIT(17), BIT(16), BIT(2), false),
|
||||
};
|
||||
|
||||
static const struct rockchip_domain_info rk3399_pm_domains[] = {
|
||||
[RK3399_PD_TCPD0] = DOMAIN_RK3399(BIT(8), BIT(8), 0, false),
|
||||
[RK3399_PD_TCPD1] = DOMAIN_RK3399(BIT(9), BIT(9), 0, false),
|
||||
[RK3399_PD_CCI] = DOMAIN_RK3399(BIT(10), BIT(10), 0, true),
|
||||
[RK3399_PD_CCI0] = DOMAIN_RK3399(0, 0, BIT(15), true),
|
||||
[RK3399_PD_CCI1] = DOMAIN_RK3399(0, 0, BIT(16), true),
|
||||
[RK3399_PD_PERILP] = DOMAIN_RK3399(BIT(11), BIT(11), BIT(1), true),
|
||||
[RK3399_PD_PERIHP] = DOMAIN_RK3399(BIT(12), BIT(12), BIT(2), true),
|
||||
[RK3399_PD_CENTER] = DOMAIN_RK3399(BIT(13), BIT(13), BIT(14), true),
|
||||
[RK3399_PD_VIO] = DOMAIN_RK3399(BIT(14), BIT(14), BIT(17), false),
|
||||
[RK3399_PD_GPU] = DOMAIN_RK3399(BIT(15), BIT(15), BIT(0), false),
|
||||
[RK3399_PD_VCODEC] = DOMAIN_RK3399(BIT(16), BIT(16), BIT(3), false),
|
||||
[RK3399_PD_VDU] = DOMAIN_RK3399(BIT(17), BIT(17), BIT(4), false),
|
||||
[RK3399_PD_RGA] = DOMAIN_RK3399(BIT(18), BIT(18), BIT(5), false),
|
||||
[RK3399_PD_IEP] = DOMAIN_RK3399(BIT(19), BIT(19), BIT(6), false),
|
||||
[RK3399_PD_VO] = DOMAIN_RK3399(BIT(20), BIT(20), 0, false),
|
||||
[RK3399_PD_VOPB] = DOMAIN_RK3399(0, 0, BIT(7), false),
|
||||
[RK3399_PD_VOPL] = DOMAIN_RK3399(0, 0, BIT(8), false),
|
||||
[RK3399_PD_ISP0] = DOMAIN_RK3399(BIT(22), BIT(22), BIT(9), false),
|
||||
[RK3399_PD_ISP1] = DOMAIN_RK3399(BIT(23), BIT(23), BIT(10), false),
|
||||
[RK3399_PD_HDCP] = DOMAIN_RK3399(BIT(24), BIT(24), BIT(11), false),
|
||||
[RK3399_PD_GMAC] = DOMAIN_RK3399(BIT(25), BIT(25), BIT(23), true),
|
||||
[RK3399_PD_EMMC] = DOMAIN_RK3399(BIT(26), BIT(26), BIT(24), true),
|
||||
[RK3399_PD_USB3] = DOMAIN_RK3399(BIT(27), BIT(27), BIT(12), true),
|
||||
[RK3399_PD_EDP] = DOMAIN_RK3399(BIT(28), BIT(28), BIT(22), false),
|
||||
[RK3399_PD_GIC] = DOMAIN_RK3399(BIT(29), BIT(29), BIT(27), true),
|
||||
[RK3399_PD_SD] = DOMAIN_RK3399(BIT(30), BIT(30), BIT(28), true),
|
||||
[RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399(BIT(31), BIT(31), BIT(29), true),
|
||||
[RK3399_PD_TCPD0] = DOMAIN_RK3399("tcpd0", BIT(8), BIT(8), 0, false),
|
||||
[RK3399_PD_TCPD1] = DOMAIN_RK3399("tcpd1", BIT(9), BIT(9), 0, false),
|
||||
[RK3399_PD_CCI] = DOMAIN_RK3399("cci", BIT(10), BIT(10), 0, true),
|
||||
[RK3399_PD_CCI0] = DOMAIN_RK3399("cci0", 0, 0, BIT(15), true),
|
||||
[RK3399_PD_CCI1] = DOMAIN_RK3399("cci1", 0, 0, BIT(16), true),
|
||||
[RK3399_PD_PERILP] = DOMAIN_RK3399("perilp", BIT(11), BIT(11), BIT(1), true),
|
||||
[RK3399_PD_PERIHP] = DOMAIN_RK3399("perihp", BIT(12), BIT(12), BIT(2), true),
|
||||
[RK3399_PD_CENTER] = DOMAIN_RK3399("center", BIT(13), BIT(13), BIT(14), true),
|
||||
[RK3399_PD_VIO] = DOMAIN_RK3399("vio", BIT(14), BIT(14), BIT(17), false),
|
||||
[RK3399_PD_GPU] = DOMAIN_RK3399("gpu", BIT(15), BIT(15), BIT(0), false),
|
||||
[RK3399_PD_VCODEC] = DOMAIN_RK3399("vcodec", BIT(16), BIT(16), BIT(3), false),
|
||||
[RK3399_PD_VDU] = DOMAIN_RK3399("vdu", BIT(17), BIT(17), BIT(4), false),
|
||||
[RK3399_PD_RGA] = DOMAIN_RK3399("rga", BIT(18), BIT(18), BIT(5), false),
|
||||
[RK3399_PD_IEP] = DOMAIN_RK3399("iep", BIT(19), BIT(19), BIT(6), false),
|
||||
[RK3399_PD_VO] = DOMAIN_RK3399("vo", BIT(20), BIT(20), 0, false),
|
||||
[RK3399_PD_VOPB] = DOMAIN_RK3399("vopb", 0, 0, BIT(7), false),
|
||||
[RK3399_PD_VOPL] = DOMAIN_RK3399("vopl", 0, 0, BIT(8), false),
|
||||
[RK3399_PD_ISP0] = DOMAIN_RK3399("isp0", BIT(22), BIT(22), BIT(9), false),
|
||||
[RK3399_PD_ISP1] = DOMAIN_RK3399("isp1", BIT(23), BIT(23), BIT(10), false),
|
||||
[RK3399_PD_HDCP] = DOMAIN_RK3399("hdcp", BIT(24), BIT(24), BIT(11), false),
|
||||
[RK3399_PD_GMAC] = DOMAIN_RK3399("gmac", BIT(25), BIT(25), BIT(23), true),
|
||||
[RK3399_PD_EMMC] = DOMAIN_RK3399("emmc", BIT(26), BIT(26), BIT(24), true),
|
||||
[RK3399_PD_USB3] = DOMAIN_RK3399("usb3", BIT(27), BIT(27), BIT(12), true),
|
||||
[RK3399_PD_EDP] = DOMAIN_RK3399("edp", BIT(28), BIT(28), BIT(22), false),
|
||||
[RK3399_PD_GIC] = DOMAIN_RK3399("gic", BIT(29), BIT(29), BIT(27), true),
|
||||
[RK3399_PD_SD] = DOMAIN_RK3399("sd", BIT(30), BIT(30), BIT(28), true),
|
||||
[RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true),
|
||||
};
|
||||
|
||||
static const struct rockchip_domain_info rk3568_pm_domains[] = {
|
||||
[RK3568_PD_NPU] = DOMAIN_RK3568("npu", BIT(1), BIT(2), false),
|
||||
[RK3568_PD_GPU] = DOMAIN_RK3568("gpu", BIT(0), BIT(1), false),
|
||||
[RK3568_PD_VI] = DOMAIN_RK3568("vi", BIT(6), BIT(3), false),
|
||||
[RK3568_PD_VO] = DOMAIN_RK3568("vo", BIT(7), BIT(4), false),
|
||||
[RK3568_PD_RGA] = DOMAIN_RK3568("rga", BIT(5), BIT(5), false),
|
||||
[RK3568_PD_VPU] = DOMAIN_RK3568("vpu", BIT(2), BIT(6), false),
|
||||
[RK3568_PD_RKVDEC] = DOMAIN_RK3568("vdec", BIT(4), BIT(8), false),
|
||||
[RK3568_PD_RKVENC] = DOMAIN_RK3568("venc", BIT(3), BIT(7), false),
|
||||
[RK3568_PD_PIPE] = DOMAIN_RK3568("pipe", BIT(8), BIT(11), false),
|
||||
};
|
||||
|
||||
static const struct rockchip_pmu_info px30_pmu = {
|
||||
|
|
@ -976,6 +999,17 @@ static const struct rockchip_pmu_info rk3399_pmu = {
|
|||
.domain_info = rk3399_pm_domains,
|
||||
};
|
||||
|
||||
static const struct rockchip_pmu_info rk3568_pmu = {
|
||||
.pwr_offset = 0xa0,
|
||||
.status_offset = 0x98,
|
||||
.req_offset = 0x50,
|
||||
.idle_offset = 0x68,
|
||||
.ack_offset = 0x60,
|
||||
|
||||
.num_domains = ARRAY_SIZE(rk3568_pm_domains),
|
||||
.domain_info = rk3568_pm_domains,
|
||||
};
|
||||
|
||||
static const struct of_device_id rockchip_pm_domain_dt_match[] = {
|
||||
{
|
||||
.compatible = "rockchip,px30-power-controller",
|
||||
|
|
@ -1021,6 +1055,10 @@ static const struct of_device_id rockchip_pm_domain_dt_match[] = {
|
|||
.compatible = "rockchip,rk3399-power-controller",
|
||||
.data = (void *)&rk3399_pmu,
|
||||
},
|
||||
{
|
||||
.compatible = "rockchip,rk3568-power-controller",
|
||||
.data = (void *)&rk3568_pmu,
|
||||
},
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,32 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __DT_BINDINGS_POWER_RK3568_POWER_H__
|
||||
#define __DT_BINDINGS_POWER_RK3568_POWER_H__
|
||||
|
||||
/* VD_CORE */
|
||||
#define RK3568_PD_CPU_0 0
|
||||
#define RK3568_PD_CPU_1 1
|
||||
#define RK3568_PD_CPU_2 2
|
||||
#define RK3568_PD_CPU_3 3
|
||||
#define RK3568_PD_CORE_ALIVE 4
|
||||
|
||||
/* VD_PMU */
|
||||
#define RK3568_PD_PMU 5
|
||||
|
||||
/* VD_NPU */
|
||||
#define RK3568_PD_NPU 6
|
||||
|
||||
/* VD_GPU */
|
||||
#define RK3568_PD_GPU 7
|
||||
|
||||
/* VD_LOGIC */
|
||||
#define RK3568_PD_VI 8
|
||||
#define RK3568_PD_VO 9
|
||||
#define RK3568_PD_RGA 10
|
||||
#define RK3568_PD_VPU 11
|
||||
#define RK3568_PD_CENTER 12
|
||||
#define RK3568_PD_RKVDEC 13
|
||||
#define RK3568_PD_RKVENC 14
|
||||
#define RK3568_PD_PIPE 15
|
||||
#define RK3568_PD_LOGIC_ALIVE 16
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue