mirror of https://gitee.com/openkylin/linux.git
ARM: tegra: clock: enable clk reset for non-peripheral clocks
Add a new 'reset' clk op. This can be provided for any clock, not just peripherals. Signed-off-by: Dima Zavin <dima@android.com> Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Colin Cross <ccross@android.com>
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@ -86,6 +86,7 @@ struct clk_ops {
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int (*set_parent)(struct clk *, struct clk *);
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int (*set_parent)(struct clk *, struct clk *);
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int (*set_rate)(struct clk *, unsigned long);
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int (*set_rate)(struct clk *, unsigned long);
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long (*round_rate)(struct clk *, unsigned long);
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long (*round_rate)(struct clk *, unsigned long);
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void (*reset)(struct clk *, bool);
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};
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};
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enum clk_state {
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enum clk_state {
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@ -263,6 +263,18 @@ static struct clk_ops tegra_clk_m_ops = {
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.disable = tegra2_clk_m_disable,
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.disable = tegra2_clk_m_disable,
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};
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};
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void tegra2_periph_reset_assert(struct clk *c)
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{
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BUG_ON(!c->ops->reset);
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c->ops->reset(c, true);
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}
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void tegra2_periph_reset_deassert(struct clk *c)
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{
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BUG_ON(!c->ops->reset);
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c->ops->reset(c, false);
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}
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/* super clock functions */
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/* super clock functions */
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/* "super clocks" on tegra have two-stage muxes and a clock skipping
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/* "super clocks" on tegra have two-stage muxes and a clock skipping
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* super divider. We will ignore the clock skipping divider, since we
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* super divider. We will ignore the clock skipping divider, since we
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@ -895,23 +907,17 @@ static void tegra2_periph_clk_disable(struct clk *c)
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CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
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CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
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}
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}
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void tegra2_periph_reset_deassert(struct clk *c)
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static void tegra2_periph_clk_reset(struct clk *c, bool assert)
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{
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{
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pr_debug("%s on clock %s\n", __func__, c->name);
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unsigned long base = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
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pr_debug("%s %s on clock %s\n", __func__,
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assert ? "assert" : "deassert", c->name);
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if (!(c->flags & PERIPH_NO_RESET))
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if (!(c->flags & PERIPH_NO_RESET))
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clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
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clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
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RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
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base + PERIPH_CLK_TO_ENB_SET_REG(c));
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}
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}
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void tegra2_periph_reset_assert(struct clk *c)
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{
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pr_debug("%s on clock %s\n", __func__, c->name);
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if (!(c->flags & PERIPH_NO_RESET))
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clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
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RST_DEVICES_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
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}
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static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p)
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static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p)
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{
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{
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u32 val;
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u32 val;
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@ -1002,6 +1008,7 @@ static struct clk_ops tegra_periph_clk_ops = {
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.set_parent = &tegra2_periph_clk_set_parent,
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.set_parent = &tegra2_periph_clk_set_parent,
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.set_rate = &tegra2_periph_clk_set_rate,
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.set_rate = &tegra2_periph_clk_set_rate,
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.round_rate = &tegra2_periph_clk_round_rate,
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.round_rate = &tegra2_periph_clk_round_rate,
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.reset = &tegra2_periph_clk_reset,
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};
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};
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/* Clock doubler ops */
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/* Clock doubler ops */
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