mirror of https://gitee.com/openkylin/linux.git
omap iommu: omap2 architecture specific functions
The structure 'arch_mmu' accommodates the difference between omap1 and omap2/3. This patch provides omap2/3 specific functions Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
This commit is contained in:
Hiroshi DOYU
parent
a9dcad5e37
commit
2bcb573343
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/*
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* omap iommu: omap2/3 architecture specific functions
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*
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* Copyright (C) 2008-2009 Nokia Corporation
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*
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* Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
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* Paul Mundt and Toshihiro Kobayashi
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/err.h>
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#include <linux/device.h>
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#include <linux/jiffies.h>
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#include <linux/module.h>
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#include <linux/stringify.h>
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#include <mach/iommu.h>
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/*
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* omap2 architecture specific register bit definitions
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*/
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#define IOMMU_ARCH_VERSION 0x00000011
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/* SYSCONF */
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#define MMU_SYS_IDLE_SHIFT 3
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#define MMU_SYS_IDLE_FORCE (0 << MMU_SYS_IDLE_SHIFT)
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#define MMU_SYS_IDLE_NONE (1 << MMU_SYS_IDLE_SHIFT)
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#define MMU_SYS_IDLE_SMART (2 << MMU_SYS_IDLE_SHIFT)
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#define MMU_SYS_IDLE_MASK (3 << MMU_SYS_IDLE_SHIFT)
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#define MMU_SYS_SOFTRESET (1 << 1)
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#define MMU_SYS_AUTOIDLE 1
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/* SYSSTATUS */
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#define MMU_SYS_RESETDONE 1
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/* IRQSTATUS & IRQENABLE */
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#define MMU_IRQ_MULTIHITFAULT (1 << 4)
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#define MMU_IRQ_TABLEWALKFAULT (1 << 3)
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#define MMU_IRQ_EMUMISS (1 << 2)
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#define MMU_IRQ_TRANSLATIONFAULT (1 << 1)
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#define MMU_IRQ_TLBMISS (1 << 0)
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#define MMU_IRQ_MASK \
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(MMU_IRQ_MULTIHITFAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_EMUMISS | \
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MMU_IRQ_TRANSLATIONFAULT)
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/* MMU_CNTL */
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#define MMU_CNTL_SHIFT 1
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#define MMU_CNTL_MASK (7 << MMU_CNTL_SHIFT)
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#define MMU_CNTL_EML_TLB (1 << 3)
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#define MMU_CNTL_TWL_EN (1 << 2)
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#define MMU_CNTL_MMU_EN (1 << 1)
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#define get_cam_va_mask(pgsz) \
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(((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 : \
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((pgsz) == MMU_CAM_PGSZ_1M) ? 0xfff00000 : \
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((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 : \
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((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0)
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static int omap2_iommu_enable(struct iommu *obj)
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{
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u32 l, pa;
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unsigned long timeout;
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if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd, SZ_16K))
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return -EINVAL;
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pa = virt_to_phys(obj->iopgd);
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if (!IS_ALIGNED(pa, SZ_16K))
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return -EINVAL;
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iommu_write_reg(obj, MMU_SYS_SOFTRESET, MMU_SYSCONFIG);
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timeout = jiffies + msecs_to_jiffies(20);
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do {
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l = iommu_read_reg(obj, MMU_SYSSTATUS);
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if (l & MMU_SYS_RESETDONE)
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break;
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} while (time_after(jiffies, timeout));
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if (!(l & MMU_SYS_RESETDONE)) {
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dev_err(obj->dev, "can't take mmu out of reset\n");
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return -ENODEV;
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}
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l = iommu_read_reg(obj, MMU_REVISION);
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dev_info(obj->dev, "%s: version %d.%d\n", obj->name,
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(l >> 4) & 0xf, l & 0xf);
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l = iommu_read_reg(obj, MMU_SYSCONFIG);
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l &= ~MMU_SYS_IDLE_MASK;
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l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE);
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iommu_write_reg(obj, l, MMU_SYSCONFIG);
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iommu_write_reg(obj, MMU_IRQ_MASK, MMU_IRQENABLE);
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iommu_write_reg(obj, pa, MMU_TTB);
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l = iommu_read_reg(obj, MMU_CNTL);
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l &= ~MMU_CNTL_MASK;
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l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN);
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iommu_write_reg(obj, l, MMU_CNTL);
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return 0;
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}
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static void omap2_iommu_disable(struct iommu *obj)
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{
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u32 l = iommu_read_reg(obj, MMU_CNTL);
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l &= ~MMU_CNTL_MASK;
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iommu_write_reg(obj, l, MMU_CNTL);
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iommu_write_reg(obj, MMU_SYS_IDLE_FORCE, MMU_SYSCONFIG);
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dev_dbg(obj->dev, "%s is shutting down\n", obj->name);
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}
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static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra)
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{
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int i;
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u32 stat, da;
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const char *err_msg[] = {
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"tlb miss",
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"translation fault",
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"emulation miss",
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"table walk fault",
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"multi hit fault",
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};
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stat = iommu_read_reg(obj, MMU_IRQSTATUS);
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stat &= MMU_IRQ_MASK;
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if (!stat)
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return 0;
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da = iommu_read_reg(obj, MMU_FAULT_AD);
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*ra = da;
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dev_err(obj->dev, "%s:\tda:%08x ", __func__, da);
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for (i = 0; i < ARRAY_SIZE(err_msg); i++) {
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if (stat & (1 << i))
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printk("%s ", err_msg[i]);
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}
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printk("\n");
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iommu_write_reg(obj, stat, MMU_IRQSTATUS);
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return stat;
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}
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static void omap2_tlb_read_cr(struct iommu *obj, struct cr_regs *cr)
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{
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cr->cam = iommu_read_reg(obj, MMU_READ_CAM);
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cr->ram = iommu_read_reg(obj, MMU_READ_RAM);
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}
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static void omap2_tlb_load_cr(struct iommu *obj, struct cr_regs *cr)
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{
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iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM);
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iommu_write_reg(obj, cr->ram, MMU_RAM);
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}
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static u32 omap2_cr_to_virt(struct cr_regs *cr)
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{
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u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK;
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u32 mask = get_cam_va_mask(cr->cam & page_size);
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return cr->cam & mask;
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}
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static struct cr_regs *omap2_alloc_cr(struct iommu *obj, struct iotlb_entry *e)
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{
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struct cr_regs *cr;
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if (e->da & ~(get_cam_va_mask(e->pgsz))) {
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dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__,
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e->da);
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return ERR_PTR(-EINVAL);
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}
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cr = kmalloc(sizeof(*cr), GFP_KERNEL);
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if (!cr)
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return ERR_PTR(-ENOMEM);
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cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz;
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cr->ram = e->pa | e->endian | e->elsz | e->mixed;
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return cr;
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}
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static inline int omap2_cr_valid(struct cr_regs *cr)
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{
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return cr->cam & MMU_CAM_V;
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}
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static u32 omap2_get_pte_attr(struct iotlb_entry *e)
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{
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u32 attr;
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attr = e->mixed << 5;
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attr |= e->endian;
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attr |= e->elsz >> 3;
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attr <<= ((e->pgsz & MMU_CAM_PGSZ_4K) ? 0 : 6);
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return attr;
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}
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static ssize_t omap2_dump_cr(struct iommu *obj, struct cr_regs *cr, char *buf)
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{
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char *p = buf;
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/* FIXME: Need more detail analysis of cam/ram */
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p += sprintf(p, "%08x %08x\n", cr->cam, cr->ram);
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return p - buf;
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}
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#define pr_reg(name) \
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p += sprintf(p, "%20s: %08x\n", \
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__stringify(name), iommu_read_reg(obj, MMU_##name));
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static ssize_t omap2_iommu_dump_ctx(struct iommu *obj, char *buf)
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{
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char *p = buf;
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pr_reg(REVISION);
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pr_reg(SYSCONFIG);
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pr_reg(SYSSTATUS);
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pr_reg(IRQSTATUS);
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pr_reg(IRQENABLE);
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pr_reg(WALKING_ST);
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pr_reg(CNTL);
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pr_reg(FAULT_AD);
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pr_reg(TTB);
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pr_reg(LOCK);
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pr_reg(LD_TLB);
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pr_reg(CAM);
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pr_reg(RAM);
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pr_reg(GFLUSH);
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pr_reg(FLUSH_ENTRY);
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pr_reg(READ_CAM);
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pr_reg(READ_RAM);
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pr_reg(EMU_FAULT_AD);
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return p - buf;
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}
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static void omap2_iommu_save_ctx(struct iommu *obj)
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{
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int i;
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u32 *p = obj->ctx;
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for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
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p[i] = iommu_read_reg(obj, i * sizeof(u32));
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dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
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}
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BUG_ON(p[0] != IOMMU_ARCH_VERSION);
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}
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static void omap2_iommu_restore_ctx(struct iommu *obj)
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{
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int i;
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u32 *p = obj->ctx;
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for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
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iommu_write_reg(obj, p[i], i * sizeof(u32));
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dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
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}
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BUG_ON(p[0] != IOMMU_ARCH_VERSION);
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}
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static void omap2_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e)
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{
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e->da = cr->cam & MMU_CAM_VATAG_MASK;
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e->pa = cr->ram & MMU_RAM_PADDR_MASK;
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e->valid = cr->cam & MMU_CAM_V;
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e->pgsz = cr->cam & MMU_CAM_PGSZ_MASK;
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e->endian = cr->ram & MMU_RAM_ENDIAN_MASK;
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e->elsz = cr->ram & MMU_RAM_ELSZ_MASK;
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e->mixed = cr->ram & MMU_RAM_MIXED;
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}
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static const struct iommu_functions omap2_iommu_ops = {
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.version = IOMMU_ARCH_VERSION,
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.enable = omap2_iommu_enable,
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.disable = omap2_iommu_disable,
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.fault_isr = omap2_iommu_fault_isr,
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.tlb_read_cr = omap2_tlb_read_cr,
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.tlb_load_cr = omap2_tlb_load_cr,
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.cr_to_e = omap2_cr_to_e,
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.cr_to_virt = omap2_cr_to_virt,
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.alloc_cr = omap2_alloc_cr,
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.cr_valid = omap2_cr_valid,
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.dump_cr = omap2_dump_cr,
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.get_pte_attr = omap2_get_pte_attr,
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.save_ctx = omap2_iommu_save_ctx,
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.restore_ctx = omap2_iommu_restore_ctx,
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.dump_ctx = omap2_iommu_dump_ctx,
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};
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static int __init omap2_iommu_init(void)
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{
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return install_iommu_arch(&omap2_iommu_ops);
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}
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module_init(omap2_iommu_init);
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static void __exit omap2_iommu_exit(void)
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{
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uninstall_iommu_arch(&omap2_iommu_ops);
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}
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module_exit(omap2_iommu_exit);
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MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi");
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MODULE_DESCRIPTION("omap iommu: omap2/3 architecture specific functions");
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MODULE_LICENSE("GPL v2");
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@ -0,0 +1,96 @@
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/*
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* omap iommu: omap2 architecture specific definitions
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*
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* Copyright (C) 2008-2009 Nokia Corporation
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*
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* Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __MACH_IOMMU2_H
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#define __MACH_IOMMU2_H
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#include <linux/io.h>
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/*
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* MMU Register offsets
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*/
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#define MMU_REVISION 0x00
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#define MMU_SYSCONFIG 0x10
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#define MMU_SYSSTATUS 0x14
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#define MMU_IRQSTATUS 0x18
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#define MMU_IRQENABLE 0x1c
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#define MMU_WALKING_ST 0x40
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#define MMU_CNTL 0x44
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#define MMU_FAULT_AD 0x48
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#define MMU_TTB 0x4c
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#define MMU_LOCK 0x50
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#define MMU_LD_TLB 0x54
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#define MMU_CAM 0x58
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#define MMU_RAM 0x5c
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#define MMU_GFLUSH 0x60
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#define MMU_FLUSH_ENTRY 0x64
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#define MMU_READ_CAM 0x68
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#define MMU_READ_RAM 0x6c
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#define MMU_EMU_FAULT_AD 0x70
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#define MMU_REG_SIZE 256
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/*
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* MMU Register bit definitions
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*/
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#define MMU_LOCK_BASE_SHIFT 10
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#define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT)
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#define MMU_LOCK_BASE(x) \
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((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT)
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#define MMU_LOCK_VICT_SHIFT 4
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#define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT)
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#define MMU_LOCK_VICT(x) \
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((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT)
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#define MMU_CAM_VATAG_SHIFT 12
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#define MMU_CAM_VATAG_MASK \
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((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
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#define MMU_CAM_P (1 << 3)
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#define MMU_CAM_V (1 << 2)
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#define MMU_CAM_PGSZ_MASK 3
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#define MMU_CAM_PGSZ_1M (0 << 0)
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#define MMU_CAM_PGSZ_64K (1 << 0)
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#define MMU_CAM_PGSZ_4K (2 << 0)
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#define MMU_CAM_PGSZ_16M (3 << 0)
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#define MMU_RAM_PADDR_SHIFT 12
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#define MMU_RAM_PADDR_MASK \
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((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)
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#define MMU_RAM_ENDIAN_SHIFT 9
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#define MMU_RAM_ENDIAN_MASK (1 << MMU_RAM_ENDIAN_SHIFT)
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#define MMU_RAM_ENDIAN_BIG (1 << MMU_RAM_ENDIAN_SHIFT)
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#define MMU_RAM_ENDIAN_LITTLE (0 << MMU_RAM_ENDIAN_SHIFT)
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#define MMU_RAM_ELSZ_SHIFT 7
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#define MMU_RAM_ELSZ_MASK (3 << MMU_RAM_ELSZ_SHIFT)
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#define MMU_RAM_ELSZ_8 (0 << MMU_RAM_ELSZ_SHIFT)
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#define MMU_RAM_ELSZ_16 (1 << MMU_RAM_ELSZ_SHIFT)
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#define MMU_RAM_ELSZ_32 (2 << MMU_RAM_ELSZ_SHIFT)
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#define MMU_RAM_ELSZ_NONE (3 << MMU_RAM_ELSZ_SHIFT)
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#define MMU_RAM_MIXED_SHIFT 6
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#define MMU_RAM_MIXED_MASK (1 << MMU_RAM_MIXED_SHIFT)
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#define MMU_RAM_MIXED MMU_RAM_MIXED_MASK
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/*
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* register accessors
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*/
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static inline u32 iommu_read_reg(struct iommu *obj, size_t offs)
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{
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return __raw_readl(obj->regbase + offs);
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}
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static inline void iommu_write_reg(struct iommu *obj, u32 val, size_t offs)
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{
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__raw_writel(val, obj->regbase + offs);
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}
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#endif /* __MACH_IOMMU2_H */
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