mirror of https://gitee.com/openkylin/linux.git
drm/amd/powerplay: add function to set default overdrive settings
Add function of vega20_set_default_od8_setttings for vega20 with smu11 arch to setup default overdrive value. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Likun Gao
Alex Deucher
parent
b55ca3bdaf
commit
2c80abe381
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@ -533,6 +533,10 @@ static int smu_smc_table_hw_init(struct smu_context *smu)
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if (ret)
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return ret;
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ret = smu_set_od8_default_settings(smu);
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if (ret)
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return ret;
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ret = smu_populate_umd_state_clk(smu);
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if (ret)
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return ret;
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@ -704,6 +708,16 @@ static int smu_hw_fini(void *handle)
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table_context->od_settings_min = NULL;
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}
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if (table_context->overdrive_table) {
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kfree(table_context->overdrive_table);
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table_context->overdrive_table = NULL;
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}
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if (table_context->od8_settings) {
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kfree(table_context->od8_settings);
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table_context->od8_settings = NULL;
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}
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ret = smu_fini_fb_allocations(smu);
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if (ret)
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return ret;
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@ -196,6 +196,8 @@ struct smu_table_context
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uint8_t *od_feature_capabilities;
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uint32_t *od_settings_max;
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uint32_t *od_settings_min;
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void *overdrive_table;
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void *od8_settings;
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};
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struct smu_dpm_context {
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@ -258,6 +260,7 @@ struct pptable_funcs {
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int (*populate_umd_state_clk)(struct smu_context *smu);
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int (*print_clk_levels)(struct smu_context *smu, enum pp_clock_type type, char *buf);
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int (*force_clk_levels)(struct smu_context *smu, enum pp_clock_type type, uint32_t mask);
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int (*set_default_od8_settings)(struct smu_context *smu);
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int (*get_clock_by_type_with_latency)(struct smu_context *smu,
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enum amd_pp_clock_type type,
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struct
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@ -331,6 +334,7 @@ struct smu_funcs
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int (*notify_smu_enable_pwe)(struct smu_context *smu);
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int (*set_watermarks_for_clock_ranges)(struct smu_context *smu,
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struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
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int (*set_od8_default_settings)(struct smu_context *smu);
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};
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#define smu_init_microcode(smu) \
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@ -377,6 +381,8 @@ struct smu_funcs
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((smu)->funcs->system_features_control ? (smu)->funcs->system_features_control((smu), (en)) : 0)
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#define smu_init_max_sustainable_clocks(smu) \
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((smu)->funcs->init_max_sustainable_clocks ? (smu)->funcs->init_max_sustainable_clocks((smu)) : 0)
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#define smu_set_od8_default_settings(smu) \
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((smu)->funcs->set_od8_default_settings ? (smu)->funcs->set_od8_default_settings((smu)) : 0)
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#define smu_send_smc_msg(smu, msg) \
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((smu)->funcs->send_smc_msg? (smu)->funcs->send_smc_msg((smu), (msg)) : 0)
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#define smu_send_smc_msg_with_param(smu, msg, param) \
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@ -407,6 +413,8 @@ struct smu_funcs
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((smu)->ppt_funcs->set_default_dpm_table ? (smu)->ppt_funcs->set_default_dpm_table((smu)) : 0)
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#define smu_populate_umd_state_clk(smu) \
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((smu)->ppt_funcs->populate_umd_state_clk ? (smu)->ppt_funcs->populate_umd_state_clk((smu)) : 0)
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#define smu_set_default_od8_settings(smu) \
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((smu)->ppt_funcs->set_default_od8_settings ? (smu)->ppt_funcs->set_default_od8_settings((smu)) : 0)
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#define smu_get_power_limit(smu) \
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((smu)->funcs->get_power_limit? (smu)->funcs->get_power_limit((smu)) : 0)
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#define smu_get_current_clk_freq(smu, clk_id, value) \
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@ -542,61 +542,12 @@ static int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
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return ret;
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}
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static int smu_v11_0_copy_table_to_smc(struct smu_context *smu,
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uint32_t table_id)
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{
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struct smu_table_context *table_context = &smu->smu_table;
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struct smu_table *driver_pptable = &smu->smu_table.tables[table_id];
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int ret = 0;
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if (table_id >= TABLE_COUNT) {
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pr_err("Invalid SMU Table ID for smu11!");
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return -EINVAL;
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}
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if (!driver_pptable->cpu_addr) {
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pr_err("Invalid virtual address for smu11!");
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return -EINVAL;
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}
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if (!driver_pptable->mc_address) {
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pr_err("Invalid MC address for smu11!");
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return -EINVAL;
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}
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if (!driver_pptable->size) {
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pr_err("Invalid SMU Table size for smu11!");
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return -EINVAL;
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}
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memcpy(driver_pptable->cpu_addr, table_context->driver_pptable,
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driver_pptable->size);
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ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetDriverDramAddrHigh,
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upper_32_bits(driver_pptable->mc_address));
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if (ret) {
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pr_err("[CopyTableToSMC] Attempt to Set Dram Addr High Failed!");
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return ret;
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}
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ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetDriverDramAddrLow,
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lower_32_bits(driver_pptable->mc_address));
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if (ret) {
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pr_err("[CopyTableToSMC] Attempt to Set Dram Addr Low Failed!");
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return ret;
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}
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ret = smu_send_smc_msg_with_param(smu, SMU_MSG_TransferTableDram2Smu,
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table_id);
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if (ret) {
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pr_err("[CopyTableToSMC] Attempt to Transfer Table To SMU Failed!");
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return ret;
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}
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return 0;
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}
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static int smu_v11_0_write_pptable(struct smu_context *smu)
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{
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struct smu_table_context *table_context = &smu->smu_table;
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int ret = 0;
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ret = smu_v11_0_copy_table_to_smc(smu, TABLE_PPTABLE);
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ret = smu_update_table(smu, TABLE_PPTABLE, table_context->driver_pptable, true);
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return ret;
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}
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@ -1246,6 +1197,36 @@ smu_v11_0_set_watermarks_for_clock_ranges(struct smu_context *smu, struct
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return ret;
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}
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static int smu_v11_0_set_od8_default_settings(struct smu_context *smu)
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{
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struct smu_table_context *table_context = &smu->smu_table;
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int ret;
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if (table_context->overdrive_table)
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return -EINVAL;
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table_context->overdrive_table = kzalloc(sizeof(OverDriveTable_t), GFP_KERNEL);
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if (!table_context->overdrive_table)
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return -ENOMEM;
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ret = smu_update_table(smu, TABLE_OVERDRIVE, table_context->overdrive_table, false);
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if (ret) {
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pr_err("Failed to export over drive table!\n");
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return ret;
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}
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smu_set_default_od8_settings(smu);
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ret = smu_update_table(smu, TABLE_OVERDRIVE, table_context->overdrive_table, true);
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if (ret) {
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pr_err("Failed to import over drive table!\n");
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return ret;
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}
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return 0;
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}
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static const struct smu_funcs smu_v11_0_funcs = {
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.init_microcode = smu_v11_0_init_microcode,
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.load_microcode = smu_v11_0_load_microcode,
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@ -1282,6 +1263,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
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.set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
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.display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
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.set_watermarks_for_clock_ranges = smu_v11_0_set_watermarks_for_clock_ranges,
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.set_od8_default_settings = smu_v11_0_set_od8_default_settings,
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};
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void smu_v11_0_set_smu_funcs(struct smu_context *smu)
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@ -904,6 +904,208 @@ static int vega20_get_clock_by_type_with_latency(struct smu_context *smu,
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return ret;
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}
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static int vega20_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu,
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uint32_t *voltage,
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uint32_t freq)
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{
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int ret;
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ret = smu_send_smc_msg_with_param(smu,
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SMU_MSG_GetAVFSVoltageByDpm,
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((AVFS_CURVE << 24) | (OD8_HOTCURVE_TEMPERATURE << 16) | freq));
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if (ret) {
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pr_err("[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!");
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return ret;
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}
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smu_read_smc_arg(smu, voltage);
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*voltage = *voltage / VOLTAGE_SCALE;
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return 0;
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}
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static int vega20_set_default_od8_setttings(struct smu_context *smu)
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{
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struct smu_table_context *table_context = &smu->smu_table;
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OverDriveTable_t *od_table = (OverDriveTable_t *)(table_context->overdrive_table);
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struct vega20_od8_settings *od8_settings = NULL;
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PPTable_t *smc_pptable = table_context->driver_pptable;
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int i, ret;
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if (table_context->od8_settings)
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return -EINVAL;
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table_context->od8_settings = kzalloc(sizeof(struct vega20_od8_settings), GFP_KERNEL);
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if (!table_context->od8_settings)
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return -ENOMEM;
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memset(table_context->od8_settings, 0, sizeof(struct vega20_od8_settings));
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od8_settings = (struct vega20_od8_settings *)table_context->od8_settings;
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if (smu_feature_is_enabled(smu, FEATURE_DPM_SOCCLK_BIT)) {
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if (table_context->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS] &&
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table_context->od_settings_max[OD8_SETTING_GFXCLK_FMAX] > 0 &&
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table_context->od_settings_min[OD8_SETTING_GFXCLK_FMIN] > 0 &&
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(table_context->od_settings_max[OD8_SETTING_GFXCLK_FMAX] >=
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table_context->od_settings_min[OD8_SETTING_GFXCLK_FMIN])) {
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od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
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OD8_GFXCLK_LIMITS;
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od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
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OD8_GFXCLK_LIMITS;
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od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
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od_table->GfxclkFmin;
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od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
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od_table->GfxclkFmax;
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}
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if (table_context->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_CURVE] &&
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(table_context->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] >=
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smc_pptable->MinVoltageGfx / VOLTAGE_SCALE) &&
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(table_context->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] <=
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smc_pptable->MaxVoltageGfx / VOLTAGE_SCALE) &&
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(table_context->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] <=
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table_context->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3])) {
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od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
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OD8_GFXCLK_CURVE;
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od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
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OD8_GFXCLK_CURVE;
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od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
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OD8_GFXCLK_CURVE;
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od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
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OD8_GFXCLK_CURVE;
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od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
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OD8_GFXCLK_CURVE;
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od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
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OD8_GFXCLK_CURVE;
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od_table->GfxclkFreq1 = od_table->GfxclkFmin;
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od_table->GfxclkFreq2 = (od_table->GfxclkFmin + od_table->GfxclkFmax) / 2;
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od_table->GfxclkFreq3 = od_table->GfxclkFmax;
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od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
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od_table->GfxclkFreq1;
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od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
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od_table->GfxclkFreq2;
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od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
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od_table->GfxclkFreq3;
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ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
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&od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value,
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od_table->GfxclkFreq1);
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if (ret)
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od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value = 0;
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od_table->GfxclkVolt1 =
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od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value
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* VOLTAGE_SCALE;
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ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
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&od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value,
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od_table->GfxclkFreq2);
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if (ret)
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od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value = 0;
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od_table->GfxclkVolt2 =
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od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value
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* VOLTAGE_SCALE;
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ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
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&od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value,
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od_table->GfxclkFreq3);
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if (ret)
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od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value = 0;
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od_table->GfxclkVolt3 =
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od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value
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* VOLTAGE_SCALE;
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}
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}
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if (smu_feature_is_enabled(smu, FEATURE_DPM_UCLK_BIT)) {
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if (table_context->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_UCLK_MAX] &&
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table_context->od_settings_min[OD8_SETTING_UCLK_FMAX] > 0 &&
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table_context->od_settings_max[OD8_SETTING_UCLK_FMAX] > 0 &&
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(table_context->od_settings_max[OD8_SETTING_UCLK_FMAX] >=
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table_context->od_settings_min[OD8_SETTING_UCLK_FMAX])) {
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od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id =
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OD8_UCLK_MAX;
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od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
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od_table->UclkFmax;
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}
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}
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if (table_context->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_POWER_LIMIT] &&
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table_context->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
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table_context->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] <= 100 &&
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table_context->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
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table_context->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] <= 100) {
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od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id =
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OD8_POWER_LIMIT;
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od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
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od_table->OverDrivePct;
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}
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if (smu_feature_is_enabled(smu, FEATURE_FAN_CONTROL_BIT)) {
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if (table_context->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ACOUSTIC_LIMIT] &&
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table_context->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
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table_context->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
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(table_context->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] >=
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table_context->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT])) {
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od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
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OD8_ACOUSTIC_LIMIT_SCLK;
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od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
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od_table->FanMaximumRpm;
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}
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if (table_context->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_SPEED_MIN] &&
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table_context->od_settings_min[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
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table_context->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
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(table_context->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] >=
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table_context->od_settings_min[OD8_SETTING_FAN_MIN_SPEED])) {
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od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
|
||||
OD8_FAN_SPEED_MIN;
|
||||
od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
|
||||
od_table->FanMinimumPwm * smc_pptable->FanMaximumRpm / 100;
|
||||
}
|
||||
}
|
||||
|
||||
if (smu_feature_is_enabled(smu, FEATURE_THERMAL_BIT)) {
|
||||
if (table_context->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_FAN] &&
|
||||
table_context->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
|
||||
table_context->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
|
||||
(table_context->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] >=
|
||||
table_context->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP])) {
|
||||
od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
|
||||
OD8_TEMPERATURE_FAN;
|
||||
od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
|
||||
od_table->FanTargetTemperature;
|
||||
}
|
||||
|
||||
if (table_context->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_SYSTEM] &&
|
||||
table_context->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
|
||||
table_context->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
|
||||
(table_context->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] >=
|
||||
table_context->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX])) {
|
||||
od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
|
||||
OD8_TEMPERATURE_SYSTEM;
|
||||
od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
|
||||
od_table->MaxOpTemp;
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < OD8_SETTING_COUNT; i++) {
|
||||
if (od8_settings->od8_settings_array[i].feature_id) {
|
||||
od8_settings->od8_settings_array[i].min_value =
|
||||
table_context->od_settings_min[i];
|
||||
od8_settings->od8_settings_array[i].max_value =
|
||||
table_context->od_settings_max[i];
|
||||
od8_settings->od8_settings_array[i].current_value =
|
||||
od8_settings->od8_settings_array[i].default_value;
|
||||
} else {
|
||||
od8_settings->od8_settings_array[i].min_value = 0;
|
||||
od8_settings->od8_settings_array[i].max_value = 0;
|
||||
od8_settings->od8_settings_array[i].current_value = 0;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct pptable_funcs vega20_ppt_funcs = {
|
||||
.alloc_dpm_context = vega20_allocate_dpm_context,
|
||||
.store_powerplay_table = vega20_store_powerplay_table,
|
||||
|
|
@ -917,6 +1119,7 @@ static const struct pptable_funcs vega20_ppt_funcs = {
|
|||
.print_clk_levels = vega20_print_clk_levels,
|
||||
.force_clk_levels = vega20_force_clk_levels,
|
||||
.get_clock_by_type_with_latency = vega20_get_clock_by_type_with_latency,
|
||||
.set_default_od8_settings = vega20_set_default_od8_setttings,
|
||||
};
|
||||
|
||||
void vega20_set_ppt_funcs(struct smu_context *smu)
|
||||
|
|
|
|||
|
|
@ -29,6 +29,10 @@
|
|||
#define MAX_REGULAR_DPM_NUMBER 16
|
||||
#define MAX_PCIE_CONF 2
|
||||
|
||||
#define VOLTAGE_SCALE 4
|
||||
#define AVFS_CURVE 0
|
||||
#define OD8_HOTCURVE_TEMPERATURE 85
|
||||
|
||||
struct vega20_dpm_level {
|
||||
bool enabled;
|
||||
uint32_t value;
|
||||
|
|
@ -70,6 +74,53 @@ struct vega20_dpm_table {
|
|||
struct vega20_pcie_table pcie_table;
|
||||
};
|
||||
|
||||
enum OD8_FEATURE_ID
|
||||
{
|
||||
OD8_GFXCLK_LIMITS = 1 << 0,
|
||||
OD8_GFXCLK_CURVE = 1 << 1,
|
||||
OD8_UCLK_MAX = 1 << 2,
|
||||
OD8_POWER_LIMIT = 1 << 3,
|
||||
OD8_ACOUSTIC_LIMIT_SCLK = 1 << 4, //FanMaximumRpm
|
||||
OD8_FAN_SPEED_MIN = 1 << 5, //FanMinimumPwm
|
||||
OD8_TEMPERATURE_FAN = 1 << 6, //FanTargetTemperature
|
||||
OD8_TEMPERATURE_SYSTEM = 1 << 7, //MaxOpTemp
|
||||
OD8_MEMORY_TIMING_TUNE = 1 << 8,
|
||||
OD8_FAN_ZERO_RPM_CONTROL = 1 << 9
|
||||
};
|
||||
|
||||
enum OD8_SETTING_ID
|
||||
{
|
||||
OD8_SETTING_GFXCLK_FMIN = 0,
|
||||
OD8_SETTING_GFXCLK_FMAX,
|
||||
OD8_SETTING_GFXCLK_FREQ1,
|
||||
OD8_SETTING_GFXCLK_VOLTAGE1,
|
||||
OD8_SETTING_GFXCLK_FREQ2,
|
||||
OD8_SETTING_GFXCLK_VOLTAGE2,
|
||||
OD8_SETTING_GFXCLK_FREQ3,
|
||||
OD8_SETTING_GFXCLK_VOLTAGE3,
|
||||
OD8_SETTING_UCLK_FMAX,
|
||||
OD8_SETTING_POWER_PERCENTAGE,
|
||||
OD8_SETTING_FAN_ACOUSTIC_LIMIT,
|
||||
OD8_SETTING_FAN_MIN_SPEED,
|
||||
OD8_SETTING_FAN_TARGET_TEMP,
|
||||
OD8_SETTING_OPERATING_TEMP_MAX,
|
||||
OD8_SETTING_AC_TIMING,
|
||||
OD8_SETTING_FAN_ZERO_RPM_CONTROL,
|
||||
OD8_SETTING_COUNT
|
||||
};
|
||||
|
||||
struct vega20_od8_single_setting {
|
||||
uint32_t feature_id;
|
||||
int32_t min_value;
|
||||
int32_t max_value;
|
||||
int32_t current_value;
|
||||
int32_t default_value;
|
||||
};
|
||||
|
||||
struct vega20_od8_settings {
|
||||
struct vega20_od8_single_setting od8_settings_array[OD8_SETTING_COUNT];
|
||||
};
|
||||
|
||||
extern void vega20_set_ppt_funcs(struct smu_context *smu);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue