mirror of https://gitee.com/openkylin/linux.git
drm/i915/bxt: Add GEN9_CS_DEBUG_MODE1 to HW whitelist
Required for, WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt WaDisableObjectLevelPreemptionForInstancedDraw:bxt WaDisableObjectLevelPreemtionForInstanceId:bxt According to WA database these are only applicable for BXT:A0 but since A0 and A1 shares the same GT these are extended for A1 as well. These are also required for SKL until B0 but not adding them because they are pre-production steppings. This register is added to HW whitelist to support WA required for future enabling of pre-emptive command execution, WA implementation will be in userspace and it cannot program this register if it is not on HW whitelist. v2: use lower case in register defines (Nick) v3: explain purpose of changes (Chris) Reviewed-by: Nick Hoath <nicholas.hoath@intel.com> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1453412634-29238-5-git-send-email-arun.siluvery@linux.intel.com Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -5998,6 +5998,7 @@ enum skl_disp_power_wells {
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#define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4)
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#define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8)
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#define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
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#define GEN8_CS_CHICKEN1 _MMIO(0x2580)
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/* GEN7 chicken */
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@ -1133,6 +1133,15 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
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GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
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}
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/* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
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/* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
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/* WaDisableObjectLevelPreemtionForInstanceId:bxt */
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if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
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ret = wa_ring_whitelist_reg(ring, GEN9_CS_DEBUG_MODE1);
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if (ret)
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return ret;
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}
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return 0;
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}
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