mirror of https://gitee.com/openkylin/linux.git
MIPS: Optimize TLB handlers for Octeon CPUs
Octeon can use scratch registers in the TLB handlers. Octeon II can use LDX instructions. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1904/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
David Daney
Ralf Baechle
parent
bb3d68c30a
commit
2c8c53e28f
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@ -77,6 +77,40 @@ static int use_bbit_insns(void)
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}
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}
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static int use_lwx_insns(void)
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{
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switch (current_cpu_type()) {
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case CPU_CAVIUM_OCTEON2:
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return 1;
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default:
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return 0;
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}
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}
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#if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \
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CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
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static bool scratchpad_available(void)
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{
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return true;
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}
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static int scratchpad_offset(int i)
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{
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/*
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* CVMSEG starts at address -32768 and extends for
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* CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines.
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*/
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i += 1; /* Kernel use starts at the top and works down. */
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return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768;
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}
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#else
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static bool scratchpad_available(void)
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{
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return false;
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}
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static int scratchpad_offset(int i)
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{
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BUG();
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}
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#endif
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/*
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* Found by experiment: At least some revisions of the 4kc throw under
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* some circumstances a machine check exception, triggered by invalid
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@ -187,7 +221,7 @@ static struct uasm_reloc relocs[128] __cpuinitdata;
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static int check_for_high_segbits __cpuinitdata;
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#endif
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#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
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static int check_for_high_segbits __cpuinitdata;
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static unsigned int kscratch_used_mask __cpuinitdata;
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@ -208,9 +242,12 @@ static int __cpuinit allocate_kscratch(void)
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return r;
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}
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static int scratch_reg __cpuinitdata;
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static int pgd_reg __cpuinitdata;
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enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch};
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#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
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#else /* !CONFIG_MIPS_PGD_C0_CONTEXT*/
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/*
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* CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current,
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* we cannot do r3000 under these circumstances.
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@ -481,21 +518,43 @@ static __cpuinit __maybe_unused void build_convert_pte_to_entrylo(u32 **p,
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static __cpuinit void build_restore_pagemask(u32 **p,
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struct uasm_reloc **r,
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unsigned int tmp,
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enum label_id lid)
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enum label_id lid,
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int restore_scratch)
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{
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/* Reset default page size */
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if (PM_DEFAULT_MASK >> 16) {
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uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
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uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
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uasm_il_b(p, r, lid);
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uasm_i_mtc0(p, tmp, C0_PAGEMASK);
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} else if (PM_DEFAULT_MASK) {
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uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
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uasm_il_b(p, r, lid);
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uasm_i_mtc0(p, tmp, C0_PAGEMASK);
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if (restore_scratch) {
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/* Reset default page size */
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if (PM_DEFAULT_MASK >> 16) {
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uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
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uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
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uasm_i_mtc0(p, tmp, C0_PAGEMASK);
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uasm_il_b(p, r, lid);
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} else if (PM_DEFAULT_MASK) {
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uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
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uasm_i_mtc0(p, tmp, C0_PAGEMASK);
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uasm_il_b(p, r, lid);
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} else {
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uasm_i_mtc0(p, 0, C0_PAGEMASK);
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uasm_il_b(p, r, lid);
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}
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if (scratch_reg > 0)
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UASM_i_MFC0(p, 1, 31, scratch_reg);
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else
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UASM_i_LW(p, 1, scratchpad_offset(0), 0);
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} else {
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uasm_il_b(p, r, lid);
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uasm_i_mtc0(p, 0, C0_PAGEMASK);
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/* Reset default page size */
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if (PM_DEFAULT_MASK >> 16) {
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uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
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uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
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uasm_il_b(p, r, lid);
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uasm_i_mtc0(p, tmp, C0_PAGEMASK);
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} else if (PM_DEFAULT_MASK) {
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uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
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uasm_il_b(p, r, lid);
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uasm_i_mtc0(p, tmp, C0_PAGEMASK);
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} else {
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uasm_il_b(p, r, lid);
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uasm_i_mtc0(p, 0, C0_PAGEMASK);
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}
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}
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}
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@ -503,7 +562,8 @@ static __cpuinit void build_huge_tlb_write_entry(u32 **p,
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struct uasm_label **l,
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struct uasm_reloc **r,
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unsigned int tmp,
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enum tlb_write_entry wmode)
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enum tlb_write_entry wmode,
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int restore_scratch)
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{
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/* Set huge page tlb entry size */
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uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16);
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@ -512,7 +572,7 @@ static __cpuinit void build_huge_tlb_write_entry(u32 **p,
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build_tlb_write_entry(p, l, r, wmode);
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build_restore_pagemask(p, r, tmp, label_leave);
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build_restore_pagemask(p, r, tmp, label_leave, restore_scratch);
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}
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/*
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@ -577,7 +637,7 @@ static __cpuinit void build_huge_handler_tail(u32 **p,
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UASM_i_SW(p, pte, 0, ptr);
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#endif
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build_huge_update_entries(p, pte, ptr);
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build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed);
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build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed, 0);
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}
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#endif /* CONFIG_HUGETLB_PAGE */
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@ -674,7 +734,6 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
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#endif
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}
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enum vmalloc64_mode {not_refill, refill};
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/*
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* BVADDR is the faulting address, PTR is scratch.
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* PTR will hold the pgd for vmalloc.
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@ -692,7 +751,7 @@ build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
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uasm_l_vmalloc(l, *p);
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if (mode == refill && check_for_high_segbits) {
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if (mode != not_refill && check_for_high_segbits) {
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if (single_insn_swpd) {
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uasm_il_bltz(p, r, bvaddr, label_vmalloc_done);
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uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
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@ -715,7 +774,7 @@ build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
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uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd));
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}
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}
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if (mode == refill && check_for_high_segbits) {
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if (mode != not_refill && check_for_high_segbits) {
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uasm_l_large_segbits_fault(l, *p);
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/*
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* We get here if we are an xsseg address, or if we are
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@ -731,7 +790,15 @@ build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
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*/
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UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0);
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uasm_i_jr(p, ptr);
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uasm_i_nop(p);
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if (mode == refill_scratch) {
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if (scratch_reg > 0)
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UASM_i_MFC0(p, 1, 31, scratch_reg);
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else
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UASM_i_LW(p, 1, scratchpad_offset(0), 0);
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} else {
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uasm_i_nop(p);
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}
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}
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}
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@ -888,6 +955,185 @@ static void __cpuinit build_update_entries(u32 **p, unsigned int tmp,
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#endif
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}
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struct mips_huge_tlb_info {
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int huge_pte;
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int restore_scratch;
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};
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static struct mips_huge_tlb_info __cpuinit
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build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l,
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struct uasm_reloc **r, unsigned int tmp,
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unsigned int ptr, int c0_scratch)
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{
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struct mips_huge_tlb_info rv;
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unsigned int even, odd;
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int vmalloc_branch_delay_filled = 0;
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const int scratch = 1; /* Our extra working register */
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rv.huge_pte = scratch;
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rv.restore_scratch = 0;
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if (check_for_high_segbits) {
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UASM_i_MFC0(p, tmp, C0_BADVADDR);
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if (pgd_reg != -1)
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UASM_i_MFC0(p, ptr, 31, pgd_reg);
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else
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UASM_i_MFC0(p, ptr, C0_CONTEXT);
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if (c0_scratch >= 0)
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UASM_i_MTC0(p, scratch, 31, c0_scratch);
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else
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UASM_i_SW(p, scratch, scratchpad_offset(0), 0);
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uasm_i_dsrl_safe(p, scratch, tmp,
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PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
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uasm_il_bnez(p, r, scratch, label_vmalloc);
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if (pgd_reg == -1) {
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vmalloc_branch_delay_filled = 1;
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/* Clear lower 23 bits of context. */
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uasm_i_dins(p, ptr, 0, 0, 23);
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}
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} else {
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if (pgd_reg != -1)
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UASM_i_MFC0(p, ptr, 31, pgd_reg);
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else
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UASM_i_MFC0(p, ptr, C0_CONTEXT);
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UASM_i_MFC0(p, tmp, C0_BADVADDR);
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if (c0_scratch >= 0)
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UASM_i_MTC0(p, scratch, 31, c0_scratch);
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else
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UASM_i_SW(p, scratch, scratchpad_offset(0), 0);
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if (pgd_reg == -1)
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/* Clear lower 23 bits of context. */
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uasm_i_dins(p, ptr, 0, 0, 23);
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uasm_il_bltz(p, r, tmp, label_vmalloc);
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}
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if (pgd_reg == -1) {
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vmalloc_branch_delay_filled = 1;
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/* 1 0 1 0 1 << 6 xkphys cached */
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uasm_i_ori(p, ptr, ptr, 0x540);
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uasm_i_drotr(p, ptr, ptr, 11);
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}
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#ifdef __PAGETABLE_PMD_FOLDED
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#define LOC_PTEP scratch
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#else
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#define LOC_PTEP ptr
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#endif
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if (!vmalloc_branch_delay_filled)
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/* get pgd offset in bytes */
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uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3);
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uasm_l_vmalloc_done(l, *p);
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/*
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* tmp ptr
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* fall-through case = badvaddr *pgd_current
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* vmalloc case = badvaddr swapper_pg_dir
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*/
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if (vmalloc_branch_delay_filled)
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/* get pgd offset in bytes */
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uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3);
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#ifdef __PAGETABLE_PMD_FOLDED
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GET_CONTEXT(p, tmp); /* get context reg */
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#endif
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uasm_i_andi(p, scratch, scratch, (PTRS_PER_PGD - 1) << 3);
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if (use_lwx_insns()) {
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UASM_i_LWX(p, LOC_PTEP, scratch, ptr);
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} else {
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uasm_i_daddu(p, ptr, ptr, scratch); /* add in pgd offset */
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uasm_i_ld(p, LOC_PTEP, 0, ptr); /* get pmd pointer */
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}
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#ifndef __PAGETABLE_PMD_FOLDED
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/* get pmd offset in bytes */
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uasm_i_dsrl_safe(p, scratch, tmp, PMD_SHIFT - 3);
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uasm_i_andi(p, scratch, scratch, (PTRS_PER_PMD - 1) << 3);
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GET_CONTEXT(p, tmp); /* get context reg */
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if (use_lwx_insns()) {
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UASM_i_LWX(p, scratch, scratch, ptr);
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} else {
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uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */
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UASM_i_LW(p, scratch, 0, ptr);
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}
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#endif
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/* Adjust the context during the load latency. */
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build_adjust_context(p, tmp);
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#ifdef CONFIG_HUGETLB_PAGE
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uasm_il_bbit1(p, r, scratch, ilog2(_PAGE_HUGE), label_tlb_huge_update);
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/*
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* The in the LWX case we don't want to do the load in the
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* delay slot. It cannot issue in the same cycle and may be
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* speculative and unneeded.
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*/
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if (use_lwx_insns())
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uasm_i_nop(p);
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#endif /* CONFIG_HUGETLB_PAGE */
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/* build_update_entries */
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if (use_lwx_insns()) {
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even = ptr;
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odd = tmp;
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UASM_i_LWX(p, even, scratch, tmp);
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UASM_i_ADDIU(p, tmp, tmp, sizeof(pte_t));
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UASM_i_LWX(p, odd, scratch, tmp);
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} else {
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UASM_i_ADDU(p, ptr, scratch, tmp); /* add in offset */
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even = tmp;
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odd = ptr;
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UASM_i_LW(p, even, 0, ptr); /* get even pte */
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UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */
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}
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if (kernel_uses_smartmips_rixi) {
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uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_NO_EXEC));
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uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_NO_EXEC));
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uasm_i_drotr(p, even, even,
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ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
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UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */
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uasm_i_drotr(p, odd, odd,
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ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
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} else {
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uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_GLOBAL));
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UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */
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uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_GLOBAL));
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}
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UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */
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if (c0_scratch >= 0) {
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UASM_i_MFC0(p, scratch, 31, c0_scratch);
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build_tlb_write_entry(p, l, r, tlb_random);
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uasm_l_leave(l, *p);
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rv.restore_scratch = 1;
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} else if (PAGE_SHIFT == 14 || PAGE_SHIFT == 13) {
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build_tlb_write_entry(p, l, r, tlb_random);
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uasm_l_leave(l, *p);
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UASM_i_LW(p, scratch, scratchpad_offset(0), 0);
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} else {
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UASM_i_LW(p, scratch, scratchpad_offset(0), 0);
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build_tlb_write_entry(p, l, r, tlb_random);
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uasm_l_leave(l, *p);
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rv.restore_scratch = 1;
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}
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uasm_i_eret(p); /* return from trap */
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return rv;
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}
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/*
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* For a 64-bit kernel, we are using the 64-bit XTLB refill exception
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* because EXL == 0. If we wrap, we can also use the 32 instruction
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@ -903,54 +1149,67 @@ static void __cpuinit build_r4000_tlb_refill_handler(void)
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struct uasm_reloc *r = relocs;
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u32 *f;
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unsigned int final_len;
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struct mips_huge_tlb_info htlb_info;
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enum vmalloc64_mode vmalloc_mode;
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memset(tlb_handler, 0, sizeof(tlb_handler));
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memset(labels, 0, sizeof(labels));
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memset(relocs, 0, sizeof(relocs));
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memset(final_handler, 0, sizeof(final_handler));
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/*
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* create the plain linear handler
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*/
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if (bcm1250_m3_war()) {
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unsigned int segbits = 44;
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if (scratch_reg == 0)
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scratch_reg = allocate_kscratch();
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uasm_i_dmfc0(&p, K0, C0_BADVADDR);
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uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
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uasm_i_xor(&p, K0, K0, K1);
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uasm_i_dsrl_safe(&p, K1, K0, 62);
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uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
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uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
|
||||
uasm_i_or(&p, K0, K0, K1);
|
||||
uasm_il_bnez(&p, &r, K0, label_leave);
|
||||
/* No need for uasm_i_nop */
|
||||
}
|
||||
if ((scratch_reg > 0 || scratchpad_available()) && use_bbit_insns()) {
|
||||
htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1,
|
||||
scratch_reg);
|
||||
vmalloc_mode = refill_scratch;
|
||||
} else {
|
||||
htlb_info.huge_pte = K0;
|
||||
htlb_info.restore_scratch = 0;
|
||||
vmalloc_mode = refill_noscratch;
|
||||
/*
|
||||
* create the plain linear handler
|
||||
*/
|
||||
if (bcm1250_m3_war()) {
|
||||
unsigned int segbits = 44;
|
||||
|
||||
uasm_i_dmfc0(&p, K0, C0_BADVADDR);
|
||||
uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
|
||||
uasm_i_xor(&p, K0, K0, K1);
|
||||
uasm_i_dsrl_safe(&p, K1, K0, 62);
|
||||
uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
|
||||
uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
|
||||
uasm_i_or(&p, K0, K0, K1);
|
||||
uasm_il_bnez(&p, &r, K0, label_leave);
|
||||
/* No need for uasm_i_nop */
|
||||
}
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
|
||||
build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
|
||||
#else
|
||||
build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
|
||||
build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_HUGETLB_PAGE
|
||||
build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update);
|
||||
build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update);
|
||||
#endif
|
||||
|
||||
build_get_ptep(&p, K0, K1);
|
||||
build_update_entries(&p, K0, K1);
|
||||
build_tlb_write_entry(&p, &l, &r, tlb_random);
|
||||
uasm_l_leave(&l, p);
|
||||
uasm_i_eret(&p); /* return from trap */
|
||||
|
||||
build_get_ptep(&p, K0, K1);
|
||||
build_update_entries(&p, K0, K1);
|
||||
build_tlb_write_entry(&p, &l, &r, tlb_random);
|
||||
uasm_l_leave(&l, p);
|
||||
uasm_i_eret(&p); /* return from trap */
|
||||
}
|
||||
#ifdef CONFIG_HUGETLB_PAGE
|
||||
uasm_l_tlb_huge_update(&l, p);
|
||||
UASM_i_LW(&p, K0, 0, K1);
|
||||
build_huge_update_entries(&p, K0, K1);
|
||||
build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random);
|
||||
build_huge_update_entries(&p, htlb_info.huge_pte, K1);
|
||||
build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random,
|
||||
htlb_info.restore_scratch);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, refill);
|
||||
build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, vmalloc_mode);
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
@ -1616,7 +1875,7 @@ static void __cpuinit build_r4000_tlb_load_handler(void)
|
|||
* We clobbered C0_PAGEMASK, restore it. On the other branch
|
||||
* it is restored in build_huge_tlb_write_entry.
|
||||
*/
|
||||
build_restore_pagemask(&p, &r, K0, label_nopage_tlbl);
|
||||
build_restore_pagemask(&p, &r, K0, label_nopage_tlbl, 0);
|
||||
|
||||
uasm_l_tlbl_goaround2(&l, p);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue