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The i.MX device tree updates for 4.13: 

- New board support: Gateworks Ventana GW5600, Technexion Pico i.MX7D
    Board.
  - A series from Alexandre Belloni to correct the vendor prefix for
    rv4162 compatible.
  - A patch-set from Andrey Smirnov ot enable PCIe support for i.MX7 and
    imx7d-sdb board.
  - Increase the SGTL5000 LRCLK pad strength to fix a random audio
    channel swapping seen on imx6qdl-wandboard and imx6qdl-colibri
    boards.
  - Clean up non-existing property 'enable-active-low' from fixed
    regulator device nodes.
  - Correct GPIO polarity for Ethernet PHY and PCI reset lines, even
    though device drivers do not use the polarity for now.
  - Add Wifi and Bluetooth support for imx7d-sdb board.
  - Adopt the i.MX6Q/DL DT to the new and more flexible GPC binding.
  - Update zii-rdu2 device tree source to use #include "..." for local
    inclusion.
  - A series from Philipp Zabel and Steve Longerbeam to enable video
    capture support for imx6qdl platforms.
  - A number of small random updates on various board support.
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Merge tag 'imx-dt-4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt

The i.MX device tree updates for 4.13:
 - New board support: Gateworks Ventana GW5600, Technexion Pico i.MX7D
   Board.
 - A series from Alexandre Belloni to correct the vendor prefix for
   rv4162 compatible.
 - A patch-set from Andrey Smirnov ot enable PCIe support for i.MX7 and
   imx7d-sdb board.
 - Increase the SGTL5000 LRCLK pad strength to fix a random audio
   channel swapping seen on imx6qdl-wandboard and imx6qdl-colibri
   boards.
 - Clean up non-existing property 'enable-active-low' from fixed
   regulator device nodes.
 - Correct GPIO polarity for Ethernet PHY and PCI reset lines, even
   though device drivers do not use the polarity for now.
 - Add Wifi and Bluetooth support for imx7d-sdb board.
 - Adopt the i.MX6Q/DL DT to the new and more flexible GPC binding.
 - Update zii-rdu2 device tree source to use #include "..." for local
   inclusion.
 - A series from Philipp Zabel and Steve Longerbeam to enable video
   capture support for imx6qdl platforms.
 - A number of small random updates on various board support.

* tag 'imx-dt-4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (47 commits)
  ARM: dts: imx6q-cm-fx6: add sdio wifi/bt nodes
  ARM: dts: ls1021a: update the clockgen node
  ARM: dts: imx6-sabreauto: add the ADV7180 video decoder
  ARM: dts: imx6-sabreauto: add pinctrl for gpt input capture
  ARM: dts: imx6-sabreauto: add reset-gpios property for max7310_b
  ARM: dts: imx6-sabreauto: create i2cmux for i2c3
  ARM: dts: imx6-sabresd: add OV5642 and OV5640 camera sensors
  ARM: dts: imx6-sabrelite: add OV5642 and OV5640 camera sensors
  ARM: dts: imx6qdl-sabrelite: remove erratum ERR006687 workaround
  ARM: dts: imx6qdl: add capture-subsystem device
  ARM: dts: imx6qdl: Add video multiplexers, mipi_csi, and their connections
  ARM: dts: imx6qdl: Add compatible, clocks, irqs to MIPI CSI-2 node
  ARM: dts: imx6qdl: add multiplexer controls
  ARM: dts: imx6: Fix PCI GPIO reset polarity
  ARM: dts: imx7d-sdb: Add Bluetooth support
  ARM: dts: imx7d-sdb: Add Wifi support
  ARM: dts: imx7d-sdb: Adjust the regulator nodes
  ARM: dts: imx: Fix Ethernet PHY reset polarity
  ARM: dts: imx7: Fix typo in watchdog pin name
  ARM: dts: vf610-zii: Add switch eeprom-length properties
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2017-06-18 23:06:36 -07:00
parent ae1d266305 d8710c3fb9
commit 2cb6115deb
78 changed files with 2361 additions and 226 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/boot/dts/Makefile
View File

@ -365,6 +365,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-gw551x.dtb \
imx6dl-gw552x.dtb \
imx6dl-gw553x.dtb \
imx6dl-gw560x.dtb \
imx6dl-gw5903.dtb \
imx6dl-gw5904.dtb \
imx6dl-hummingboard.dtb \
@ -410,6 +411,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-gw551x.dtb \
imx6q-gw552x.dtb \
imx6q-gw553x.dtb \
imx6q-gw560x.dtb \
imx6q-gw5903.dtb \
imx6q-gw5904.dtb \
imx6q-h100.dtb \
@ -478,6 +480,7 @@ dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-cl-som-imx7.dtb \
imx7d-colibri-eval-v3.dtb \
imx7d-nitrogen7.dtb \
imx7d-pico.dtb \
imx7d-sbc-imx7.dtb \
imx7d-sdb.dtb \
imx7d-sdb-sht11.dtb \

7
arch/arm/boot/dts/imx23-sansa.dts
View File

@ -42,6 +42,7 @@
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "imx23.dtsi"
/ {
@ -149,9 +150,8 @@ reg_vdd_touchpad: regulator-vdd-touchpad0 {
regulator-name = "vdd-touchpad0";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio0 26 0>;
gpio = <&gpio0 26 GPIO_ACTIVE_LOW>;
regulator-always-on;
enable-active-low;
};
reg_vdd_tuner: regulator-vdd-tuner0 {
@ -159,9 +159,8 @@ reg_vdd_tuner: regulator-vdd-tuner0 {
regulator-name = "vdd-tuner0";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio0 29 0>;
gpio = <&gpio0 29 GPIO_ACTIVE_LOW>;
regulator-always-on;
enable-active-low;
};
backlight {

2
arch/arm/boot/dts/imx25-karo-tx25.dts
View File

@ -97,7 +97,7 @@ &uart1 {
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-reset-gpios = <&gpio3 7 0>;
phy-reset-gpios = <&gpio3 7 GPIO_ACTIVE_LOW>;
phy-mode = "rmii";
phy-supply = <&reg_fec_phy>;
status = "okay";

2
arch/arm/boot/dts/imx25-pdk.dts
View File

@ -125,7 +125,7 @@ &fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-supply = <&reg_fec_3v3>;
phy-reset-gpios = <&gpio4 8 0>;
phy-reset-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
status = "okay";
};

1
arch/arm/boot/dts/imx25.dtsi
View File

@ -9,6 +9,7 @@
* http://www.gnu.org/copyleft/gpl.html
*/
#include <dt-bindings/gpio/gpio.h>
#include "imx25-pinfunc.h"
/ {

2
arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi
View File

@ -40,7 +40,7 @@ &i2c2 {
status = "okay";
at24@52 {
compatible = "at,24c32";
compatible = "atmel,24c32";
pagesize = <32>;
reg = <0x52>;
};

2
arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
View File

@ -193,7 +193,7 @@ &i2c2 {
status = "okay";
at24@52 {
compatible = "at,24c32";
compatible = "atmel,24c32";
pagesize = <32>;
reg = <0x52>;
};

2
arch/arm/boot/dts/imx28-cfa10037.dts
View File

@ -64,7 +64,7 @@ mac0: ethernet@800f0000 {
pinctrl-names = "default";
pinctrl-0 = <&mac0_pins_a
&mac0_pins_cfa10037>;
phy-reset-gpios = <&gpio2 21 0>;
phy-reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>;
phy-reset-duration = <100>;
status = "okay";
};

2
arch/arm/boot/dts/imx28-cfa10049.dts
View File

@ -327,7 +327,7 @@ mac0: ethernet@800f0000 {
pinctrl-names = "default";
pinctrl-0 = <&mac0_pins_a
&mac0_pins_cfa10049>;
phy-reset-gpios = <&gpio2 21 0>;
phy-reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>;
phy-reset-duration = <100>;
status = "okay";
};

2
arch/arm/boot/dts/imx28-cfa10057.dts
View File

@ -162,7 +162,7 @@ mac0: ethernet@800f0000 {
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&mac0_pins_a>;
phy-reset-gpios = <&gpio2 21 0>;
phy-reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>;
phy-reset-duration = <100>;
status = "okay";
};

2
arch/arm/boot/dts/imx28-cfa10058.dts
View File

@ -129,7 +129,7 @@ mac0: ethernet@800f0000 {
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&mac0_pins_a>;
phy-reset-gpios = <&gpio2 21 0>;
phy-reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>;
phy-reset-duration = <100>;
status = "okay";
};

2
arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts
View File

@ -31,7 +31,7 @@ &mac1 {
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&mac1_pins_a>;
phy-reset-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>;
phy-reset-gpios = <&gpio3 27 GPIO_ACTIVE_LOW>;
status = "okay";
};

4
arch/arm/boot/dts/imx28-evk.dts
View File

@ -203,7 +203,7 @@ sgtl5000: codec@0a {
};
at24@51 {
compatible = "at24,24c32";
compatible = "atmel,24c32";
pagesize = <32>;
reg = <0x51>;
};
@ -262,7 +262,7 @@ mac0: ethernet@800f0000 {
pinctrl-names = "default";
pinctrl-0 = <&mac0_pins_a>;
phy-supply = <&reg_fec_3v3>;
phy-reset-gpios = <&gpio4 13 0>;
phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>;
phy-reset-duration = <100>;
status = "okay";
};

2
arch/arm/boot/dts/imx28-m28cu3.dts
View File

@ -188,7 +188,7 @@ mac0: ethernet@800f0000 {
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&mac0_pins_a>;
phy-reset-gpios = <&gpio4 13 0>;
phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>;
phy-reset-duration = <100>;
status = "okay";
};

2
arch/arm/boot/dts/imx50-evk.dts
View File

@ -53,7 +53,7 @@ &fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio4 12 0>;
phy-reset-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
status = "okay";
};

1
arch/arm/boot/dts/imx50.dtsi
View File

@ -12,6 +12,7 @@
*/
#include "imx50-pinfunc.h"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/imx5-clock.h>
/ {

2
arch/arm/boot/dts/imx51-apf51.dts
View File

@ -36,7 +36,7 @@ &fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "mii";
phy-reset-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
phy-reset-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
phy-reset-duration = <1>;
status = "okay";
};

2
arch/arm/boot/dts/imx53-mba53.dts
View File

@ -195,7 +195,7 @@ sensor2: lm75@49 {
};
&fec {
phy-reset-gpios = <&gpio7 6 0>;
phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
status = "okay";
};

2
arch/arm/boot/dts/imx53-qsb-common.dtsi
View File

@ -344,7 +344,7 @@ &fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio7 6 0>;
phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
status = "okay";
};

2
arch/arm/boot/dts/imx53-smd.dts
View File

@ -273,6 +273,6 @@ &fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio7 6 0>;
phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
status = "okay";
};

2
arch/arm/boot/dts/imx53-tqma53.dtsi
View File

@ -272,7 +272,7 @@ sensor1: lm75@48 {
};
eeprom: 24c64@50 {
compatible = "at,24c64";
compatible = "atmel,24c64";
pagesize = <32>;
reg = <0x50>;
};

2
arch/arm/boot/dts/imx53-tx53.dtsi
View File

@ -201,7 +201,7 @@ &fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
phy-handle = <&phy0>;
mac-address = [000000000000]; /* placeholder; will be overwritten by bootloader */
status = "okay";

2
arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi
View File

@ -137,7 +137,7 @@ &fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio4 2 0>;
phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
status = "okay";
};

55
arch/arm/boot/dts/imx6dl-gw560x.dts Normal file
View File

@ -0,0 +1,55 @@
/*
* Copyright 2017 Gateworks Corporation
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this file; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-gw560x.dtsi"
/ {
model = "Gateworks Ventana i.MX6 DualLite/Solo GW560X";
compatible = "gw,imx6dl-gw560x", "gw,ventana", "fsl,imx6dl";
};

2
arch/arm/boot/dts/imx6dl-riotboard.dts
View File

@ -94,7 +94,7 @@ &fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio3 31 0>;
phy-reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
fsl,err006687-workaround-present;

5
arch/arm/boot/dts/imx6dl-sabrelite.dts
View File

@ -48,3 +48,8 @@ / {
model = "Freescale i.MX6 DualLite SABRE Lite Board";
compatible = "fsl,imx6dl-sabrelite", "fsl,imx6dl";
};
&ipu1_csi1_from_ipu1_csi1_mux {
clock-lanes = <0>;
data-lanes = <1 2>;
};

5
arch/arm/boot/dts/imx6dl-sabresd.dts
View File

@ -15,3 +15,8 @@ / {
model = "Freescale i.MX6 DualLite SABRE Smart Device Board";
compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
};
&ipu1_csi1_from_ipu1_csi1_mux {
clock-lanes = <0>;
data-lanes = <1 2>;
};

189
arch/arm/boot/dts/imx6dl.dtsi
View File

@ -100,6 +100,11 @@ i2c4: i2c@021f8000 {
};
};
capture-subsystem {
compatible = "fsl,imx-capture-subsystem";
ports = <&ipu1_csi0>, <&ipu1_csi1>;
};
display-subsystem {
compatible = "fsl,imx-display-subsystem";
ports = <&ipu1_di0>, <&ipu1_di1>;
@ -164,6 +169,116 @@ &gpio7 {
<&iomuxc 9 207 1>, <&iomuxc 10 206 1>, <&iomuxc 11 133 3>;
};
&gpr {
ipu1_csi0_mux: ipu1_csi0_mux@34 {
compatible = "video-mux";
mux-controls = <&mux 0>;
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ipu1_csi0_mux_from_mipi_vc0: endpoint {
remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
};
};
port@1 {
reg = <1>;
ipu1_csi0_mux_from_mipi_vc1: endpoint {
remote-endpoint = <&mipi_vc1_to_ipu1_csi0_mux>;
};
};
port@2 {
reg = <2>;
ipu1_csi0_mux_from_mipi_vc2: endpoint {
remote-endpoint = <&mipi_vc2_to_ipu1_csi0_mux>;
};
};
port@3 {
reg = <3>;
ipu1_csi0_mux_from_mipi_vc3: endpoint {
remote-endpoint = <&mipi_vc3_to_ipu1_csi0_mux>;
};
};
port@4 {
reg = <4>;
ipu1_csi0_mux_from_parallel_sensor: endpoint {
};
};
port@5 {
reg = <5>;
ipu1_csi0_mux_to_ipu1_csi0: endpoint {
remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
};
};
};
ipu1_csi1_mux: ipu1_csi1_mux@34 {
compatible = "video-mux";
mux-controls = <&mux 1>;
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ipu1_csi1_mux_from_mipi_vc0: endpoint {
remote-endpoint = <&mipi_vc0_to_ipu1_csi1_mux>;
};
};
port@1 {
reg = <1>;
ipu1_csi1_mux_from_mipi_vc1: endpoint {
remote-endpoint = <&mipi_vc1_to_ipu1_csi1_mux>;
};
};
port@2 {
reg = <2>;
ipu1_csi1_mux_from_mipi_vc2: endpoint {
remote-endpoint = <&mipi_vc2_to_ipu1_csi1_mux>;
};
};
port@3 {
reg = <3>;
ipu1_csi1_mux_from_mipi_vc3: endpoint {
remote-endpoint = <&mipi_vc3_to_ipu1_csi1_mux>;
};
};
port@4 {
reg = <4>;
ipu1_csi1_mux_from_parallel_sensor: endpoint {
};
};
port@5 {
reg = <5>;
ipu1_csi1_mux_to_ipu1_csi1: endpoint {
remote-endpoint = <&ipu1_csi1_from_ipu1_csi1_mux>;
};
};
};
};
&gpt {
compatible = "fsl,imx6dl-gpt";
};
@ -172,6 +287,12 @@ &hdmi {
compatible = "fsl,imx6dl-hdmi";
};
&ipu1_csi1 {
ipu1_csi1_from_ipu1_csi1_mux: endpoint {
remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>;
};
};
&ldb {
clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
@ -181,6 +302,74 @@ &ldb {
"di0", "di1";
};
&mipi_csi {
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi_vc0_to_ipu1_csi0_mux: endpoint@0 {
remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
};
mipi_vc0_to_ipu1_csi1_mux: endpoint@1 {
remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>;
};
};
port@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
mipi_vc1_to_ipu1_csi0_mux: endpoint@0 {
remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc1>;
};
mipi_vc1_to_ipu1_csi1_mux: endpoint@1 {
remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc1>;
};
};
port@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
mipi_vc2_to_ipu1_csi0_mux: endpoint@0 {
remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc2>;
};
mipi_vc2_to_ipu1_csi1_mux: endpoint@1 {
remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc2>;
};
};
port@4 {
reg = <4>;
#address-cells = <1>;
#size-cells = <0>;
mipi_vc3_to_ipu1_csi0_mux: endpoint@0 {
remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc3>;
};
mipi_vc3_to_ipu1_csi1_mux: endpoint@1 {
remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc3>;
};
};
};
&mux {
mux-reg-masks = <0x34 0x00000007>, /* IPU_CSI0_MUX */
<0x34 0x00000038>, /* IPU_CSI1_MUX */
<0x0c 0x0000000c>, /* HDMI_MUX_CTL */
<0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
<0x0c 0x00000300>, /* LVDS1_MUX_CTL */
<0x28 0x00000003>, /* DCIC1_MUX_CTL */
<0x28 0x0000000c>; /* DCIC2_MUX_CTL */
};
&vpu {
compatible = "fsl,imx6dl-vpu", "cnm,coda960";
};

2
arch/arm/boot/dts/imx6q-ba16.dtsi
View File

@ -321,7 +321,7 @@ rtc@32 {
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
fsl,tx-swing-full = <103>;
fsl,tx-swing-low = <103>;
status = "okay";

43
arch/arm/boot/dts/imx6q-cm-fx6.dts
View File

@ -64,6 +64,14 @@ heartbeat-led {
};
};
awnh387_pwrseq: pwrseq {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwrseq>;
compatible = "mmc-pwrseq-sd8787";
powerdown-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
};
reg_pcie_power_on_gpio: regulator-pcie-power-on-gpio {
compatible = "regulator-fixed";
regulator-name = "regulator-pcie-power-on-gpio";
@ -215,7 +223,7 @@ &i2c3 {
clock-frequency = <100000>;
eeprom@50 {
compatible = "at24,24c02";
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
@ -304,6 +312,13 @@ MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b1
>;
};
pinctrl_pwrseq: pwrseqgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0
>;
};
pinctrl_spdif: spdifgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
@ -330,6 +345,17 @@ MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
>;
};
};
&pcie {
@ -382,3 +408,18 @@ &usbotg {
dr_mode = "otg";
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
mmc-pwrseq = <&awnh387_pwrseq>;
non-removable;
/*
* If the OS probes the Bluetooth AMP function advertised on this bus
* but the firmware in place does not support it, the WiFi/BT module
* gets unresponsive.
* Users who configured their OS properly can enable this node to gain
* WiFi and/or plain Bluetooth support.
*/
status = "disabled";
};

4
arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
View File

@ -118,7 +118,7 @@ &fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio1 25 0>;
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
phy-supply = <&vgen2_1v2_eth>;
status = "okay";
};
@ -435,7 +435,7 @@ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio4 8 0>;
reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>;
status = "okay";
};

2
arch/arm/boot/dts/imx6q-evi.dts
View File

@ -135,7 +135,7 @@ &fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio1 25 0>;
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
fsl,err006687-workaround-present;

7
arch/arm/boot/dts/imx6q-gw5400-a.dts
View File

@ -19,7 +19,6 @@ / {
/* these are used by bootloader for disabling nodes */
aliases {
ethernet1 = &eth1;
i2c0 = &i2c1;
i2c1 = &i2c2;
i2c2 = &i2c3;
@ -154,7 +153,7 @@ &fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
status = "okay";
};
@ -347,10 +346,6 @@ &ldb {
&pcie {
reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
status = "okay";
eth1: sky2@8 { /* MAC/PHY on bus 8 */
compatible = "marvell,sky2";
};
};
&ssi1 {

59
arch/arm/boot/dts/imx6q-gw560x.dts Normal file
View File

@ -0,0 +1,59 @@
/*
* Copyright 2017 Gateworks Corporation
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this file; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-gw560x.dtsi"
/ {
model = "Gateworks Ventana i.MX6 Dual/Quad GW560X";
compatible = "gw,imx6q-gw560x", "gw,ventana", "fsl,imx6q";
};
&sata {
status = "okay";
};

4
arch/arm/boot/dts/imx6q-novena.dts
View File

@ -217,7 +217,7 @@ &fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet_novena>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
rxc-skew-ps = <3000>;
rxdv-skew-ps = <0>;
txc-skew-ps = <3000>;
@ -446,7 +446,7 @@ lvds-channel@0 {
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie_novena>;
reset-gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
reset-gpio = <&gpio3 29 GPIO_ACTIVE_LOW>;
status = "okay";
};

5
arch/arm/boot/dts/imx6q-sabrelite.dts
View File

@ -52,3 +52,8 @@ / {
&sata {
status = "okay";
};
&ipu1_csi1_from_mipi_vc1 {
clock-lanes = <0>;
data-lanes = <1 2>;
};

5
arch/arm/boot/dts/imx6q-sabresd.dts
View File

@ -23,3 +23,8 @@ / {
&sata {
status = "okay";
};
&ipu1_csi1_from_mipi_vc1 {
clock-lanes = <0>;
data-lanes = <1 2>;
};

2
arch/arm/boot/dts/imx6q-utilite-pro.dts
View File

@ -130,7 +130,7 @@ i2c@0 {
#size-cells = <0>;
eeprom@50 {
compatible = "at24,24c02";
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};

4
arch/arm/boot/dts/imx6q-zii-rdu2.dts
View File

@ -41,8 +41,8 @@
/dts-v1/;
#include <imx6q.dtsi>
#include <imx6qdl-zii-rdu2.dtsi>
#include "imx6q.dtsi"
#include "imx6qdl-zii-rdu2.dtsi"
/ {
model = "ZII RDU2 Board";

127
arch/arm/boot/dts/imx6q.dtsi
View File

@ -125,7 +125,7 @@ gpu_vg: gpu@02204000 {
clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
<&clks IMX6QDL_CLK_GPU2D_CORE>;
clock-names = "bus", "core";
power-domains = <&gpc 1>;
power-domains = <&pd_pu>;
};
ipu2: ipu@02800000 {
@ -143,10 +143,18 @@ ipu2: ipu@02800000 {
ipu2_csi0: port@0 {
reg = <0>;
ipu2_csi0_from_mipi_vc2: endpoint {
remote-endpoint = <&mipi_vc2_to_ipu2_csi0>;
};
};
ipu2_csi1: port@1 {
reg = <1>;
ipu2_csi1_from_ipu2_csi1_mux: endpoint {
remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>;
};
};
ipu2_di0: port@2 {
@ -198,6 +206,11 @@ ipu2_di1_lvds1: lvds1-endpoint {
};
};
capture-subsystem {
compatible = "fsl,imx-capture-subsystem";
ports = <&ipu1_csi0>, <&ipu1_csi1>, <&ipu2_csi0>, <&ipu2_csi1>;
};
display-subsystem {
compatible = "fsl,imx-display-subsystem";
ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
@ -246,6 +259,68 @@ &gpio7 {
gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
};
&gpr {
ipu1_csi0_mux {
compatible = "video-mux";
mux-controls = <&mux 0>;
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ipu1_csi0_mux_from_mipi_vc0: endpoint {
remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
};
};
port@1 {
reg = <1>;
ipu1_csi0_mux_from_parallel_sensor: endpoint {
};
};
port@2 {
reg = <2>;
ipu1_csi0_mux_to_ipu1_csi0: endpoint {
remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
};
};
};
ipu2_csi1_mux {
compatible = "video-mux";
mux-controls = <&mux 1>;
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ipu2_csi1_mux_from_mipi_vc3: endpoint {
remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>;
};
};
port@1 {
reg = <1>;
ipu2_csi1_mux_from_parallel_sensor: endpoint {
};
};
port@2 {
reg = <2>;
ipu2_csi1_mux_to_ipu2_csi1: endpoint {
remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>;
};
};
};
};
&hdmi {
compatible = "fsl,imx6q-hdmi";
@ -266,6 +341,12 @@ hdmi_mux_3: endpoint {
};
};
&ipu1_csi1 {
ipu1_csi1_from_mipi_vc1: endpoint {
remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
};
};
&ldb {
clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
@ -312,6 +393,40 @@ lvds1_mux_3: endpoint {
};
};
&mipi_csi {
port@1 {
reg = <1>;
mipi_vc0_to_ipu1_csi0_mux: endpoint {
remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
};
};
port@2 {
reg = <2>;
mipi_vc1_to_ipu1_csi1: endpoint {
remote-endpoint = <&ipu1_csi1_from_mipi_vc1>;
};
};
port@3 {
reg = <3>;
mipi_vc2_to_ipu2_csi0: endpoint {
remote-endpoint = <&ipu2_csi0_from_mipi_vc2>;
};
};
port@4 {
reg = <4>;
mipi_vc3_to_ipu2_csi1_mux: endpoint {
remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>;
};
};
};
&mipi_dsi {
ports {
port@2 {
@ -332,6 +447,16 @@ mipi_mux_3: endpoint {
};
};
&mux {
mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
<0x04 0x00100000>, /* MIPI_IPU2_MUX */
<0x0c 0x0000000c>, /* HDMI_MUX_CTL */
<0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
<0x0c 0x00000300>, /* LVDS1_MUX_CTL */
<0x28 0x00000003>, /* DCIC1_MUX_CTL */
<0x28 0x0000000c>; /* DCIC2_MUX_CTL */
};
&vpu {
compatible = "fsl,imx6q-vpu", "cnm,coda960";
};

2
arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
View File

@ -232,7 +232,7 @@ &ipu1_di0_disp0 {
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio6 2 GPIO_ACTIVE_HIGH>;
reset-gpio = <&gpio6 2 GPIO_ACTIVE_LOW>;
status = "okay";
};

2
arch/arm/boot/dts/imx6qdl-aristainetos.dtsi
View File

@ -118,7 +118,7 @@ &fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
status = "okay";
};

4
arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi
View File

@ -320,7 +320,7 @@ &fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio7 18 GPIO_ACTIVE_HIGH>;
phy-reset-gpios = <&gpio7 18 GPIO_ACTIVE_LOW>;
txd0-skew-ps = <0>;
txd1-skew-ps = <0>;
txd2-skew-ps = <0>;
@ -335,7 +335,7 @@ &gpmi {
};
&pcie {
reset-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>;
reset-gpio = <&gpio2 16 GPIO_ACTIVE_LOW>;
status = "okay";
};

1
arch/arm/boot/dts/imx6qdl-colibri.dtsi
View File

@ -254,6 +254,7 @@ codec: sgtl5000@0a {
clocks = <&clks IMX6QDL_CLK_CKO>;
VDDA-supply = <&reg_2p5v>;
VDDIO-supply = <&reg_3p3v>;
lrclk-strength = <3>;
};
/* STMPE811 touch screen controller */

5
arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
View File

@ -14,7 +14,6 @@
/ {
/* these are used by bootloader for disabling nodes */
aliases {
ethernet1 = &eth1;
led0 = &led0;
led1 = &led1;
led2 = &led2;
@ -342,10 +341,6 @@ &pcie {
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
status = "okay";
eth1: sky2@8 { /* MAC/PHY on bus 8 */
compatible = "marvell,sky2";
};
};
&pwm2 {

5
arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
View File

@ -14,7 +14,6 @@
/ {
/* these are used by bootloader for disabling nodes */
aliases {
ethernet1 = &eth1;
led0 = &led0;
led1 = &led1;
led2 = &led2;
@ -379,10 +378,6 @@ &pcie {
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
status = "okay";
eth1: sky2@8 { /* MAC/PHY on bus 8 */
compatible = "marvell,sky2";
};
};
&pwm1 {

749
arch/arm/boot/dts/imx6qdl-gw560x.dtsi Normal file
View File

@ -0,0 +1,749 @@
/*
* Copyright 2017 Gateworks Corporation
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this file; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
/* these are used by bootloader for disabling nodes */
aliases {
led0 = &led0;
led1 = &led1;
led2 = &led2;
ssi0 = &ssi1;
usb0 = &usbh1;
usb1 = &usbotg;
};
chosen {
stdout-path = &uart2;
};
backlight-display {
compatible = "pwm-backlight";
pwms = <&pwm4 0 5000000>;
brightness-levels = <
0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100
>;
default-brightness-level = <100>;
};
backlight-keypad {
compatible = "gpio-backlight";
gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
default-on;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led0: user1 {
label = "user1";
gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
default-state = "on";
linux,default-trigger = "heartbeat";
};
led1: user2 {
label = "user2";
gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
default-state = "off";
};
led2: user3 {
label = "user3";
gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
default-state = "off";
};
};
memory@10000000 {
reg = <0x10000000 0x40000000>;
};
pps {
compatible = "pps-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pps>;
gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
};
reg_2p5v: regulator-2p5v {
compatible = "regulator-fixed";
regulator-name = "2P5V";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_5p0v: regulator-5p0v {
compatible = "regulator-fixed";
regulator-name = "5P0V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
reg_12p0v: regulator-12p0v {
compatible = "regulator-fixed";
regulator-name = "12P0V";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_1p4v: regulator-vddsoc {
compatible = "regulator-fixed";
regulator-name = "vdd_soc";
regulator-min-microvolt = <1400000>;
regulator-max-microvolt = <1400000>;
regulator-always-on;
};
reg_usb_h1_vbus: regulator-usb-h1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
sound {
compatible = "fsl,imx6q-ventana-sgtl5000",
"fsl,imx-audio-sgtl5000";
model = "sgtl5000-audio";
ssi-controller = <&ssi1>;
audio-codec = <&sgtl5000>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
mux-int-port = <1>;
mux-ext-port = <4>;
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&ecspi3 {
cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
status = "okay";
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan>;
status = "okay";
};
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
status = "okay";
};
&hdmi {
ddc-i2c-bus = <&i2c3>;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
eeprom1: eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
eeprom2: eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
pagesize = <16>;
};
eeprom3: eeprom@52 {
compatible = "atmel,24c02";
reg = <0x52>;
pagesize = <16>;
};
eeprom4: eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
};
pca9555: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
};
ds1672: rtc@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clocks = <&clks IMX6QDL_CLK_CKO>;
VDDA-supply = <&reg_1p8v>;
VDDIO-supply = <&reg_3p3v>;
};
tca8418: keypad@34 {
compatible = "ti,tca8418";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_keypad>;
reg = <0x34>;
interrupt-parent = <&gpio5>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
linux,keymap = < MATRIX_KEY(0x00, 0x01, BTN_0)
MATRIX_KEY(0x00, 0x00, BTN_1)
MATRIX_KEY(0x01, 0x01, BTN_2)
MATRIX_KEY(0x01, 0x00, BTN_3)
MATRIX_KEY(0x02, 0x00, BTN_4)
MATRIX_KEY(0x00, 0x03, BTN_5)
MATRIX_KEY(0x00, 0x02, BTN_6)
MATRIX_KEY(0x01, 0x03, BTN_7)
MATRIX_KEY(0x01, 0x02, BTN_8)
MATRIX_KEY(0x02, 0x02, BTN_9)
>;
keypad,num-rows = <4>;
keypad,num-columns = <4>;
};
ltc3676: pmic@3c {
compatible = "lltc,ltc3676";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
reg = <0x3c>;
interrupt-parent = <&gpio1>;
interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
regulators {
/* VDD_DDR (1+R1/R2 = 2.105) */
reg_vdd_ddr: sw2 {
regulator-name = "vddddr";
regulator-min-microvolt = <868310>;
regulator-max-microvolt = <1684000>;
lltc,fb-voltage-divider = <221000 200000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_ARM (1+R1/R2 = 1.931) */
reg_vdd_arm: sw3 {
regulator-name = "vddarm";
regulator-min-microvolt = <796551>;
regulator-max-microvolt = <1544827>;
lltc,fb-voltage-divider = <243000 261000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
linux,phandle = <&reg_vdd_arm>;
};
/* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
reg_1p8v: sw4 {
regulator-name = "vdd1p8";
regulator-min-microvolt = <1033310>;
regulator-max-microvolt = <2004000>;
lltc,fb-voltage-divider = <301000 200000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_1P0 (1+R1/R2 = 1.39): PCIe/ENET-PHY */
reg_1p0v: ldo2 {
regulator-name = "vdd1p0";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1050000>;
lltc,fb-voltage-divider = <78700 200000>;
regulator-boot-on;
regulator-always-on;
};
/* VDD_AUD_1P8: Audio codec */
reg_aud_1p8v: ldo3 {
regulator-name = "vdd1p8a";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
};
/* VDD_HIGH (1+R1/R2 = 4.17) */
reg_3p0v: ldo4 {
regulator-name = "vdd3p0";
regulator-min-microvolt = <3023250>;
regulator-max-microvolt = <3023250>;
lltc,fb-voltage-divider = <634000 200000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
egalax_ts: touchscreen@4 {
compatible = "eeti,egalax_ts";
reg = <0x04>;
interrupt-parent = <&gpio5>;
interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
wakeup-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
};
};
&ldb {
fsl,dual-channel;
status = "okay";
lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
status = "okay";
display-timings {
native-mode = <&timing0>;
timing0: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
};
};
};
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio4 31 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
status = "disabled";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
status = "disabled";
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
&ssi1 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
uart-has-rtscts;
rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_usb_h1_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <8>;
vmmc-supply = <&reg_3p3v>;
non-removable;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
};
&iomuxc {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
/* AUD4 */
MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0
MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
/* AUD6 */
MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0
MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0
MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0
MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0
>;
};
pinctrl_ecspi3: escpi3grp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */
>;
};
pinctrl_flexcan: flexcangrp {
fsl,pins = <
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x4001b0b0 /* DIOI2C_DIS# */
MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x0001b0b0 /* LVDS_TOUCH_IRQ# */
MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x0001b0b0 /* LVDS_BACKEN */
>;
};
pinctrl_keypad: keypadgrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x0001b0b0 /* KEYPAD_IRQ# */
MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x0001b0b0 /* KEYPAD_LED_EN */
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b0 /* PCI_RST# */
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b0 /* PCIESKT_WDIS# */
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
>;
};
pinctrl_pps: ppsgrp {
fsl,pins = <
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
>;
};
pinctrl_usbh1: usbh1grp {
fsl,pins = <
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* USBHUB_RST# */
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x170f9
MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x170f9
MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x170f9
MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x170f9
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
>;
};
};

2
arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
View File

@ -46,7 +46,7 @@ &fec {
pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
phy-mode = "rgmii";
phy-reset-duration = <2>;
phy-reset-gpios = <&gpio4 15 0>;
phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
status = "okay";
};

2
arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
View File

@ -408,7 +408,7 @@ codec: sgtl5000@0a {
};
rtc: rtc@68 {
compatible = "st,rv4162";
compatible = "microcrystal,rv4162";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rv4162>;
reg = <0x68>;

2
arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
View File

@ -326,7 +326,7 @@ codec: sgtl5000@0a {
};
rtc@68 {
compatible = "st,rv4162";
compatible = "microcrystal,rv4162";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rv4162>;
reg = <0x68>;

2
arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
View File

@ -271,7 +271,7 @@ &fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio1 27 0>;
phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
txen-skew-ps = <0>;
txc-skew-ps = <3000>;
rxdv-skew-ps = <0>;

2
arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
View File

@ -374,7 +374,7 @@ MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio4 17 0>;
reset-gpio = <&gpio4 17 GPIO_ACTIVE_LOW>;
status = "disabled";
};

131
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
View File

@ -108,6 +108,76 @@ backlight {
default-brightness-level = <7>;
status = "okay";
};
i2cmux {
compatible = "i2c-mux-gpio";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3mux>;
mux-gpios = <&gpio5 4 0>;
i2c-parent = <&i2c3>;
idle-state = <0>;
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
adv7180: camera@21 {
compatible = "adi,adv7180";
reg = <0x21>;
powerdown-gpios = <&max7310_b 2 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio1>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
port {
adv7180_to_ipu1_csi0_mux: endpoint {
remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
bus-width = <8>;
};
};
};
max7310_a: gpio@30 {
compatible = "maxim,max7310";
reg = <0x30>;
gpio-controller;
#gpio-cells = <2>;
};
max7310_b: gpio@32 {
compatible = "maxim,max7310";
reg = <0x32>;
gpio-controller;
#gpio-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_max7310>;
reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
};
max7310_c: gpio@34 {
compatible = "maxim,max7310";
reg = <0x34>;
gpio-controller;
#gpio-cells = <2>;
};
};
};
};
&ipu1_csi0_from_ipu1_csi0_mux {
bus-width = <8>;
};
&ipu1_csi0_mux_from_parallel_sensor {
remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
bus-width = <8>;
};
&ipu1_csi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu1_csi0>;
};
&clks {
@ -290,27 +360,6 @@ &i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
max7310_a: gpio@30 {
compatible = "maxim,max7310";
reg = <0x30>;
gpio-controller;
#gpio-cells = <2>;
};
max7310_b: gpio@32 {
compatible = "maxim,max7310";
reg = <0x32>;
gpio-controller;
#gpio-cells = <2>;
};
max7310_c: gpio@34 {
compatible = "maxim,max7310";
reg = <0x34>;
gpio-controller;
#gpio-cells = <2>;
};
};
&iomuxc {
@ -418,12 +467,52 @@ MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_i2c3mux: i2c3muxgrp {
fsl,pins = <
MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0b0b1
>;
};
pinctrl_ipu1_csi0: ipu1csi0grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
>;
};
pinctrl_max7310: max7310grp {
fsl,pins = <
MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0
>;
};
pinctrl_pwm3: pwm1grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_gpt_input_capture0: gptinputcapture0grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x1b0b0
>;
};
pinctrl_gpt_input_capture1: gptinputcapture1grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x1b0b0
>;
};
pinctrl_spdif: spdifgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0

152
arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
View File

@ -39,6 +39,8 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
@ -94,6 +96,42 @@ reg_can_xcvr: regulator@3 {
pinctrl-0 = <&pinctrl_can_xcvr>;
gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
};
reg_1p5v: regulator@4 {
compatible = "regulator-fixed";
reg = <4>;
regulator-name = "1P5V";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
};
reg_1p8v: regulator@5 {
compatible = "regulator-fixed";
reg = <5>;
regulator-name = "1P8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
reg_2p8v: regulator@6 {
compatible = "regulator-fixed";
reg = <6>;
regulator-name = "2P8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
};
};
mipi_xclk: mipi_xclk {
compatible = "pwm-clock";
#clock-cells = <0>;
clock-frequency = <22000000>;
clock-output-names = "mipi_pwm3";
pwms = <&pwm3 0 45>; /* 1 / 45 ns = 22 MHz */
status = "okay";
};
gpio-keys {
@ -220,6 +258,22 @@ panel_in: endpoint {
};
};
&ipu1_csi0_from_ipu1_csi0_mux {
bus-width = <8>;
data-shift = <12>; /* Lines 19:12 used */
hsync-active = <1>;
vync-active = <1>;
};
&ipu1_csi0_mux_from_parallel_sensor {
remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
};
&ipu1_csi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu1_csi0>;
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
@ -270,9 +324,6 @@ &fec {
txd1-skew-ps = <0>;
txd2-skew-ps = <0>;
txd3-skew-ps = <0>;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
fsl,err006687-workaround-present;
status = "okay";
};
@ -301,6 +352,53 @@ &i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
ov5640: camera@40 {
compatible = "ovti,ov5640";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ov5640>;
reg = <0x40>;
clocks = <&mipi_xclk>;
clock-names = "xclk";
DOVDD-supply = <&reg_1p8v>;
AVDD-supply = <&reg_2p8v>;
DVDD-supply = <&reg_1p5v>;
reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* NANDF_D5 */
powerdown-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* NANDF_WP_B */
port {
#address-cells = <1>;
#size-cells = <0>;
ov5640_to_mipi_csi2: endpoint {
remote-endpoint = <&mipi_csi2_in>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
ov5642: camera@42 {
compatible = "ovti,ov5642";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ov5642>;
clocks = <&clks IMX6QDL_CLK_CKO2>;
clock-names = "xclk";
reg = <0x42>;
reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
powerdown-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
gp-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
status = "disabled";
port {
ov5642_to_ipu1_csi0_mux: endpoint {
remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
bus-width = <8>;
hsync-active = <1>;
vsync-active = <1>;
};
};
};
};
&i2c3 {
@ -373,7 +471,6 @@ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
/* Phy reset */
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x000b0
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>;
};
@ -415,6 +512,23 @@ MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_ipu1_csi0: ipu1csi0grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x1b0b0
>;
};
pinctrl_j15: j15grp {
fsl,pins = <
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
@ -448,6 +562,22 @@ MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
>;
};
pinctrl_ov5640: ov5640grp {
fsl,pins = <
MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000b0
MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0
>;
};
pinctrl_ov5642: ov5642grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0
MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x130b0
MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
@ -602,3 +732,17 @@ &usdhc4 {
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
&mipi_csi {
status = "okay";
port@0 {
reg = <0>;
mipi_csi2_in: endpoint {
remote-endpoint = <&ov5640_to_mipi_csi2>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};

116
arch/arm/boot/dts/imx6qdl-sabresd.dtsi
View File

@ -10,6 +10,7 @@
* http://www.gnu.org/copyleft/gpl.html
*/
#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
@ -146,6 +147,36 @@ panel_in: endpoint {
};
};
&ipu1_csi0_from_ipu1_csi0_mux {
bus-width = <8>;
data-shift = <12>; /* Lines 19:12 used */
hsync-active = <1>;
vsync-active = <1>;
};
&ipu1_csi0_mux_from_parallel_sensor {
remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
};
&ipu1_csi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu1_csi0>;
};
&mipi_csi {
status = "okay";
port@0 {
reg = <0>;
mipi_csi2_in: endpoint {
remote-endpoint = <&ov5640_to_mipi_csi2>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
@ -178,7 +209,7 @@ &fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio1 25 0>;
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
status = "okay";
};
@ -213,7 +244,32 @@ codec: wm8962@1a {
0x8014 /* 4:FN_DMICCDAT */
0x0000 /* 5:Default */
>;
};
};
ov5642: camera@3c {
compatible = "ovti,ov5642";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ov5642>;
clocks = <&clks IMX6QDL_CLK_CKO>;
clock-names = "xclk";
reg = <0x3c>;
DOVDD-supply = <&vgen4_reg>; /* 1.8v */
AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3
rev B board is VGEN5 */
DVDD-supply = <&vgen2_reg>; /* 1.5v*/
powerdown-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
status = "disabled";
port {
ov5642_to_ipu1_csi0_mux: endpoint {
remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
bus-width = <8>;
hsync-active = <1>;
vsync-active = <1>;
};
};
};
};
&i2c2 {
@ -222,6 +278,32 @@ &i2c2 {
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
ov5640: camera@3c {
compatible = "ovti,ov5640";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ov5640>;
reg = <0x3c>;
clocks = <&clks IMX6QDL_CLK_CKO>;
clock-names = "xclk";
DOVDD-supply = <&vgen4_reg>; /* 1.8v */
AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3
rev B board is VGEN5 */
DVDD-supply = <&vgen2_reg>; /* 1.5v*/
powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
port {
#address-cells = <1>;
#size-cells = <0>;
ov5640_to_mipi_csi2: endpoint {
remote-endpoint = <&mipi_csi2_in>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
pmic: pfuze100@08 {
compatible = "fsl,pfuze100";
reg = <0x08>;
@ -425,6 +507,36 @@ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_ipu1_csi0: ipu1csi0grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
>;
};
pinctrl_ov5640: ov5640grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0
MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x1b0b0
>;
};
pinctrl_ov5642: ov5642grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0

5
arch/arm/boot/dts/imx6qdl-tx6.dtsi
View File

@ -133,8 +133,7 @@ reg_can_xcvr: regulator-can-xcvr {
regulator-max-microvolt = <3300000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan_xcvr>;
gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
enable-active-low;
gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
};
reg_lcd0_pwr: regulator-lcd0-pwr {
@ -249,7 +248,7 @@ &fec {
<&clks IMX6QDL_CLK_ENET_REF>;
clock-names = "ipg", "ahb", "ptp", "enet_out";
phy-mode = "rmii";
phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
phy-handle = <&etnphy>;
phy-supply = <&reg_3v3_etn>;
status = "okay";

3
arch/arm/boot/dts/imx6qdl-wandboard.dtsi
View File

@ -88,6 +88,7 @@ codec: sgtl5000@0a {
clocks = <&clks IMX6QDL_CLK_CKO>;
VDDA-supply = <&reg_2p5v>;
VDDIO-supply = <&reg_3p3v>;
lrclk-strength = <3>;
};
};
@ -208,7 +209,7 @@ &fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio3 29 0>;
phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
fsl,err006687-workaround-present;

60
arch/arm/boot/dts/imx6qdl.dtsi
View File

@ -156,7 +156,7 @@ gpu_3d: gpu@00130000 {
<&clks IMX6QDL_CLK_GPU3D_CORE>,
<&clks IMX6QDL_CLK_GPU3D_SHADER>;
clock-names = "bus", "core", "shader";
power-domains = <&gpc 1>;
power-domains = <&pd_pu>;
};
gpu_2d: gpu@00134000 {
@ -166,7 +166,7 @@ gpu_2d: gpu@00134000 {
clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,
<&clks IMX6QDL_CLK_GPU2D_CORE>;
clock-names = "bus", "core";
power-domains = <&gpc 1>;
power-domains = <&pd_pu>;
};
timer@00a00600 {
@ -434,7 +434,7 @@ vpu: vpu@02040000 {
clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
<&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
clock-names = "per", "ahb";
power-domains = <&gpc 1>;
power-domains = <&pd_pu>;
resets = <&src 1>;
iram = <&ocram>;
};
@ -644,6 +644,7 @@ regulator-1p1 {
anatop-min-bit-val = <4>;
anatop-min-voltage = <800000>;
anatop-max-voltage = <1375000>;
anatop-enable-bit = <0>;
};
regulator-3p0 {
@ -658,6 +659,7 @@ regulator-3p0 {
anatop-min-bit-val = <0>;
anatop-min-voltage = <2625000>;
anatop-max-voltage = <3400000>;
anatop-enable-bit = <0>;
};
regulator-2p5 {
@ -672,6 +674,7 @@ regulator-2p5 {
anatop-min-bit-val = <0>;
anatop-min-voltage = <2100000>;
anatop-max-voltage = <2875000>;
anatop-enable-bit = <0>;
};
reg_arm: regulator-vddcore {
@ -797,19 +800,39 @@ gpc: gpc@020dc000 {
interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
<0 90 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
pu-supply = <&reg_pu>;
clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
<&clks IMX6QDL_CLK_GPU3D_SHADER>,
<&clks IMX6QDL_CLK_GPU2D_CORE>,
<&clks IMX6QDL_CLK_GPU2D_AXI>,
<&clks IMX6QDL_CLK_OPENVG_AXI>,
<&clks IMX6QDL_CLK_VPU_AXI>;
#power-domain-cells = <1>;
clocks = <&clks IMX6QDL_CLK_IPG>;
clock-names = "ipg";
pgc {
#address-cells = <1>;
#size-cells = <0>;
power-domain@0 {
reg = <0>;
#power-domain-cells = <0>;
};
pd_pu: power-domain@1 {
reg = <1>;
#power-domain-cells = <0>;
power-supply = <&reg_pu>;
clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
<&clks IMX6QDL_CLK_GPU3D_SHADER>,
<&clks IMX6QDL_CLK_GPU2D_CORE>,
<&clks IMX6QDL_CLK_GPU2D_AXI>,
<&clks IMX6QDL_CLK_OPENVG_AXI>,
<&clks IMX6QDL_CLK_VPU_AXI>;
};
};
};
gpr: iomuxc-gpr@020e0000 {
compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
reg = <0x020e0000 0x38>;
mux: mux-controller {
compatible = "mmio-mux";
#mux-control-cells = <1>;
};
};
iomuxc: iomuxc@020e0000 {
@ -1135,7 +1158,16 @@ audmux: audmux@021d8000 {
};
mipi_csi: mipi@021dc000 {
compatible = "fsl,imx6-mipi-csi2";
reg = <0x021dc000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 100 0x04>, <0 101 0x04>;
clocks = <&clks IMX6QDL_CLK_HSI_TX>,
<&clks IMX6QDL_CLK_VIDEO_27M>,
<&clks IMX6QDL_CLK_EIM_PODF>;
clock-names = "dphy", "ref", "pix";
status = "disabled";
};
mipi_dsi: mipi@021e0000 {
@ -1237,6 +1269,10 @@ ipu1: ipu@02400000 {
ipu1_csi0: port@0 {
reg = <0>;
ipu1_csi0_from_ipu1_csi0_mux: endpoint {
remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>;
};
};
ipu1_csi1: port@1 {

4
arch/arm/boot/dts/imx6qp-zii-rdu2.dts
View File

@ -41,8 +41,8 @@
/dts-v1/;
#include <imx6qp.dtsi>
#include <imx6qdl-zii-rdu2.dtsi>
#include "imx6qp.dtsi"
#include "imx6qdl-zii-rdu2.dtsi"
/ {
model = "ZII RDU2+ Board";

4
arch/arm/boot/dts/imx6qp.dtsi
View File

@ -120,6 +120,10 @@ &fec {
<0 119 IRQ_TYPE_LEVEL_HIGH>;
};
&gpc {
compatible = "fsl,imx6qp-gpc", "fsl,imx6q-gpc";
};
&ipu1 {
compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
fsl,prg = <&prg1>;

3
arch/arm/boot/dts/imx6sl.dtsi
View File

@ -530,6 +530,7 @@ regulator-1p1 {
anatop-min-bit-val = <4>;
anatop-min-voltage = <800000>;
anatop-max-voltage = <1375000>;
anatop-enable-bit = <0>;
};
regulator-3p0 {
@ -544,6 +545,7 @@ regulator-3p0 {
anatop-min-bit-val = <0>;
anatop-min-voltage = <2625000>;
anatop-max-voltage = <3400000>;
anatop-enable-bit = <0>;
};
regulator-2p5 {
@ -558,6 +560,7 @@ regulator-2p5 {
anatop-min-bit-val = <0>;
anatop-min-voltage = <2100000>;
anatop-max-voltage = <2850000>;
anatop-enable-bit = <0>;
};
reg_arm: regulator-vddcore {

4
arch/arm/boot/dts/imx6sx-nitrogen6sx.dts
View File

@ -296,7 +296,7 @@ t_lcd: t_lcd_default {
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>;
reset-gpio = <&gpio4 10 GPIO_ACTIVE_LOW>;
status = "okay";
};
@ -374,7 +374,7 @@ &usdhc3 {
cap-sdio-irq;
status = "okay";
brcmf: bcrmf@1 {
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&gpio7>;

8
arch/arm/boot/dts/imx6sx-sdb.dts
View File

@ -128,3 +128,11 @@ flash1: n25q256a@1 {
reg = <1>;
};
};
&reg_arm {
vin-supply = <&sw1a_reg>;
};
&reg_soc {
vin-supply = <&sw1a_reg>;
};

3
arch/arm/boot/dts/imx6sx.dtsi
View File

@ -587,6 +587,7 @@ regulator-1p1 {
anatop-min-bit-val = <4>;
anatop-min-voltage = <800000>;
anatop-max-voltage = <1375000>;
anatop-enable-bit = <0>;
};
regulator-3p0 {
@ -601,6 +602,7 @@ regulator-3p0 {
anatop-min-bit-val = <0>;
anatop-min-voltage = <2625000>;
anatop-max-voltage = <3400000>;
anatop-enable-bit = <0>;
};
regulator-2p5 {
@ -615,6 +617,7 @@ regulator-2p5 {
anatop-min-bit-val = <0>;
anatop-min-voltage = <2100000>;
anatop-max-voltage = <2875000>;
anatop-enable-bit = <0>;
};
reg_arm: regulator-vddcore {

2
arch/arm/boot/dts/imx6ul-opos6ul.dtsi
View File

@ -120,7 +120,7 @@ &usdhc2 {
#address-cells = <1>;
#size-cells = <0>;
brcmf: bcrmf@1 {
brcmf: wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpio2>;

2
arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts
View File

@ -78,7 +78,7 @@ &fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio &pinctrl_etnphy1_rst>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
phy-supply = <&reg_3v3_etn>;
phy-handle = <&etnphy1>;
status = "okay";

7
arch/arm/boot/dts/imx6ul-tx6ul.dtsi
View File

@ -173,8 +173,7 @@ reg_can_xcvr: regulator-canxcvr {
regulator-max-microvolt = <3300000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan_xcvr>;
gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
enable-active-low;
gpio = <&gpio3 5 GPIO_ACTIVE_LOW>;
};
reg_lcd_pwr: regulator-lcdpwr {
@ -308,7 +307,7 @@ &fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio &pinctrl_etnphy0_rst>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>;
phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
phy-supply = <&reg_3v3_etn>;
phy-handle = <&etnphy0>;
status = "okay";
@ -343,7 +342,7 @@ &fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2 &pinctrl_etnphy1_rst>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
phy-supply = <&reg_3v3_etn>;
phy-handle = <&etnphy1>;
status = "disabled";

1
arch/arm/boot/dts/imx6ul.dtsi
View File

@ -542,6 +542,7 @@ reg_3p0: regulator-3p0 {
anatop-min-bit-val = <0>;
anatop-min-voltage = <2625000>;
anatop-max-voltage = <3400000>;
anatop-enable-bit = <0>;
};
reg_arm: regulator-vddcore {

2
arch/arm/boot/dts/imx7-colibri.dtsi
View File

@ -43,7 +43,7 @@
/ {
bl: backlight {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
pwms = <&pwm1 0 5000000 0>;
};
reg_module_3v3: regulator-module-3v3 {

6
arch/arm/boot/dts/imx7d-nitrogen7.dts
View File

@ -67,7 +67,7 @@ backlight-j9 {
backlight-j20 {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
pwms = <&pwm1 0 5000000 0>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
status = "okay";
@ -279,7 +279,7 @@ &i2c2 {
status = "okay";
rtc@68 {
compatible = "rv4162";
compatible = "microcrystal,rv4162";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_rv4162>;
reg = <0x68>;
@ -738,7 +738,7 @@ MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x14
pinctrl_wdog1: wdog1grp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_B 0x75
MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x75
>;
};
};

403
arch/arm/boot/dts/imx7d-pico.dts Normal file
View File

@ -0,0 +1,403 @@
/*
* Copyright 2017 NXP
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx7d.dtsi"
/ {
model = "Technexion Pico i.MX7D Board";
compatible = "technexion,imx7d-pico", "fsl,imx7d";
memory {
reg = <0x80000000 0x80000000>;
};
reg_2p5v: regulator-2p5v {
compatible = "regulator-fixed";
regulator-name = "2P5V";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;
};
reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg2_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_vref_1v8: regulator-vref-1v8 {
compatible = "regulator-fixed";
regulator-name = "vref-1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "imx7-sgtl5000";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&dailink_master>;
simple-audio-card,frame-master = <&dailink_master>;
simple-audio-card,cpu {
sound-dai = <&sai1>;
};
dailink_master: simple-audio-card,codec {
sound-dai = <&codec>;
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
};
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
<&clks IMX7D_ENET1_TIME_ROOT_CLK>;
assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
assigned-clock-rates = <0>, <100000000>;
phy-mode = "rgmii";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
status = "okay";
};
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
codec: sgtl5000@0a {
#sound-dai-cells = <0>;
reg = <0x0a>;
compatible = "fsl,sgtl5000";
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
VDDA-supply = <&reg_2p5v>;
VDDIO-supply = <&reg_vref_1v8>;
};
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
pmic: pfuze3000@08 {
compatible = "fsl,pfuze3000";
reg = <0x08>;
regulators {
sw1a_reg: sw1a {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
/* use sw1c_reg to align with pfuze100/pfuze200 */
sw1c_reg: sw1b {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1475000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw2_reg: sw2 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1850000>;
regulator-boot-on;
regulator-always-on;
};
sw3a_reg: sw3 {
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1650000>;
regulator-boot-on;
regulator-always-on;
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-boot-on;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-boot-on;
regulator-always-on;
};
vgen1_reg: vldo1 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen2_reg: vldo2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen3_reg: vccsd {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen4_reg: v33 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen5_reg: vldo3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen6_reg: vldo4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
};
&sai1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>;
assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
<&clks IMX7D_SAI1_ROOT_CLK>;
assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
assigned-clock-rates = <0>, <24576000>;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
status = "okay";
};
&usbotg1 {
vbus-supply = <&reg_usb_otg1_vbus>;
status = "okay";
};
&usbotg2 {
vbus-supply = <&reg_usb_otg2_vbus>;
dr_mode = "host";
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
assigned-clock-rates = <400000000>;
bus-width = <8>;
no-1-8-v;
fsl,tuning-step = <2>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_enet1: enet1grp {
fsl,pins = <
MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3
MX7D_PAD_SD2_WP__ENET1_MDC 0x3
MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX7D_PAD_UART1_TX_DATA__I2C1_SDA 0x4000007f
MX7D_PAD_UART1_RX_DATA__I2C1_SCL 0x4000007f
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f
MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f
>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <
MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f
MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f
MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30
MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x79
MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x79
>;
};
pinctrl_usbotg1_pwr: usbotg_pwr {
fsl,pins = <
MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 0x14
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x59
MX7D_PAD_SD3_CLK__SD3_CLK 0x19
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
>;
};
};
&iomuxc_lpsr {
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
>;
};
};

6
arch/arm/boot/dts/imx7d-pinfunc.h
View File

@ -17,9 +17,9 @@
#define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
#define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
#define MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
#define MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
#define MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
#define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
#define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
#define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
#define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
#define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
#define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0

133
arch/arm/boot/dts/imx7d-sdb.dts
View File

@ -52,47 +52,70 @@ memory {
reg = <0x80000000 0x80000000>;
};
regulators {
compatible = "simple-bus";
spi4 {
compatible = "spi-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi4>;
gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>;
gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
num-chipselects = <1>;
#address-cells = <1>;
#size-cells = <0>;
reg_usb_otg1_vbus: regulator@0 {
compatible = "regulator-fixed";
extended_io: gpio-expander@0 {
compatible = "fairchild,74hc595";
gpio-controller;
#gpio-cells = <2>;
reg = <0>;
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
enable-active-high;
registers-number = <1>;
spi-max-frequency = <100000>;
};
};
reg_usb_otg2_vbus: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "usb_otg2_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_can2_3v3: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "can2-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 7 GPIO_ACTIVE_LOW>;
};
reg_usb_otg2_vbus: regulator-usb-otg1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg2_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_vref_1v8: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "vref-1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reg_can2_3v3: regulator-can2-3v3 {
compatible = "regulator-fixed";
regulator-name = "can2-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 7 GPIO_ACTIVE_LOW>;
};
reg_vref_1v8: regulator-vref-1v8 {
compatible = "regulator-fixed";
regulator-name = "vref-1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reg_brcm: regulator-brcm {
compatible = "regulator-fixed";
gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-name = "brcm_reg";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_brcm_reg>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
startup-delay-us = <200000>;
};
};
@ -328,6 +351,11 @@ timing0: timing0 {
};
};
&pcie {
reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
@ -342,6 +370,15 @@ &uart1 {
status = "okay";
};
&uart6 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart6>;
assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
uart-has-rtscts;
status = "okay";
};
&usbotg1 {
vbus-supply = <&reg_usb_otg1_vbus>;
status = "okay";
@ -363,6 +400,19 @@ &usdhc1 {
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
wakeup-source;
keep-power-in-suspend;
non-removable;
vmmc-supply = <&reg_brcm>;
fsl,tuning-step = <2>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
@ -387,6 +437,12 @@ &iomuxc {
pinctrl-0 = <&pinctrl_hog>;
imx7d-sdb {
pinctrl_brcm_reg: brcmreggrp {
fsl,pins = <
MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x14
>;
};
pinctrl_ecspi3: ecspi3grp {
fsl,pins = <
MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2
@ -554,7 +610,6 @@ MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x59 /* WL_REG_ON */
>;
};
@ -634,7 +689,7 @@ MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b
&iomuxc_lpsr {
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_B 0x74
MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
>;
};
@ -642,5 +697,13 @@ pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x110b0
>;
pinctrl_spi4: spi4grp {
fsl,pins = <
MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59
MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59
MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59
>;
};
};
};

37
arch/arm/boot/dts/imx7d.dtsi
View File

@ -42,6 +42,7 @@
*/
#include "imx7s.dtsi"
#include <dt-bindings/reset/imx7-reset.h>
/ {
cpus {
@ -127,6 +128,42 @@ fec2: ethernet@30bf0000 {
fsl,num-rx-queues=<3>;
status = "disabled";
};
pcie: pcie@0x33800000 {
compatible = "fsl,imx7d-pcie", "snps,dw-pcie";
reg = <0x33800000 0x4000>,
<0x4ff00000 0x80000>;
reg-names = "dbi", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000 /* downstream I/O */
0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */
num-lanes = <1>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>,
<&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,
<&clks IMX7D_PCIE_PHY_ROOT_CLK>;
clock-names = "pcie", "pcie_bus", "pcie_phy";
assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>,
<&clks IMX7D_PCIE_PHY_ROOT_SRC>;
assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
<&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
fsl,max-link-speed = <2>;
power-domains = <&pgc_pcie_phy>;
resets = <&src IMX7_RESET_PCIEPHY>,
<&src IMX7_RESET_PCIE_CTRL_APPS_EN>;
reset-names = "pciephy", "apps";
status = "disabled";
};
};
&ca_funnel_ports {

3
arch/arm/boot/dts/imx7s-warp.dts
View File

@ -295,6 +295,7 @@ &usdhc3 {
assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
assigned-clock-rates = <400000000>;
bus-width = <8>;
no-1-8-v;
fsl,tuning-step = <2>;
non-removable;
status = "okay";
@ -442,7 +443,7 @@ MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1b
&iomuxc_lpsr {
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_B 0x74
MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
>;
};
};

50
arch/arm/boot/dts/imx7s.dtsi
View File

@ -42,6 +42,7 @@
*/
#include <dt-bindings/clock/imx7d-clock.h>
#include <dt-bindings/power/imx7-power.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@ -119,7 +120,7 @@ soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&intc>;
interrupt-parent = <&gpc>;
ranges;
funnel@30041000 {
@ -301,6 +302,7 @@ intc: interrupt-controller@31001000 {
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
#interrupt-cells = <3>;
interrupt-controller;
interrupt-parent = <&intc>;
reg = <0x31001000 0x1000>,
<0x31002000 0x2000>,
<0x31004000 0x2000>,
@ -309,6 +311,7 @@ intc: interrupt-controller@31001000 {
timer {
compatible = "arm,armv7-timer";
interrupt-parent = <&intc>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
@ -488,7 +491,8 @@ iomuxc: iomuxc@30330000 {
};
gpr: iomuxc-gpr@30340000 {
compatible = "fsl,imx7d-iomuxc-gpr", "syscon";
compatible = "fsl,imx7d-iomuxc-gpr",
"fsl,imx6q-iomuxc-gpr", "syscon";
reg = <0x30340000 0x10000>;
};
@ -516,6 +520,7 @@ reg_1p0d: regulator-vdd1p0d {
anatop-min-bit-val = <8>;
anatop-min-voltage = <800000>;
anatop-max-voltage = <1200000>;
anatop-enable-bit = <0>;
};
};
@ -563,6 +568,27 @@ src: src@30390000 {
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
#reset-cells = <1>;
};
gpc: gpc@303a0000 {
compatible = "fsl,imx7d-gpc";
reg = <0x303a0000 0x10000>;
interrupt-controller;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <3>;
interrupt-parent = <&intc>;
#power-domain-cells = <1>;
pgc {
#address-cells = <1>;
#size-cells = <0>;
pgc_pcie_phy: pgc-power-domain@IMX7_POWER_DOMAIN_PCIE_PHY {
#power-domain-cells = <0>;
reg = <IMX7_POWER_DOMAIN_PCIE_PHY>;
power-supply = <&reg_1p0d>;
};
};
};
};
aips2: aips-bus@30400000 {
@ -609,7 +635,7 @@ pwm1: pwm@30660000 {
clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
<&clks IMX7D_PWM1_ROOT_CLK>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};
@ -620,7 +646,7 @@ pwm2: pwm@30670000 {
clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
<&clks IMX7D_PWM2_ROOT_CLK>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};
@ -631,7 +657,7 @@ pwm3: pwm@30680000 {
clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
<&clks IMX7D_PWM3_ROOT_CLK>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};
@ -642,7 +668,7 @@ pwm4: pwm@30690000 {
clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
<&clks IMX7D_PWM4_ROOT_CLK>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};
@ -934,8 +960,8 @@ usdhc1: usdhc@30b40000 {
compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
reg = <0x30b40000 0x10000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_CLK_DUMMY>,
<&clks IMX7D_CLK_DUMMY>,
clocks = <&clks IMX7D_IPG_ROOT_CLK>,
<&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
<&clks IMX7D_USDHC1_ROOT_CLK>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
@ -946,8 +972,8 @@ usdhc2: usdhc@30b50000 {
compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
reg = <0x30b50000 0x10000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_CLK_DUMMY>,
<&clks IMX7D_CLK_DUMMY>,
clocks = <&clks IMX7D_IPG_ROOT_CLK>,
<&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
<&clks IMX7D_USDHC2_ROOT_CLK>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
@ -958,8 +984,8 @@ usdhc3: usdhc@30b60000 {
compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
reg = <0x30b60000 0x10000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_CLK_DUMMY>,
<&clks IMX7D_CLK_DUMMY>,
clocks = <&clks IMX7D_IPG_ROOT_CLK>,
<&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
<&clks IMX7D_USDHC3_ROOT_CLK>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;

90
arch/arm/boot/dts/ls1021a.dtsi
View File

@ -75,7 +75,7 @@ cpu0: cpu@f00 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0xf00>;
clocks = <&cluster1_clk>;
clocks = <&clockgen 1 0>;
#cooling-cells = <2>;
};
@ -83,10 +83,17 @@ cpu1: cpu@f01 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0xf01>;
clocks = <&cluster1_clk>;
clocks = <&clockgen 1 0>;
};
};
sysclk: sysclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "sysclk";
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
@ -165,7 +172,7 @@ sata: sata@3200000 {
<0x0 0x20220520 0x0 0x4>;
reg-names = "ahci", "sata-ecc";
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&platform_clk 1>;
clocks = <&clockgen 4 1>;
dma-coherent;
status = "disabled";
};
@ -216,41 +223,10 @@ sec_jr3: jr@40000 {
};
clockgen: clocking@1ee1000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x1ee1000 0x10000>;
sysclk: sysclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "sysclk";
};
cga_pll1: pll@800 {
compatible = "fsl,qoriq-core-pll-2.0";
#clock-cells = <1>;
reg = <0x800 0x10>;
clocks = <&sysclk>;
clock-output-names = "cga-pll1", "cga-pll1-div2",
"cga-pll1-div4";
};
platform_clk: pll@c00 {
compatible = "fsl,qoriq-core-pll-2.0";
#clock-cells = <1>;
reg = <0xc00 0x10>;
clocks = <&sysclk>;
clock-output-names = "platform-clk", "platform-clk-div2";
};
cluster1_clk: clk0c0@0 {
compatible = "fsl,qoriq-core-mux-2.0";
#clock-cells = <0>;
reg = <0x0 0x10>;
clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
clock-output-names = "cluster1-clk";
};
compatible = "fsl,ls1021a-clockgen";
reg = <0x0 0x1ee1000 0x0 0x1000>;
#clock-cells = <2>;
clocks = <&sysclk>;
};
tmu: tmu@1f00000 {
@ -338,7 +314,7 @@ dspi0: dspi@2100000 {
reg = <0x0 0x2100000 0x0 0x10000>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dspi";
clocks = <&platform_clk 1>;
clocks = <&clockgen 4 1>;
spi-num-chipselects = <6>;
big-endian;
status = "disabled";
@ -351,7 +327,7 @@ dspi1: dspi@2110000 {
reg = <0x0 0x2110000 0x0 0x10000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dspi";
clocks = <&platform_clk 1>;
clocks = <&clockgen 4 1>;
spi-num-chipselects = <6>;
big-endian;
status = "disabled";
@ -364,7 +340,7 @@ i2c0: i2c@2180000 {
reg = <0x0 0x2180000 0x0 0x10000>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&platform_clk 1>;
clocks = <&clockgen 4 1>;
status = "disabled";
};
@ -375,7 +351,7 @@ i2c1: i2c@2190000 {
reg = <0x0 0x2190000 0x0 0x10000>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&platform_clk 1>;
clocks = <&clockgen 4 1>;
status = "disabled";
};
@ -386,7 +362,7 @@ i2c2: i2c@21a0000 {
reg = <0x0 0x21a0000 0x0 0x10000>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&platform_clk 1>;
clocks = <&clockgen 4 1>;
status = "disabled";
};
@ -479,7 +455,7 @@ lpuart1: serial@2960000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2960000 0x0 0x1000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&platform_clk 1>;
clocks = <&clockgen 4 1>;
clock-names = "ipg";
status = "disabled";
};
@ -488,7 +464,7 @@ lpuart2: serial@2970000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2970000 0x0 0x1000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&platform_clk 1>;
clocks = <&clockgen 4 1>;
clock-names = "ipg";
status = "disabled";
};
@ -497,7 +473,7 @@ lpuart3: serial@2980000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2980000 0x0 0x1000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&platform_clk 1>;
clocks = <&clockgen 4 1>;
clock-names = "ipg";
status = "disabled";
};
@ -506,7 +482,7 @@ lpuart4: serial@2990000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2990000 0x0 0x1000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&platform_clk 1>;
clocks = <&clockgen 4 1>;
clock-names = "ipg";
status = "disabled";
};
@ -515,7 +491,7 @@ lpuart5: serial@29a0000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x29a0000 0x0 0x1000>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&platform_clk 1>;
clocks = <&clockgen 4 1>;
clock-names = "ipg";
status = "disabled";
};
@ -524,7 +500,7 @@ wdog0: watchdog@2ad0000 {
compatible = "fsl,imx21-wdt";
reg = <0x0 0x2ad0000 0x0 0x10000>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&platform_clk 1>;
clocks = <&clockgen 4 1>;
clock-names = "wdog-en";
big-endian;
};
@ -534,8 +510,8 @@ sai1: sai@2b50000 {
compatible = "fsl,vf610-sai";
reg = <0x0 0x2b50000 0x0 0x10000>;
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&platform_clk 1>, <&platform_clk 1>,
<&platform_clk 1>, <&platform_clk 1>;
clocks = <&clockgen 4 1>, <&clockgen 4 1>,
<&clockgen 4 1>, <&clockgen 4 1>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
dma-names = "tx", "rx";
dmas = <&edma0 1 47>,
@ -548,8 +524,8 @@ sai2: sai@2b60000 {
compatible = "fsl,vf610-sai";
reg = <0x0 0x2b60000 0x0 0x10000>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&platform_clk 1>, <&platform_clk 1>,
<&platform_clk 1>, <&platform_clk 1>;
clocks = <&clockgen 4 1>, <&clockgen 4 1>,
<&clockgen 4 1>, <&clockgen 4 1>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
dma-names = "tx", "rx";
dmas = <&edma0 1 45>,
@ -569,16 +545,16 @@ edma0: edma@2c00000 {
dma-channels = <32>;
big-endian;
clock-names = "dmamux0", "dmamux1";
clocks = <&platform_clk 1>,
<&platform_clk 1>;
clocks = <&clockgen 4 1>,
<&clockgen 4 1>;
};
dcu: dcu@2ce0000 {
compatible = "fsl,ls1021a-dcu";
reg = <0x0 0x2ce0000 0x0 0x10000>;
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&platform_clk 0>,
<&platform_clk 0>;
clocks = <&clockgen 4 0>,
<&clockgen 4 0>;
clock-names = "dcu", "pix";
big-endian;
status = "disabled";

2
arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
View File

@ -78,6 +78,7 @@ switch0: switch@0 {
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <2>;
eeprom-length = <512>;
ports {
#address-cells = <1>;
@ -163,6 +164,7 @@ switch1: switch@0 {
interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <2>;
eeprom-length = <512>;
ports {
#address-cells = <1>;